CMOS-4

CMOS-4 NEC | Alldatasheet

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Electrical Characteristics

The electrical characteristics of a particular gate array Table 5-1. Absolute Maxium Ratings design are determined after evaluation of samples. Ta=+25°C This section describes the standard characteristics by Power supply voltage, Vop —0.5to +7.0V a series of tables and graphs. input voltage, V) =05 Vio Vop +05V Tables Input current, |; 40 mA tI 40 mA Exposure to the absolute maximum ratings in table 5-1 Outputcurentig Am current 10 ul for extended periods may affect device reliability, Perating temperature, Topr 40 to +85°C exceeding the ratings could cause permanentdamage. _Storage temperature, Tstg —65 to +150°C The gate array device should not be operated under conditions Outside those recommended in table 5-2. Tapie 5-2. Recommended Operating Conditions interface is with a CMOS-level or TTL-level device. me Level TTL Level Parameter Symbol Min Max Min = Max Unit . Tables 5-3 and 5-4 show dc characteristics and ac Oe er | characteristics. Some of these signal specifications are voltage” Yoo 45 55 475 525 OV . dependent on an external CMOS or TTL interface, Ambien aR oe also. If all input and output signals interface with entre Ta 40 +850 0 +70 °C CMOS-level devices, the supply voltage and ambient “2™Perare temperature limits of the gate array chip are: Low-level Vit 0 03Vp 0 08 Vv input voltage | Vpp = 5.0 volts +10% Highlevel Vm 07 Vp Vag vg igh-level Vin O.7Vp Vpp 20 Vpn V Ta = —40 to +85°C input voltage If one or more of the signals interface with TTL-level _Input rise or tr, te 0 10 0 10 ous devices: fall time (1) _ Positive Schmitt Vp 1.8 4.0 12 23 v Von = 5.0 volts +5% trigger voltage (2) Ta = —40 to +85°C a Negative Schmitt Vy 06 34 06 1.8 Vv Table 5-5 lists the maximum internal capacitance that __ trigger voltage (2) you may expect at the signal ports of the gate array Hysteresis Vu 03 15 03 15 Vv chip. voltage (2) Note: (1) For Schmitt trigger input buffers. (2) Vpp = 5.0V 5-1

1.5-Micron NEC CMOS-4 and -4A Table 5-3. DC Characteristics Table 5-4. AC Characteristics Vpp = 5 V +10%; Ta = —40 to +85°C. Vpp = 5 V +10%; Ta = —40 to +85°C Limits Limits Parameter ‘Symbol Min Typ Max Unit Test Conditions Parameter ‘Symbol Min Typ Max Unit Test Conditions Static current It 0.1 200 wA Vj=Vppor GND Max operating fmax 70 MHz _ Internal toggle; (Note 1) frequency (75) FIO=1 Input current (Note With pull-up | 2 80 250 wA V\\=GND internal gate L=3mm sla ia \\ 25 80 250 uA i= Vo Delay time, tep 2.0 ns Sang input buffer restr 198 10 #A Mi=Voper SND Delay time, trp 40 ns 0, = 15 pF (Note 1) output buffer Dynamic current pp 3 uA Per cell at 1 MHz Outputrisetime tr 32s Off-state loz 10 uA Vo=Vpporanp ‘Mutputfalltime te ms output leakage Note: current Fi i theses is for TTL level interface. Vpp =5 V Low-level output current (Note 2) o isuandi= 400 t85°C. eP Buffer FOOT ot 40 11 MA Vo. =04V (Note 3) (4.3) Table 5-5. Input/Output Capacitance Butfer F002 Ip és 5 mA ints — Terminal Symbol L Mi Te Buffer F003 I~ 2B mA Terminal ___ Symbol Typ_Max_Unit_Test Conditions _ (Note 4) (13) Input Cin 10 PF Vpp = Vi=0V; High-level output current (Note 2) Output Court 30 pr f= 1MHe Buffer F001 — low 40 8 MA Vou = Von — v0 Cio 35 pF (Note 3) (43) o4V — Buffer F002 Io eo) i] mA Graphs buller FO) gg Figures 5-1 through 5-5 are graphs depicting the (Note 4) m3) operating characteristics. Low-level Vor 01 Vi Ip=OmA Figure Description outputvoltage 54 Input buffers (Vo vs Vi) High-level VoH Yoo Vv 5-2 Input buffers (V, vs Vpp) output voltage 5-3 Input buffers (V, vs Ta) Note: 5-4 Internal gate delay time (1) Not applicable to blocks with a pull-up or pull-down resistor or 5-5 Output buffers (also see Section 4) to oscillator blocks. (2) Current values in parentheses are for TTL level interface. Vpp = 5 V £5% and Ta = —40 to +85°C. (3) Current values for F001 are applicable to these low-drive output buffers: B003, BO04, BOOB BOD3, BOD4, BOD BOU3, BOU4, BOUS EXT1, EXT2, EXT3, EXT4 (4) Current values for FO03 are applicable to these high-drive output buffers: B005, B006, BOOS BODS, BOD6, BODS BOUS, BOU, BOUS EXTS, EXT6, EXT7, EXTS 5-2

N. j (Cc Section 5 Figure 5-1. Input Buffers; Output Voltage vs Input Voltage CMOS Input TTL Input 6 6 Vop = 5.5V rt aa a | - =45V Cn =5.0¥ sq oa sal. | psy z s $ | 3 3 Fi 2 & 6? Cd oO | & : ° 3 ° F o 1 2 3 4 ° 1 2 3 4 Input Voltage [V] Input Voltage (V] Figure 5-2. Input Buffers; Threshold Voltage vs Supply Voltage CMOS Input CMOS Schmitt Trigger Input 4 4 ue fee] || =) >3 rs 3 | + 3 3 S s 2 o : i ey Fy ° 3 0 3 Supply Voltage (V] Supply Voltage [V] TTL Input TTL Schmitt Trigger Input 4 4 <3 <3 = = $2 ca 2 3 = z Fi m4 o 2 0 2 ‘Supply Voltage [V] ‘Supply Voltage [V] 5-3

1.5-Micron NEC CMOS-4 and -4A Figure 5-3. Input Buffers; Threshold Voltage vs Ambient Temperature CMOS Input CMOS Schmitt Trigger Input = | =° | Fy 3? 3? 2 2 H iH ey Fy 3 8

0 FE o 2

Ambient Temperature [°C] Ambient Temperature [°C] TTL Input TTL Schmitt Trigger Input 4 4 | Vop=5.0V & ry 2 t | $, é _ _ _ = ol | - 3 | 3 C Vin é é Vie = ! oo * Fy 4 — 1 aa ; i 3 | < | | 8 | 3 0 2 2 ° z 50 0) 50 100 50 o 50 100 Ambient Temperature [°C] Ambient Temperature {°C} 5-4

Figure 5-4. Internal Gate Delay Time Delay Time vs Supply Voltage Delay Time vs Ambient Temperature

4 T +25°C 4

A “ ! Fan-Ins = 2 Fan-Ins =2 } Fan-Outs = 3 Fan-Outs = 3 i Yop =5V | Le jth = 3 t | z z | g { A | NOR z —_| NOR T NAND 8 NAND. i ee re 1 1 — — ae : oO 8 0 z 4.0 45 5.0 5.5 60 50 0 50 100 ‘Supply Voltage [V} Ambient Temperature [°C] Delay Time vs Fan-Outs Ta = +25°C Fan-ins = 2 Length = 3mm — -— — + — NOR g NAND: E i 1 = 24 —- 4---- t = Fs 1 4... —— 5 1 2 3 4 5 6 Fan-Outs 5-5

1.5-Micron NEC CMOS-4 and -4A Figure 5-5. Output Buffers (FO01); Output Current vs Output Voltage P-Channel N-Channel ° ° L_—| 10 { . _ Yo 40 1 | | < Sov Yo Fs =Sov. ~ = 45 £.i =45V 3 nn \\ en - ——T =o pe 5 \\ a : ~30 — a | Fs 20 - Yi 2 ‘ Es é i 3 J 40 + - $ 10 Vy y $

50 Ha z

Voo- 4 Vop- 3 Voo~2 Voo—1 Voo 0 1 2 3 4 Output Voltage (V) Output Voltage [V) 5-6