CM4072 CALMIRCO | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 11

Technical content

Features

  • Low noise regulator with integrated charge pump voltage-booster
  • 5V output with input vo ltage as low as 2.8V
  • Charge pump can also power an external LDO
  • Low noise in 20Hz to 20kHz audio band
  • Up to 200mA continuous output current
  • Low operating and shutdown currents
  • Stable with low-ESR cera mic or tantalum capaci- tors
  • Over-current and over -temperature protection
  • 10-lead TDFN package, 3mm x 3mm
  • Lead-free versions available

Applications

  • White backlight LEDs for main display in wireless handsets and LCD modules
  • Power flash LEDs for camera phones
  • 3.3V to 5V conversion in PCMCIA cards, PCI Express Cards, other applications needing 5V
  • 5V analog supply for audio codec in notebook computers, PDAs, MP3 players, etc Product Description The CM4072 Low-noise Charge Pump / LDO Regulator is designed to power white backlight LEDs used in main dis- plays or camera flash LEDs in wireless handsets. The 5V output provides up to 100mA continuous current for input voltages from 3.0V to 5.5V, and up to 200mA for a nar- rower range. This is accomplished with an integrated charge pump that boosts the input voltage before feeding it to an internal LDO linear regulator. The CM4072 oper- ates with excellent power supply ripple rejection while maintaining good power efficiency. The device utilizes two external capacitors and operates at 250kHz. Separate analog and digital ground pins are provided for the charge pump and the rest of the circuitry to eliminate ground noise feed-through from the charge pump to the regulated output. The CM4072 provides both overcurrent and thermal over- load protection. Two enable inputs provide flexibility in powering down the device. To maximize power saving in shutdown mode, both enable inputs should be at a logic low level. For applications that require the 5V output to be re-established with minimum delay after shutdown, the charge pump can be left enabled while the regulator is disabled. The CMOS LDO regulator features low quies- cent current even at full load, making it very suitable for power sensitive applications. A bypass pin is provided to further minimize noise by con- necting an external capacitor between this pin and ground. The CM4072 is available in a 10-lead TDFN package, with optional lead-free finishing, and is ideal for space crit- ical applications Typical Application Sim plified Block Diagram CM4072 TDFN-10 VIN 0.1μF* CS 2.2μF +CBYP CP PWM *Optional 1μF CHARGE PUMP CS CP- CP+ CP CS VCP DGND VIN EN_CP EN_LDO VREF LDO BYP GND VOUT ENABLE CHARGE PUMP CONTROL CIRCUIT ENABLE LDO 0-200kHz

© 2005 California Micro Devices Corp. All rights reserved. CM4072 PRELIMINARY PACKAGE / PINOUT DIAGRAM Note: This drawing is not to scale. CM4072-50DF/DE

10 Lead TDFN Package

(Pins Up View) TOP VIEW (Pins Down View) PIN DESCRIPTIONS LEAD(S) NAME DESCRIPTION 1 DGND Ground for the charge pump circuit. This should be connected to the system (noisy) ground. 2V IN Input power source for the device. Since the charge pump draws current in pulses at the 250kHz internal clock frequency, a low-ESR input decoupling capacitor is usually required close to this pin to ensure low noise operation. 3V CP Charge pump output which is connected to the external reservoir capacitor CS. This should be a low-ESR capacitor. When the voltage on this pin reaches about 5.8V then the charge pump pauses until the voltage on this pin drops to about 5.7V. This gives rise to at least 100mV of 'rip- ple' (the frequency and amplitude of this ripple depends upon values of CP and CS and also the ESR of CS). 4 GND Ground reference for all internal circuits exce pt the charge pump. This pin should be connected to a "clean" low-noise analog ground 5 BYP Bypass input connected to the internal volt age reference of the LDO regulator. An external bypass capacitor CBYP of 0.1uF is recommended to minimize internal voltage reference noise and maximize power supply ripple rejection. 6, 7 EN_LDO, EN_CP EN_LDO (pin 6) and EN_CP (pin 7) are active-high TTL-level logic inputs to enable the linear regulator and charge pump according to the following truth table: 8V OUT The regulated output. An output capacitor may be added to improve noise and load-transient response. When the LDO regulator is disabled, an internal pull-down with a nominal resistance of 50 ohms is activated to discharge the VOUT rail to GND 9, 10 CP+, CP- CP+ (pin 9) and CP- (pin 10) are us ed to connect the external "flying" capacitor CP to the charge pump. The charge stored in CP is transferred to the reservoir capacitor CS at the 250kHz inter- nal clock rate. EN_CP (Pin 7) EN_LDO (Pin 6) CHARGE PUMP REGULATOR 1 1 Enabled Enabled 1 0 Enabled Disabled 0 1 Disabled Disabled 0 0 Disabled Disabled

© 2005 California Micro Devices Corp. All rights reserved. CM4072 PRELIMINARY

Ordering Information

Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Specifications PART NUMBERING INFORMATION Leads Package Standard Finish Lead-free Finish Ordering Part Number1 Part Marking Ordering Part Number1 Part Marking

10 TDFN-10 CM4072-50DF CM407 250DF CM4072-50DE CM407 250DE

ESD Protection (HBM) ±2000 V VEN Logic Input Voltage (V IN + 0.5) to (GND - 0.5) V VIN, VOUT Pin Voltages +5.5 to (GND - 0.5) V Storage Temperature Range -65 to +150 °C Operating Temperature Range Ambient Junction -40 to +85 -40 to +150 STANDARD OPERATING CONDITIONS PARAMETER VALUE UNITS Input Voltage Range (VIN) 2.8 to 5.5 V Ambient Operating Temperature -40 to +85 °C θJA of TDFN package on PCB 200 (approx.) °C/W Output Load Current (IOUT) 0 to 200 mA CBYP 0.1 μF COUT 0 to 100 μF RECOMMENDED EXTERNAL COMPONENTS DEVICE VALUE UNITS CS 2.2 μF CP 1.0 μF

© 2005 California Micro Devices Corp. All rights reserved. CM4072 PRELIMINARY Specifications (cont’d) Note 1: Unless otherwise noted, electrical oper ating characteristics are specified with T A = 0 to 70°C, V IN = 5.0V, I OUT =100mA, COUT=10μF, CP = 1μF, CS = 10μF. Note 2: These parameters are guarant eed by design and characterization. ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCP Charge Pump Output Voltage V OUT = 5V, 1mA < IOUT < 100mA 5.5 5.8 7 V VOUT Regulator Output Voltage V IN = 4.0V, 1mA < IOUT < 100mA 4.85 5.15 V VR LOAD Load Regulation I OUT = 1mA to 100mA 0.2 % VR LINE Line Regulation Vary V IN from 3.0V to 5.0V 0.02 % RDISCHG VOUT Discharge Resistance LDO regulator disabled, EN_LDO grounded, VIN = 5V 500 Ω IGND LDO Regulator Ground Current via the GND pin Shutdown (EN_LDO grounded) 1 10 μA Regulator Enabled, IOUT = 0mA 180 μA Regulator Enabled, IOUT = 100mA 180 μA IDGND Charge Pump Shutdown Current via DGND pin EN_CP grounded, VIN = 5V 1 10 μA PSRR Power Supply Ripple Rejection I OUT = 100mA, CBYP =0.1μF, Note 2 f = 100Hz f = 10kHz dB dB eNO Output Voltage Noise BW=22Hz-22kHz, C OUT = 10μF, CBYP = 0.1μF, IOUT = 100mA, Note 2 35 μVrms BW=22Hz-22kHz, CP = 1μF, CS =3μF, COUT = CBYP = 0.1μF, IOUT = 100mA, Note 2 38 μVrms VIH EN_CP, EN_LDO Input High Threshold VIN = 5.0V 2.0 V VIL EN_CP, EN_LDO Input Low Threshold VIN = 5.0V 0.5 V ILIM Overload Current Limit LDO Only, Note 2 200 300 mA ISC Output Short Circuit Current LDO Only, Note 2 50 mA TJSD Thermal Shutdown Junction Temperature 170 °C THYS Thermal Shutdown Hysteresis 25 °C

© 2005 California Micro Devices Corp. All rights reserved. CM4072 PRELIMINARY

Application Information

The charge pump internal oscillation frequency is about 250kHz. However, this is the continuous, free- running frequency, which is usually only seen while the charge pump is powering up. Such a sawtooth 'ripple' waveform on CS can have a much lower frequency than 250kHz. This mode of operation is necessary to conserve power. If it were not done this way, then a much larger package with heatsink would be required. The frequency of this 'ripple' is affected by V IN, IOUT, CS capacitor value and CP capacitor value. Guidelines for External Capacitors (1) To find C P: specify value of V IN, and highest value of IOUT: If VIN= 3.3V +/- 5%, then minimum value of CP (µF) = IOUT (mA) / 85. If VIN= 5.0V +/- 10%, then minimum value of CP (µF) = IOUT (mA) / 700 (2) The VIN decoupling capacitor, C IN, should typically be much greater than CP to prevent voltage droop dur- ing CP charging. Excessive glitches on V IN will affect the output voltage V OUT. C IN is typically 10X greater than CP. (3) C S should be small to ensure that the ripple fre- quency is high, but at least 2x greater than C P, other- wise the ripple amplitude will be very high. Reducing the value of CS will increase the ripple frequency. Examples of C S ripple frequencies (C S=10μF, TA=25°C) are shown in following tables: (4) COUT, the optional V OUT capacitor, helps minimize noise and improve load regulation; 0.1µF to 100µF is recommended. (5) CBYP, the optional bypass capacitor helps reduce noise in the LDO; 0.1µF is recommended. After choosing external component values, check in- system performance (at min/max V IN, max tempera- ture, and min/max IOUT). See the troubleshooting guide on next page for tips if there are problems. Charge Pump Noise The charge pump is 'digital' in operation and can pro- duce digital noise at both the free-running frequency and at the ripple frequency. To minimize noise, PCB grounding is important! This part requires short, low-impedance ground connec- tions for DGND (pin 1), GND (pin 4), the V IN decou- pling capacitor (pin 2), the C S capacitor (pin 3), the Bypass decoupling capacitor (pin 5) and the V OUT decoupling capacitor (pin 8) . All decoupling capacitors and the C S capacitor should be low-ESR ceramics. The CP capacitor needs to be low-ESR. CP = 0.47μF VIN IOUT CS Frequency 3.14 15mA 46kHz 3.60 15mA 35kHz 4.50 70mA 76kHz 5.50 70mA 56kHz CP = 1.0μF VIN IOUT CS Frequency 3.14 100mA 250kHz 3.60 100mA 110kHz 4.50 100mA 67kHz 5.50 100mA 49kHz

© 2005 California Micro Devices Corp. All rights reserved. CM4072 PRELIMINARY Efficiency The power efficiency in % of the combined charge pump and LDO is approximately: 100 x (VOUT) / (VIN x 2) Power Dissipation The dissipation of the part is approximately: ((VIN x 2) - VOUT) x IOUT The TDFN-10 package heats at a rate of about 200°C/ W (θJA). Note that this value is approximate because it depends upon the copper tracks and ground planes on the pcb. If VIN = 5V and IOUT = 100mA then the power dissipation will be approxima tely 500mW. Multiplying this by the θJA gives an internal temperature about 100°C higher than the ambient temperature (T A). If the TA is 70°C then the inte rnal temperature will be approximately 170°C which will trigger the overtemper- ature circuit and lead to power-down. Internal temperature = Ambient temperature + ( θJA x Power dissipation ) (Must be less than 170°C) Note that the evaluation PCB has a θJA of less than 150°C/W, based upon measured performance. How to Reduce the Power Dissipation of the Part and How to Get More Than 100mA If VIN = 5V typ., then the charge pump / LDO combina- tion is capable of providing more than 100mA. The only problem is power dissipation. If the input voltage is lowered using an external diode then the output current can be increased without caus- ing the part to overheat. The circuit below illustrates an example of how to increase the output current. Using this circuit, I OUT can be 200mA if V IN = 4.75V, and yet the part will not overheat even if V IN = 5.25V, IOUT=200mA and the ambient temperature is 85°C. Warnings The charge pump output V CP ( p i n 3 ) m u s t n o t b e shorted to GND or held belo w its internally-set voltage while the part is powered. Th is usually results in the destruction of the part. With VIN = 5V, the maximum current that can be con- tinuously drawn from VCP is approximately 100mA dc. Never short CP+ (pin 9) to CP- (pin 10). This will cause large currents to flow from V IN to DGND through the part, usually causing its de struction. This will happen even if EN_CP and EN_LDO are off. Troubleshooting Guide 1) Is the output voltage drooping under heavy loads? Perhaps the charge pump cannot provide the neces- sary current. Try increasing the value of C P. If that does not work, then, is V IN too low? Is V IN dropping during the C P charging cycle? If V IN is not suitably decoupled and drops below 3.1V then the available current will be very low. 2) Is the output voltage oscillating between 5V and 0V? The part may be reaching its overtemperature limit. Reduce current consumption, reduce θJA or add an external diode on the input to reduce VIN. 3. Is the part too noisy? Try increasing the value (or reducing ESR) of CS, CIN, CS, CB. At minimum current the charge pump ripple frequency will be low. If V OUT noise is at the charge pump ripple frequency, then change values of C P and C S. Reducing the input volt- age VIN will reduce the charge pump ripple frequency noise on VOUT. 4. Will the part power up? Pin 6 must be HIGH to power up. Even if pin 7 is HIGH, pin 6 must also be high to power up. 5. Can the cold start power-up time be reduced? Yes, by reducing the value of the C BYP. CM4072 TDFN-10 Ci 10μF CS 3μF CBYP 0.1μF VOUTCO 0.1μF CP Enable 1μF ±10% 1N4006

© 2005 California Micro Devices Corp. All rights reserved. CM4072 PRELIMINARY Mechanical Details TDFN-10 Mechanical Specifications Dimensions for the CM4072-50DF/DE supplied in a 10-lead TDFN package are presented below. For complete information on the TDFN-10, see the Cal- ifornia Micro Devices TDFN Package Information doc- ument. ✝This package is compliant with JEDEC standard MO-229, variation WEED-3 with exception of the "D 2" and "E2" dimensions as called out in the table above. Package Dimensions for 10-Lead TDFN PACKAGE DIMENSIONS Package TDFN JEDEC No. MO-229 (Var. WEED-3)✝ Leads 10 Dim. Millimeters Inches Min Nom Max Min Nom Max A3 0.20 0.008 D 3.00 0.118 E 3.00 0.118 e 0.50 0.020 K 0.20 0.008 # per tape and reel 3000 pieces Controlling dimension: millimeters Mechanical Package Diagrams BOTTOM VIEW A A3A1 0.10 C 0.08 C SIDE VIEW TOP VIEW b L

0.10 C A BM

e GND PAD D E Pin 1 Marking 4321 78910 K 78910 3214 5 Pin 1 ID C0.35