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Document overview
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Technical content
Features
- Two Linear Regulators ♦ Maximum 2 A Current from VDDQ ♦ Source and Sink Up to 2 A VTT Current
- 1.7 V to 2.8 V Adjustable VDDQ Output V oltage
- 500 mV Typical VDDQ Dropout V oltage at 2 A
- VTT Tracking at 50% of VDDQ
- Excellent Load and Line Regulation, Low Noise
- Fast Transient Response
- Meet JEDEC DDR−I and DDR−II Memory Power Spec.
- Linear Regulator Design Requires No Inductors and Has Low External Component Count
- Integrated Power MOSFETs
- Dual Purpose ADJ/Shutdown Pin
- Built−In Over−Current Limit and Thermal Shutdown for VDDQ and VTT
- Fast Transient Response
- Low Quiescent Current
- These Devices are Pb−Free and are RoHS Compliant
Applications
- DDR Memory and Active Termination Buses
- Desktop Computers, Servers
- Residential and Enterprise Gateways
- DSL Modems
- Routers and Switchers
- DVD Recorders
- 3D AGP Cards
- LCD TV and STB MARKING DIAGRAM Device Package Shipping †
ORDERING INFORMATION
http://onsemi.com CM3202−00DE WDFN8 (Pb−Free) 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. CM320 200DE = CM3202 −00DE CM320 200DE WDFN8 DE SUFFIX CASE 511BH
CM3202−00 http://onsemi.com TYPICAL APPLICATION VIN = 3.3 V to 3.6 V CIN 220 /C0109F/ 10 V CTT 4.7 /C0109F/C0047 10 V cer VTT = 1.25 V/2 A VIN1 NC VTT NC CM3202 VDDQ ADJSD GND GND S/D 10 k/C0087 VDDQ = 2.5 V/2 A Chip Set VDDQCDDQ DL0 DLn VDDQ RT0 RTn DDR REF MEMORY VTT 0.1 /C0109F/10 V cer 4.7 /C0109F/C004710 V cer220 /C0109F/ 10 V 4.7 /C0109F/C004710 V, cer 220 /C0109F/ 10 V 1 k/C0087 1.25 V, 2.5 A VREF 10 k/C0087 FUNCTIONAL BLOCK DIAGRAM VIN ADJSD VDDQ VTT GND Current Limit OTP & Shutdown UVLO & Bandgap CM3202 Current Limit 1.22 V 0.49* VDDQ 0.51* VDDQ Current Limit
Table 1. PIN DESCRIPTIONS 1 VIN Input supply voltage pin. Bypass with a 220 /C0109F capacitor to GND. 2 NC Not internally connected. For better heat flow, connect to GND (exposed pad). 3 VTT VTT regulator output pin, which is preset to 50% of VDDQ. 4 NC Not internally connected. For better heat flow, connect to GND (exposed pad).
7 ADJSD
This pin is for VDDQ output voltage adjustment. It is available as long as VDDQ is enabled. a Shutdown pin. When ADJSD voltage is higher than 2.7 V (SHDN_H), the circuit is in Shutdown mode. diode in series with ADJSD pin is recommended to avoid interference with the voltage adjustment setting. 8 VDDQ VDDQ regulator output voltage pin. EPad GND The backside exposed pad which serves as the package heatsink. Must be connected to GND.
Table 2. ABSOLUTE MAXIMUM RATINGS
- Despite the fact that the device is designed to handle large continuous/peak output currents, it is not capable of handling t hese under all
maximum power dissipation value.
- Measured with the package using a 4 in
2 / 2 layers PCB with thermal vias. Table 3. STANDARD OPERATING CONDITIONS
Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)
- he SHDN Logic High value is normally satisfied for full input voltage range by using a low leakage current (bellow 1 /C0109A). Schottky diode at
- Load and line regulation are measured at constant junction temperature by using pulse testing with a low duty cycle. Changes in output
- Dropout voltage is input to output voltage differential at which output voltage has dropped 100 mV from the nominal value obtained at 3.3 V
input. It depends on load current and junction temperature.
CM3202−00 http://onsemi.com TYPICAL OPERATING CHARACTERISTICS 0.75 0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55 1.65 2.490 2.495 2.500 2.505 2.510 −40 −20 0 20 40 60 80 100 120 140 100 200 300 400 500 600 0.5 1.0 1.5 2.0 2.5 3.0 0.5 1.0 1.5 2.0 2.5 TEMPERATURE (/C0053C) VDDQ (V) VDDQ vs. TemperatureVTT vs. VDDQ VDDQ (V) VTT (V) VDDQ vs. Load Current IDDQ (A) VDDQ (V) VIN = 3.3 V TA = 25°C VDDQ Dropout vs. IDDQ IDDQ (A) Dropout Voltage (mV) TA = 25°C VTT vs. Load Current ITT (A) VTT (V) Startup into Full Load TIME (1 ms/div) UVLO Vin
2 V/div
1 V/div
0 1.0 2.0 3.0 4.0
CM3202−00 http://onsemi.com TYPICAL OPERATING CHARACTERISTICS (Cont’d) VIN IDDQ 0.5A/div VDDQ 0.1V/div ITT 0.5A/div VTT 0.1V/div TIME (0.2 ms/div) -0.75A VDDQ Transient Response VTT Transient Response VIN = 3.3V TIME (0.2 ms/div)
APPLICATION INFORMATION
Double−Data−Rate (DDR) memory has provided a huge step in performance for personal computers, servers and graphic systems. As is apparent in its name, DDR operates at double the data rate of earlier RAM, with two memory accesses per cycle versus one. DDR SDRAM’s transmit data at both the rising and falling edges of the memory bus clock. DDR’s use of Stub Series Terminated Logic (SSTL) topology improves noise immunity and power−supply rejection, while reducing power dissipation. To achieve this performance improvement, DDR requires more complex power management architecture than previous RAM technology. Unlike the conventional DRAM technology, DDR SDRAM uses differential inputs and a reference voltage for all interface signals. This increases the data bus bandwidth, and lowers the system power consumption. Power consumption is reduced by lower operating voltage, a lower signal voltage swing associated with Stub Series Terminated Logic (SSTL_2), and by the use of a termination voltage, V TT. SSTL_2 is an industry standard defined in JEDEC document JESD8 −9. SSTL_2 maintains high−speed data bus signal integrity by reducing transmission reflections. JEDEC further defines the DDR SDRAM specification in JESD79C. DDR memory requires three tightly regulated voltages: VDDQ, VTT, and VREF (see Typical DDR terminations, Class II). In a typical SSTL_2 receiver, the higher current VDDQ supply voltage is normally 2.5 V with a tolerance of ±200 mV . The active bus termination voltage, VTT, is half of VDDQ. VREF is a reference voltage that tracks half of VDDQ, ±1%, and is compared with the VTT terminated signal at the receiver. VTT must be within ±40 mV of VREF Figure 1. Typical DDR Terminations, Class II
CM3202−00 http://onsemi.com APPLICATION INFORMATION (Cont’d) The VTT power requirement is proportional to the number of data lines and the resistance of the termination resistor, but does not vary with memory size. In a typical DDR data bus system each data line termination may momentarily consume 16.2 mA to achieve the 405 mV minimum over VTT needed at the receiver: Iterminaton /C0043405/C8201mV Rt(25/C8201/C0087) /C004316.2/C8201mA A typical 64 Mbyte SSTL−2 memory system, with 128 terminated lines, has a worst−case maximum VTT supply current up to ±2.07 A. However, a DDR memory system is dynamic, and the theoretical peak currents only occur for short durations, if they ever occur at all. These high current peaks can be handled by the VTT external capacitor. In a real memory system, the continuous average VTT current level in normal operation is less than ±200 mA. The VDDQ power supply, in addition to supplying current to the memory banks, could also supply current to controllers and other circuitry. The current level typically stays within a range of 0.5 A to 1 A, with peaks up to 2 A or more, depending on memory size and the computing operations being performed. The tight tracking requirements and the need for V TT to sink, as well as source, current provide unique challenges for powering DDR SDRAM. CM3202−00 Regulator The CM3202−00 dual output linear regulator provides all of the power requirements of DDR memory by combining two linear regulators into a single TDFN−8 package. VDDQ regulator can supply up to 2 A current, and the two−quadrant VTT termination regulator has current sink and source capability to ±2 A. The VDDQ linear regulator uses a PMOS pass element for a very low dropout voltage, typically 500 mV at a 2 A output. The output voltage of VDDQ can be set by an external voltage divider. The use of regulators for both the upper and lower side of the VDDQ output allows a fast transient response to any change of the load, from high current to low current or inversely. The second output, V TT, is regulated at VDDQ/2 by an internal resistor divider. Same as VDDQ, VTT has the same fast transient response to load change in both directions. The VTT regulator can source, as well as sink, up to 2 A current. The CM3202−00 is designed for optimal operation from a nominal 3.3 VDC bus, but can work with VIN as high as 5 V . When operating at higher VIN voltages, attention must be given to the increased package power dissipation and proportionally increased heat generation. VREF is typically routed to inputs with high impedance, such as a comparator, with little current draw. An adequate VREF can be created with a simple voltage divider of precision, matched resistors from VDDQ to ground. A small ceramic bypass capacitor can also be added for improved noise performance. Input and Output Capacitors The CM3202−00 requires that at least a 220 /C0109F electrolytic capacitor be located near the VIN pin for stability and to maintain the input bus voltage during load transients. An additional 4.7 /C0109F ceramic capacitor between the VIN and the GND, located as close as possible to those pins, is recommended to ensure stability. At a minimum of a 220 /C0109F electrolytic capacitor is recommended for the V DDQ output. An additional 4.7 /C0109F ceramic capacitor between the VDDQ and GND, located very close to those pins, is recommended. At a minimum of a 220 /C0109F electrolytic capacitor is recommended for the VTT output. This capacitor should have low ESR to achieve best output transient response. SP or OSCON capacitors provide low ESR at high frequency, and thus are a good choice. In addition, place a 4.7 /C0109F ceramic capacitor between the VTT pin and GND, located very close to those pins. The total ESR must be low enough to keep the transient within the V TT window of 40 mV during the transition for source to sink. An average current step of ±0.5 A requires: ESR /C011640/C8201mV 1/C8201A /C004340/C8201m/C0087 Both outputs will remain stable and in regulation even during light or no load conditions.
CM3202−00 http://onsemi.com APPLICATION INFORMATION (Cont’d) Adjusting VDDQ Output Voltage The CM3202−00 internal bandgap reference is set at 1.25 V . The VDDQ voltage is adjustable by using a resistor divider, R1 and R2: VDDQ /C0043VADJ /C0032R1 /C0041R2 where VADJ = 1.25 V . For best regulator stability, we recommend that R1 and R2 not exceed 10 k/C0087 each. Shutdown ADJSD also serves as a shutdown pin. When this is pulled high (SHDN_H), both the VDDQ and the VTT outputs tri−state and could sink/source less than 10 /C0109A. During shutdown, the quiescent current is reduced to less than 0.5 mA, independent of output load. It is recommended that a low leakage Schottky diode be placed between the ADJSD Pin and an external shutdown signal to prevent interference with the ADJ pin’s normal operation. When the diode anode is pulled low, or left open, the CM3202−00 is again enabled. Current Limit, Foldback and Over−temperature Protection The CM3202−00 features internal current limiting with thermal protection. During normal operation, VDDQ limits the output current to approximately 2 A and VTT limits the output current to approximately ±2 A. When VTT is current limiting into ahard short circuit, the output current folds back to a lower level, about 1 A, until the over −current condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the junction temperature of the device exceeds 170 °C (typical), the thermal protection circuitry triggers and tri−states both VDDQ and VTT outputs. Once the junction temperature has cooled to below about 120 °C the CM3202−00 returns to normal operation. Thermal Considerations Typical Thermal Characteristics The overall junction to ambient thermal resistance (/C0113JA) for device power dissipation (PD) primarily consists of two paths in the series. The first path is the junction to the case (/C0113JC) which is defined by the package style and the second path is case to ambient (/C0113CA) thermal resistance which is dependent on board layout. The final operating junction temperature for any condition can be estimated by the following thermal equation: TJUNC /C0043TAMB /C0041PD /C0032(/C0113JC) /C0041PD /C0032(/C0113CA) /C8201/C8201/C8201/C8201/C8201/C8201/C8201/C8201/C8201/C8201/C0043TAMB /C0041PD /C0032(/C0113CA) When a CM3202−00 using WDFN8 package is mounted on a double−sided printed circuit board with four square inches of copper allocated for “heat spreading,” the /C0113JA is approximately 55°C/W. Based on the over temperature limit of 170°C with an ambient temperature of 85°C, the available power of the package will be: PD /C0043170° C /C004285° C 55° C/C0324W /C00431.5/C8201W
more easily from the package to the PCB. The heat spreader is a copper pad of dimensions just smaller than the package itself. /C0113JA, of approximately 55°C/W. Figure 2. Thermal Layout for WDFN8 Package
CM3202−00 http://onsemi.com PACKAGE DIMENSIONS WDFN8, 3x3, 0.65P CASE 511BH−01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP . 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. ÇÇÇ ÇÇÇ ÇÇÇ AD E B C0.10 PIN ONE REFERENCE TOP VIEW SIDE VIEW BOTTOM VIEW LD2 C C0.10 C0.10 C0.08 A1 SEATING PLANE NOTE 3 b8X 0.10 C 0.05 C A BB DIM MIN MAX MILLIMETERS A 0.70 0.80 A1 0.00 0.05 b 0.25 0.35 D 3.00 BSC D2 2.20 2.40 E 3.00 BSC E2 1.40 1.60 e 0.65 BSC L 0.20 0.40 1 4 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* 0.65 PITCH 1.66 3.30 DIMENSIONS: MILLIMETERS 0.53 NOTE 4 0.40 DETAIL A A3 0.20 REF ADETAIL B DETAIL A L ALTERNATE CONSTRUCTIONS ÉÉÇÇ ÇÇ L ÇÇÇ ÉÉÉ DETAIL B MOLD CMPDEXPOSED Cu ALTERNATE CONSTRUCTIONS L1 −−− 0.15 OUTLINE PACKAGE e RECOMMENDED K 0.45 REF 2.46 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 CM3202−00/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative