CM3121 | DigiCamel IC Datasheet

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Features

Fully integrated power solution for DDR memory ICs Ideal for DDR-I (2.5VDDQ) and DDR-II (1.8VDDQ) Lowest system cost and smallest footprint with just two external output capacitors Two linear regulators: - VDDQ regulator with a maximum output current of 1.5A shared by DRAM and VTT regulator - source-sink VTT regulator with maximum out- put current of 0.5A (DDR-I) or 0.3A (DDR-II) Fault output indicates overcurrent condition in either regulator, under voltage lock-out and over- temperature condition Reverse current protection if host is powered off PSOP-8 package with integrated heat spreader Lead-free versions available

Applications

DDR-I and DDR-II memory power for: − Set Top Boxes, DVD Players, Games − Digital TVs, Flat Panel Displays − Printers, Digital Projectors − Embedded systems − Communications systems Product Description The CM3121 provides an integrated power solution for DDR-I and DDR-II memory systems in consumer electron- ics applications. The CM3121 is ideal for a 2.8V to 3.6V supply for DDR-I memory and 2.2V to 2.8V for DDR-II mem- ory. The CM3121 features two independent linear regula- tors for VDDQ and VTT supply regulation. The default voltage for VDDQ is 2.5V. The VDDQ regulator SENSE pin allows for setting VDDQ in the 2.2V to 2.8V range, or DDR-II memories from 1.7V to 1.9V. The VTT regulator output is always half the VDDQ voltage, derived internally. A capacitor should be connected to each of the two outputs. When EN_DDR is set high, the two DDR regulators are dis- abled to minimize overall system power dissipation such as when memory is in standby. The FAULT pin goes low whenever either of the two regula- tors goes into current limit mode, the input voltage drops too far or if overtemp occurs. The CM3121 is available in a PSOP-8 package that has excellent thermal dissipation. It is available with optional lead-free finishing. Typical Application Circuit Circuit Schematic VREF R R FAULT VTT=1.25V VDDQ = 2.5V VDDQ REGULATOR VTT REGULATOR EN_DDR VCC GND CDDQ DDR MEMORY CPU CORE + I/O CCC CTT Enable DDR Memory # 2.8V to 3.3V SENSE VTT VTT SENSE VTT VDDQ SENSE VDDQ CURRENT LIMIT OVERTEMP LOW INPUT VREF R R FAULT VDDQ REGULATOR VTT REGULATOR GND SENSE VTT VTT SENSE VTT VDDQ SENSE VDDQ CURRENT LIMIT OVERTEMP LOW INPUT SENSE_VTT VTT SENSE_ VDDQ VDDQ VCC EN_DDR

© 2004 California Micro Devices Corp. All rights reserved. 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.calmicro.com 11/12/04 CM3121 PRELIMINARY Functional Description The CM3121 provides power for DDR-I/DDR-II memo- ries from two voltage regulators on-chip. There is an over-temperature thermal shutdown if any of the regu- lators overheat. Each regulator also has reverse cur- rent protection in the event of any being shut down. The VDDQ linear regulator can provide 2.5V/1.8V for DDR-I/-II memory at up to 1.5A. An external feedback resistor divider R1 and R2, when connected to the SENSE_VDDQ pin, enables selection of VDDQ output voltages from 2.2V to 2.8V for use with DDR-I memo- ries requiring other than 2.5V for VDDQ (see Figure 5). In this mode, the voltage on VDDQ is detemined as fol- lows: VDDQ = 1.25V x When SENSE_VDDQ is connected to GND or left open, VDDQ is fixed at 2.50V (and VTT at 1.25V). For DDR-II operation, VDDQ can be set from 1.7V to 1.9V. The VTT regulator is a linear source-sink regulator powered from the VDDQ output that supplies the VTT supply required by DDR-I memory termination resistors. This regulator sinks or sources up to 0.5A. The VTT output voltage accurately tracks VDDQ/2 to 1%. When there is no VCC provided, VTT is powered down and its output is 0V. This regulator has overload current limiting of 0.6A minimum. The EN_DDR pin when set active low enables the CM3121 to operate in normal mode with VDDQ and VTT active. When EN_DDR is high, the CM3121 is disabled and both VDDQ and VTT are set to 0V. The FAULT output is normally at logic high but when an overcurrent occurs on either VDDQ or VTT outputs, FAULT goes active low, and remains low as long as the overcurrent fault persists. Also if the chip goes into thermal overload, or the input voltage VCC drops suffi- ciently that the chip goes into Under Voltage Lock-Out mode (UVLO), FAULT goes active low, and remains low as long as the condition persists. (R1+R2) PIN DESCRIPTIONS LEAD NAME

DESCRIPTION

Input supply. VDDQ VDDQ output. VTT VTT output for termination resistors or VREF GND Ground reference. EN_DDR Enable DDR power. Active low input. SENSE_VTT Sense input for VTT rail adjustment. FAULT Overcurrent Fault / UVLO indication, active low output. SENSE_VDDQ Sense input for VDDQ rail adjustment. PAD GND Tied to ground reference. PACKAGE / PINOUT DIAGRAM Note: This drawing is not to scale. 8-Lead PSOP VCC VDDQ VTT GND SENSE_VDDQ FAULT SENSE_VTT EN_DDR TOP VIEW

Ordering Information

Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Specifications Note 1: The VDDQ regulator provides power for both the memory load and the VTT regulator, supplying a total of 1.5A to the VDDQ and VTT outputs. For example, if the VDDQ load current is 1.2A, then the maximum VTT load current will be 0.3A, regardless of the actual VTT output current rating. PART NUMBERING INFORMATION Leads Package Standard Finish Lead-free Finish Ordering Part Number1 Part Marking Ordering Part Number1 Part Marking PSOP-8 CM3121-02SB CM3121 02SB CM3121-02SH CM3121 02SH ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS ESD (Human Body Model) ±2000 V Pin Voltages VCC EN_DDR, SENSE_VDDQ, SENSE_VTT [GND - 0.6] to [VCC + 0.6] V V Storage Temperature Range -40 to +150 Operating Temperature Range Ambient Junction -40 to +85 0 to +125 STANDARD OPERATING CONDITIONS PARAMETER RATING UNITS Ambient Operating Temperature Range -40 to +85 1. VDDQ Regulator DDR-I Supply Voltage VCC [VDDQ + 0.3] to 3.6 V DDR-II Supply Voltage VCC 2.2 to 2.8 V Load Current (note 1) 0 to 1500 mA CCC, CDDQ 10, 10 µF 2. VTT Regulator DDR-I Supply Voltage VDDQ 2.3 to 2.8 V DDR-II Supply Voltage VDDQ 1.7 to 1.9 V DDR-I Load Current 0 to ±500 mA DDR-II Load Current 0 to ±300 mA CTT µF

© 2004 California Micro Devices Corp. All rights reserved. 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.calmicro.com 11/12/04 CM3121 PRELIMINARY Specifications (cont’d) DDR-I Specifications ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS General Parameters TOVER Shutdown Junction Temperature 150 THYST Junction Temp Hysterisis IC in shutdown ICCN Normal Mode VCC Supply Current EN_DDR = logic "0", EN_CORE =logic "0" 700 1100 µA ICCQ Shutdown Mode VCC Supply Current EN_DDR = logic "1", VDDQ = 0V, VTT = 0V µA VIH EN_DDR Input High Threshold VCC =3.3V 2.0 V VIL EN_DDR Input Low Threshold VCC =3.3V 0.4 V UVLO Under Voltage Lock-Out IDDQ = 10mA 1.8 V tRISE VDDQ Rise TIme VCC = 3.3V, CDDQ = 10µF 0.5 ms VDDQ Regulator Parameters VCC MIN Input Voltage VDDQ = 2.5V, IDDQ = 1.5A, SENSE_VDDQ = 0V, Note 2 2.80 V VDDQ DEF Default Output Voltage Range IDDQ = 0.01A, 2.8V ≤ VCC ≤ 3.6V, SENSE_VDDQ = 0V, Note 2 2.45 2.50 2.55 V VDDQ ADJ Adjustable Output Voltage Range VCC = 3.6V, SENSE_VDDQ tied to external resistors R1 and R2, Note 2 1.6 2.8 V VDDQ LD Load Regulation TA = 25°C, VCC = 3.3V, 0.01A ≤ IDDQ ≤ 1.0A, Note 2 2.5 VDDQ LINE Line Regulation TA = 25°C, IDDQ = 0.01A, 2.8V ≤ VCC ≤ 3.6V, Note 2 -1.0 1.0 eN DDQ Output Noise Voltage BW = 10Hz - 100kHz, CDDQ = 10µF µVrms IDDQ LIM Current Limit Note 2 1.7 2.0 A IDDQ SC Short Circuit Current VDDQ < 0.3V 0.5 A

© 2004 California Micro Devices Corp. All rights reserved. 11/12/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.calmicro.com CM3121 PRELIMINARY Note 1: All parameters specified at TA = -40°C to +85°C unless otherwise noted. Note 2: Note that the IDDQ current specified is the load current output from the VDDQ pin. VDDQ also supplies current internally to the VTT regulator when it is sourcing current. The maximum source current can be up to 0.5A. So the maximum total current from the VDDQ regulator is the external VDDQ current IDDQ added to the maximum VTT sourcing current ITT. All load currents are specified as such, but the VDDQ current limit is specified at a current just above the total maximum current. DDR-II Specifications VTT Regulator Parameters VTT Output Voltage Range VDDQ = 2.5V, ITT = 0.01A, 1.20 1.25 1.30 V VTT REF Output Voltage Range VDDQ = 2.500V, ITT = 0.01A 1.225 1.250 1.275 V VTT LD Load Regulation TA = 25°C, VDDQ = 2.5V, 0.01A ≤ ITT ≤ ±0.5A -1.0 1.0 VTT LINE Line Regulation TA = 25°C, ITT = 0.01A, 2.8V ≤ VCC ≤ 3.6V, Note 2 -1.0 1.0 eN TT Output Noise Voltage BW = 10Hz - 100kHz, CTT = 10µF µVrms ITT LIM Current Limit 0.6 0.8 A ITT SC Short Circuit Current VTT < 0.3V 0.3 A ELECTRICAL OPERATING CHARACTERISTICS (CONT’D) (SEE NOTE1) ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS General Parameters TOVER Shutdown Junction Temperature 150 THYST Junction Temp Hysterisis IC in shutdown ICCN Normal Mode VCC Supply Current EN_DDR = logic "0", 700 1100 µA ICCQ Shutdown Mode VCC Supply Current EN_DDR = logic "1", VDDQ = 0V, VTT = 0V µA VIH EN_DDR Input High Threshold VCC =3.3V 2.0 V VIL EN_DDR Input Low Threshold VCC =3.3V 0.4 V UVLO Under Voltage Lock-Out IDDQ = 10mA 1.8 V tRISE VDDQ Rise TIme VCC = 3.3V, CDDQ = 10µF 0.5 ms

© 2004 California Micro Devices Corp. All rights reserved. 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.calmicro.com 11/12/04 CM3121 PRELIMINARY Note 3: All parameters specified at TA = -40°C to +85°C unless otherwise noted. Note 4: Note that the IDDQ current specified is the load current output from the VDDQ pin. VDDQ also supplies current internally to the VTT regulator when it is sourcing current. The maximum source current can be up to 0.5A. So the maximum total current from the VDDQ regulator is the external VDDQ current IDDQ added to the maximum VTT sourcing current ITT. All load currents are specified as such, but the VDDQ current limit is specified at a current just above the total maximum current. Table 1: Truth Table for CM3121 VDDQ Regulator Parameters VCC MIN Input Voltage VDDQ = 2.5V, IDDQ = 1.5A, SENSE_VDDQ = 0V, Note 4 2.2 V VDDQ Default Output Voltage Range IDDQ = 0.01A,VCC = 3.3V, SENSE_VDDQ = 0V, Note 4 1.75 1.80 1.85 V VDDQ ADJ Adjustable Output Voltage Range VCC = 3.3V, SENSE_VDDQ tied to external resistors R1 and R2, Note 4 1.6 2.8 V VDDQ LD Load Regulation TA = 25°C, VCC = 2.5V, 0.01A ≤ IDDQ ≤ 1.0A, Note 4 2.5 VDDQ LINE Line Regulation TA = 25°C, IDDQ = 0.01A, 2.2V ≤ VCC ≤ 2.8V, Note 4 -1.0 1.0 eN DDQ Output Noise Voltage BW = 10Hz - 100kHz, CDDQ = 10µF µVrms IDDQ LIM Current Limit Note 4 1.7 2.0 A IDDQ SC Short Circuit Current VDDQ < 0.3V 0.5 A VTT Regulator Parameters VTT Output Voltage Range VDDQ = 1.8V, ITT = 0.01A, 0.86 0.90 0.94 V VTT LD Load Regulation TA = 25°C, VDDQ = 1.8V, 0.01A ≤ ITT ≤ ±0.3A -1.0 1.0 VTT LINE Line Regulation TA = 25°C, ITT = 0A, 2.2V ≤ VCC ≤ 2.8V -1.0 1.0 eN TT Output Noise Voltage BW = 10Hz - 100kHz, CTT = 10µF µVrms ITT LIM Current Limit 0.4 0.6 A ITT SC Short Circuit Current VTT < 0.3V 0.3 A VCC(1) EN_DDR VDDQ OUT VTT OUT 2.8V to 3.6V Low VDDQ VDDQ / 2 X High ELECTRICAL OPERATING CHARACTERISTICS (CONT’D) (SEE NOTE 3)

Application Information

The CM3121 can be used without any external resis- tors if a VDDQ voltage of 2.5V is required by connecting the SENSE_VDDQ pin to GND. Also in applications where a reference voltage (VREF) is required, a PCB trace directly from the VTT pin can be used. The VTT output pin has an error relative to VDDQ/2 of up to +/-25mV, which is well within most DDR system specs of +/-50mV. This is because the VTT output internally tracks the VDDQ output very closely due to the matched on-chip resistors R that tap down from the VDDQ rail, and the low offset voltage of the VTT regulator. It is recommended that the VREF trace be connected directly to the VTT pin, to eliminate noise and ripple on the VTT line caused by current switching Figure 4. Typical Application for the CM3121

© 2004 California Micro Devices Corp. All rights reserved. II application is 1.5V, and the maximum for ITT is 0.3V. ence voltage or a controller input. Figure 5. Minimal CM3132 DDR-II power solution.

© 2004 California Micro Devices Corp. All rights reserved. 11/12/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.calmicro.com CM3121 PRELIMINARY Mechanical Details PSOP-8 Mechanical Specifications Dimensions for CM3121 devices packaged in an 8- lead PSOP package with a heatspreader are shown below. * This is an approximate number which may vary. Centered on package centerline. Package Dimensions for PSOP-8 PACKAGE DIMENSIONS Package PSOP-8 Leads Dimensions Millimeters Inches Min Max Min Max A 1.30 1.62 0.051 0.064 0.03 0.10 0.001 0.004 B 0.33 0.51 0.013 0.020 C 0.18 0.25 0.007 0.010 D 4.83 5.00 0.190 0.197 E 3.81 3.99 0.150 0.157 e 1.02 1.52 0.040 0.060 H 5.79 6.20 0.228 0.244 L 0.41 1.27 0.016 0.050 x 3.30 3.81 0.130 0.150 y** 2.29 2.79 0.090 0.110 # per tube 100 pieces* # per tape and reel 2500 pieces Controlling dimension: inches Mechanical Package Diagrams H TOP VIEW L END VIEW C e B A SEATING PLANE SIDE VIEW Pin 1 E D H BOTTOM VIEW x y y/2 x/2 Marking D E Heat Slug

Product Information

CM3121 specifications and overview.

Summary

Dual Linear Voltage Regulator for DDR-I and DDR-II Memory

Description

Dual Linear Voltage Regulator for DDR-I and DDR-II Memory

Source title CM3121 Datasheet(PDF) - California Micro Devices Corp

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