CM3106 CALMIRCO | Alldatasheet

Document overview

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Technical content

Features

  • Ideal for DDR-I and DDR-II V TT applications  Sinks and sources 2.0A for DDR-I  Over current protection  Over temperature protection  Integrated power MOSFETs  Excellent accuracy (0.5% load regulation)  Pin and functionally compatible with LP2995  8-lead SOIC and PSOP packages  Lead-free versions available

Applications

 Single and Dual Channel DDR Memory Bus Termination  Active Termination Buses  Graphics Card Memory Termination Product Description The CM3106 is a sinking and sourcing regulator specif- ically designed for providing power to DDR memory terminating resistors and companion chip set V TT power. The output voltage accurately tracks V DDQ/2. The CM3106 can source and sink current up to 2A, ideal for DDR-I memory systems, and 1.2A for DDR-II systems, while maintaining a load regulation of 0.5% in either application. The CM3106 provides over current and over tempera- ture protection which protects the device from exces- sive heating due to high current and high temperature. A shutdown capability using an external transistor reduces power consumption and provides a high impedance output. The CM3106 is housed in both 8-lead SOIC and PSOP packages and is available with optional lead-free finish- ing. Simplified Electrical Schematic VREF AVIN GND Over Current VSENSE 50K Over Temp Reference INOUT Buffer VTT Driver 50K VDDQ PVIN

© 2004 California Micro Devices Corp. All rights reserved. CM3106

Ordering Information

Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. PIN DESCRIPTIONS LEAD(S) NAME DESCRIPTION

1 NC No Connect

2 GND Ground

4V REF Reference Output, VDDQ/2 5V DDQ VDDQ Input 6A V IN Analog Input 7P V IN Power Input 8V TT Output PACKAGE / PINOUT DIAGRAM Note: This drawing is not to scale. 8-lead SOIC NC GND VSENSE VREF VTT PVIN AVIN VDDQ TOP VIEW 8-lead PSOP TOP VIEW NC GND VSENSE VREF VTT PVIN AVIN VDDQ GND PART NUMBERING INFORMATION Pins Package Standard Finish Lead-free Finish Ordering Part Number1 Part Marking Ordering Part Number1 Part Marking

8 SOIC-8 CM3106-12SN CM310601S CM3106-12SM CM3106-12SM

8 PSOP-8 CM3106-12SB CM3106-12SB CM3106-12SH CM3106-12SH

© 2004 California Micro Devices Corp. All rights reserved. CM3106 Specifications Note 1: These devices must be derated based on thermal resistance at elevated temperatures. The device packaged in a 8-lead SOIC leadframe must be derated at θJA = 151°C/W . θJA of the 8-lead PSOP is 40°C/W. Note 1: Operating Characteristics are over Standard Operating Conditions unless otherwise specified. ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS AVIN Operating Supply Voltage 7 V VDDQ Input Voltage 7V Pin Voltages VTT Output Any other pins V V ESD (HBM) ±2000 V Storage T emperature Range -40 to +150 °C Operating Temperature Range Ambient Junction -40 to +85 (see note1) -40 to +150 Power Dissipation (see note 1) Internally Limited W STANDARD OPERATING CONDITIONS PARAMETER VALUE UNITS VDDQ 2.5 V AVIN 2.5 V PVIN 2.5 V Ambient Operating T emperature 0 to +70 °C CTT 220 +20% µF ELECTRICAL OPERATING CHARACTERISTICS(SEE NOTE 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input Voltage Range VDDQ AVIN 2.2 2.2 2.5 2.5 AV IN 5.5 V V ICC AVIN Quiescent Current I VTT = 0A 450 µA VRLOAD Load Regulation 0A < IVTT < 2.0A or -2.0A < IVTT < 0A 6.25 mV VREF Output Reference Voltage V DDQ=2.5V, IREF=0A 1.225 1.25 1.275 V VOSVTT Output Offset from VREF -20 20 mV ZREF VREF Output Impedance -5 µA < IREF < 5µA5 k Ω ZVDDQ VDDQ Input Impedance 100 k Ω ILIM VTT Current Limit 2.5 A TDISABLE THYST Shutdown T emperature Thermal Hysteresis 150

© 2004 California Micro Devices Corp. All rights reserved. CM3106 Mechanical Details The CM3106 is available in an 8-lead SOIC and PSOP package. SOIC-8 Mechanical Specifications Dimensions for CM3106 devices packaged in 8-pin SOIC packages are presented below. For complete information on the SOIC-8 package, see the California Micro Devices SOIC Package Informa- tion document. * This is an approximate number which may vary. Package Dimensions for SOIC-8 PACKAGE DIMENSIONS Package SOIC Leads 8 Dimensions Millimeters Inches Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.19 0.150 0.165 e 1.27 BSC 0.050 BSC H 5.80 6.20 0.228 0.244 L 0.40 1.27 0.016 0.050 # per tube 100 pieces* # per tape and reel 2500 pieces Controlling dimension: inches Mechanical Package Diagrams E D H TOP VIEW L END VIEW C eB A A1SEATING PLANE SIDE VIEW 1234 8765 Pin 1 Marking

© 2004 California Micro Devices Corp. All rights reserved. CM3106 Mechanical Details PSOP-8 Mechanical Specifications Dimensions for CM3106 devices packaged in 8-pin PSOP packages with an intagrated heatslug are pre- sented below. * This is an approximate number which may vary. Centered on package centerline. Package Dimensions for PSOP-8 PACKAGE DIMENSIONS Package PSOP-8 Leads 8 Dimensions Millimeters Inches Min Max Min Max A 1.30 1.62 0.051 0.064 A1 0.03 0.10 0.001 0.004 B 0.33 0.51 0.013 0.020 C 0.18 0.25 0.007 0.010 D 4.83 5.00 0.190 0.197 E 3.81 3.99 0.150 0.157 e 1.02 1.52 0.040 0.060 H 5.79 6.20 0.228 0.244 L 0.41 1.27 0.016 0.050 x 3.30 3.81 0.130 0.150 y** 2.29 2.79 0.090 0.110 # per tube 100 pieces* # per tape and reel 2500 pieces Controlling dimension: inches Mechanical Package Diagrams H TOP VIEW L END VIEW C eB A A1SEATING PLANE SIDE VIEW 1234 8765 Pin 1 E D H BOTTOM VIEW 1234 8765 x y y/2x/2 Marking D E Heat Slug