CM2031-A0TR

CM2031 CALMIRCO | Alldatasheet

Document overview

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• PDF pages: 14

Technical content

Features

• HDMI 1.3 compliant
• Supports thin dielectric and 2-layer boards
• Minimizes TMDS skew with 0.05pF matching
• Long HDMI cable support with integrated I2C accelerator
• Active termination and slew rate limiting for CEC
• Supports direct connection to CEC microcontroller
• Integrated I2C level shifting to CMOS level including low logic level voltages
• Integrated 8kV ESD protection and backdrive protection on all external I/O lines
• Supports active and passive control of hot plug detect signal
• Multiport I2C support eliminates need for analog mux on DDC lines
• Simplified layout with matched 0.5mm trace spacing

Applications

• PC and consumer electronics
• Digital TV, PC monitors and projectors Product Description The CM 2031 HD MI R eceiver P ort P rotection and Interface De vice is sp ecifically d esigned f or ne xt generation HDMI Sink interface protection. An i ntegrated pa ckage pr ovides a ll ES D, s lew r ate limiting on CEC line, level shifting/isolation and backdrive protection for an HDMI por t in a si ngle 38­ Pin TSSOP package. The CM2 031 part i s s pecifically des igned to pr ovide the de signer with the most reliable pa th to HDM I 1.3 CTS compliance. Electrical Schematic TMDS_CK+ TMDS_GND TMDS_CK­ TMDS_D2+ TMDS_GND TMDS_D2­ TMDS_D1+ TMDS_GND TMDS_D1­ TMDS_D0+ TMDS_GND TMDS_D0­ CE_REMOTE_OUT CE_REMOTE_IN DDC_CLK_OUT DDC_CLK_IN CE_SUPPLY LV_SUPPLY 5V_SUPPLY ACTIVE SLEW RATE LIMITING 5V_SUPPLY DDC_DAT_OUT DDC_DAT_IN LV_SUPPLY 5V_SUPPLY DYNAMIC PULLUP DYNAMIC PULLUP CMOS/I2C LEVEL SHIFT CMOS/I2C LEVEL SHIFT CE_SUPPLY 5V_SUPPLY 1kΩ HOTPLUG_DET_IN HOTPLUG_DET_OUT © 2007 California Micro Devices Corp. All rights reserved.

Note: This drawing is not to scale. 38-PIN TSSOP PACKAGE TMDS_GND TMDS_D2– TMDS_D1+ TMDS_GND TMDS_D1– TMDS_D0+ TMDS_GND TMDS_D0– 5V_SUPPLY LV_SUPPLY GND TMDS_D2+ CE_SUPPLY GND TMDS_D2+ TMDS_GND TMDS_D2– TMDS_D1+ TMDS_GND TMDS_D1– TMDS_D0+ TMDS_GND TMDS_D0– N/C TMDS_CK+ TMDS_GND TMDS_CK+ TMDS_GND TOP VIEW TMDS_CK– CE_REMOTE_IN DDC_CLK_IN TMDS_CK– CE_REMOTE_OUT DDC_CLK_OUT DDC_DAT_OUT HOTPLUG_DET_OUT DDC_DAT_IN HOTPLUG_DET_IN PIN DESCRIPTIONS PINS NAME ESD Level DESCRIPTION 4, 35 TMDS_D2+ 8kV3 TMDS 0.9pF ESD protection.1 6, 33 TMDS_D2– 8kV3 TMDS 0.9pF ESD protection.1 7, 32 TMDS_D1+ 8kV3 TMDS 0.9pF ESD protection.1 9, 30 TMDS_D1– 8kV3 TMDS 0.9pF ESD protection.1 10, 29 TMDS_D0+ 8kV3 TMDS 0.9pF ESD protection.1 12, 27 TMDS_D0– 8kV3 TMDS 0.9pF ESD protection.1 13, 26 TMDS_CK+ 8kV3 TMDS 0.9pF ESD protection.1 15, 24 TMDS_CK– 8kV3 TMDS 0.9pF ESD protection.1 16 CE_REMOTE_IN 2kV4 CE_SUPPLY referenced logic level in. 23 CE_REMOTE_OUT 8kV3 5V_SUPPLY referenced logic level out plus 10pF ESD. 17 DDC_CLK_IN 2kV4 LV_SUPPLY referenced logic level in. 22 DDC_CLK_OUT 8kV3 5V_SUPPLY referenced logic level out plus 10pF ESD. 18 DDC_DAT_IN 2kV4 LV_SUPPLY referenced logic level in. 21 DDC_DAT_OUT 8kV3 5V_SUPPLY referenced logic level out plus 10pF ESD. 19 HOTPLUG_DET_IN 2kV4 LV_SUPPLY referenced logic level in. 20 HOTPLUG_DET_OUT 8kV3 5V_SUPPLY referenced logic level out plus 10pF ESD. A 0.1μF bypass ceramic capacitor is recommended on this pin.2 2 LV_SUPPLY 2kV4 Bias for CE / DDC / HOTPLUG level shifters. 37 CE_SUPPLY 2kV4,2 CEC bias voltage. Previously CM2020 ESD_BYP pin. 1 5V_SUPPLY 2kV4 Current source for 5V_OUT, VREF for DDC I2C voltage references, and bias for 8kV ESD pins.

38 N/C N/A N/C

© 2007 California Micro Devices Corp. All rights reserved.

PIN DESCRIPTIONS (CONT’D) PINS NAME ESD Level DESCRIPTION 3, 5, 8, 11, 14, 25, 28, 31, 34, GND / TMDS_GND N/A GND reference. Note 1: These 2 pins need to be connected together in-line on the PCB. See recommended layout diagram. Note 2: This out put c an be conn ected t o an e xternal 0. 1μF ceramic cap acitor/pads t o m aintain bac kward com patibility wit h t he CM2020. Note 3: Standard I EC 61000 -4-2, C DISCHARGE=150pF, R DISCHARGE=330Ω, 5V _SUPPLY and LV_SUPPLY wit hin recommended operating conditions, GND=0V, 5V_OUT (pin 38), and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1μF ceramic capacitor connected to GND. Note 4: Human B ody Model per MI L-STD-883, Method 3015, C DISCHARGE=100pF, R DISCHARGE=1.5kΩ, 5 V_SUPPLYand LV_SUPPLY within recommended op erating conditions, GND=0V, 5V_OUT (pin 38), and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1μF ceramic capacitor connected to GND. Note 5: These pins should be routed directly to the associated GND pins on the HDMI connector with single point ground vias at the connector © 2007 California Micro Devices Corp. All rights reserved.

exceeds its related operating CM2031 supply voltage. Figure 1. Backdrive Protection Diagram. protocol for EDID configuration. cable). At the upper range of ca pacitance values (i.e. pull-up resistor of 1.5k Ω (at the source). © 2007 California Micro Devices Corp. All rights reserved.

Ordering Information

PART NUMBERING INFORMATION Pins Package Lead-free Finish Ordering Part Number1 Part Marking

38 TSSOP-38 CM2031-A0TR CM2031-A0TR

Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS VCC5, VCCLV 6.0 V DC Voltage at any Channel Input [GND - 0.5] to [VCC + 0.5] V Storage Temperature Range –65 to +150 °C STANDARD (RECOMMENDED) OPERATING CONDITIONS SYMBOL PARAMETER MIN TYP MAX UNITS 5V_SUPPLY Operating Supply Voltage 5 5.5 V LV_SUPPLY Bias Supply Voltage 1 3.3 5.5 V CE_SUPPLY Bias Supply Voltage 3 3.3 3.6 V Operating Temperature Range –40 85 °C ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ICC5 Operating Supply Current 5V_SUPPLY = 5.0V, CEC_OUT = 3.3V, LV_SUPPLY= CE_SUPPLY= 3.3V, DDC=5V; Note 7 300 350 μA ICCLV Bias Supply Current LV_SUPPLY = 3.3V; Note 7 60 150 μA ICCCE Bias Supply Current CE_SUPPLY=3.3V, CEC_OUT=0V; Note 7 60 150 μA IOFF OFF state leakage current, level shifting NFET LV_SUPPLY=0V 0.1 5 μA IBACKDRIVETMDS Current through TMDS pins when powered down All Supplies = 0V; TMDS_[2:0]+/–, TMDS_CK+/– = 4V 0.1 5 μA IBACKDRIVEDDC Current through DDC_DAT_OUT when pow­ ered down All Supplies = 0V; DDC_DAT/CLK_OUT = 5V; DDC_DAT/CLK_IN = 0V 0.1 5 μA © 2007 California Micro Devices Corp. All rights reserved.

ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IBACKDRIVEHOTPLUG Current through HOTPLUG_DET_OUT when powered down All Supplies = 0V; HOTPLUG_DET_OUT = 5V; HOTPLUG_IN = 0V 0.1 5 μA IBACKDRIVECEC Current through CE-REMOTE_OUT when powered down CE-REMOTE_IN = CE_SUPPLY < CE_REMOTE_OUT 0.1 1.8 μA CECSL CEC Slew Limit Measured from10-90% or 90-10% 0.26 0.65 V/μs CECRT CEC Rise Time Measured from 10-90% Assumes a signal swing from 0­ 3.3V 26.4 250 μs CECFT CEC Fall Time Measured from 90-10% Assumes a signal swing from 0­ 3.3V 4 50 μs RHOTPLUG Hotplug Resistance Voltage on HotPlug_In is greater than the specified range below 0.8 1 1.2 kΩ VTH Threshold Voltage to Assert 1kΩ 1.5 5.5 V VACC Turn On Threshold of I2C/DDC Accelerator Voltage is 0.3 X 5V_Supply 1.35 1.5 1.65 V VON(DDC_OUT) Voltage drop across DDC level shifter LV_SUPPLY=2.5V, 4mA Sink at DDCIN, DDCOUT < VACC 140 mV VOL(DDC_IN) Logic Level (ASIC side) when I2C/DDC Logic Low Applied; (I2C pass-through compatibility) DDC_OUT=0.4V, LV_SUPPLY=3.3V, 1.5kΩ pullup on DDC_OUT to 5.0V, Note 2 0.3 0.4 V tr(DDC) DDC_OUT Line Risetime, VACC < VDDC_OUT < (5V_Supply-0.5V) DDC_IN floating, LV_SUPPLY=3.3V, 1.5kΩ pullup on DDC_OUT to 5.0V, Bus Capacitance = 1500pF, Note 2 1 μs VF Diode Forward Voltage Top Diode Bottom Diode IF = 8mA, TA = 25°C, Note 2 0.6 0.6 0.85 0.85 0.95 0.95 V V VESD ESD Withstand Voltage (IEC) Pins 4, 7, 10, 13, 20, 21, 22, 23, 24, 27, 30, 33; Notes 2 and 3 ±8 kV VESD ESD Withstand Voltage (HBM) Pins 1, 2, 16, 17, 18, 19, 37, 38; Notes 2 and 4 ±2 kV VCL Channel Clamp Voltage Positive Transients Negative Transients TA=25°C, IPP=1A, tP=8/20μS; Notes 2 & 6 11.0 –2.0 V V RDYN Dynamic Resistance Positive Transients Negative Transients TA=25°C, IPP=1A, tP=8/20μS Any I/O pin to Ground; Note 6 1.4 0.9 Ω Ω ILEAK TMDS Channel Leakage Current TA = 25°C, Note 2 0.01 1 μA © 2007 California Micro Devices Corp. All rights reserved.

ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CIN, TMDS TMDS Channel Input Capacitance 5V_SUPPLY=5.0V, Measured at 1MHz, VBIAS=2.5V, Note 2 0.9 1.2 pF ΔCIN, TMDS TMDS Channel Input Capacitance Matching 5V_SUPPLY=5.0V, Measured at 1MHz, VBIAS=2.5V, Note 2, 5 0.05 pF CMUTUAL Mutual Capacitance between signal pin and adjacent signalpin 5V_SUPPLY=0V, Measured at 1MHz, VBIAS=2.5V, Note 2 0.07 pF CIN, DDCOUT Level Shifting Input Capacitance, Capacitance to GND 5V_SUPPLY=0V, Measured at 100KHz, VBIAS=2.5V, Note 2 10 pF CIN, CECOUT Level Shifting Input Capacitance, Capacitance to GND 5V_SUPPLY=0V, Measured at 100KHz, VBIAS=1.65V, Note 2 10 pF CIN, HPOUT Level Shifting Input Capacitance, Capacitance to GND 5V_SUPPLY=0V, Measured at 100KHz, VBIAS=2.5V, Note 2 10 pF Note 1: Operating Characteristics are over Standard Operating Conditions unless otherwise specified. Note 2: This parameter is guaranteed by design and verified by device characterization. Note 3: Standard IEC61000-4-2, CDISCHARGE=150pF, RDISCHARGE=330Ω, 5V_SUPPLY=5V, 3.3V_SUPPLY=3.3V, LV_SUPPLY=3.3V, GND=0V. Note 4: Human Body Model per MIL-STD-883, Method 3015, CDISCHARGE=100pF, RDISCHARGE=1.5kΩ, 5V_SUPPLY=5V, 3.3V_SUPPLY=3.3V, LV_SUPPLY=3.3V, GND=0V. Note 5: Intra-pair matching, each TMDS pair (i.e. D+, D–). Note 6: These measurements performed with no external capacitor on VP (VP floating). Note 7: These static measurements do not include AC activity on controlled I/O lines. © 2007 California Micro Devices Corp. All rights reserved.

Figure 9. Insertion Loss vs. Frequency (TMDS_D1- to GND) © 2007 California Micro Devices Corp. All rights reserved.

Application Information

Figure 10. Typical Application for CM2031

1 Differential TMDS Pairs should be designed as normal

2 Level Shifter signals should be biased with a weak pullup to

3 Place MediaGuardTM as close to the connector as possible,

placing any silkscreen printing over TMDS traces. 100nF CBYP is recommended for all applications. © 2007 California Micro Devices Corp. All rights reserved.

DUT On vs. DUT Off Many HDMI CTS tests require a power off condition on circuitry limits this c urrent t o less t han 5 μA, an d wil l the System Under T est. Man y di screte E SD di ode help ensure HDMI compliance. configurations can be forward baised when their VDD rail i s l ower th an th e I/O p in b ias, th ereby e xhibiting extremely high ap parent c apacitance me asurements, for e xample. T he MediaGuardΤΜ b ackdrive isolation PLEASE REVIEW ALL OF THE CURRENT HDMI DESIGN GUIDELINES AVAILABLE AT http://www.calmicro.com/applications/customer/downloads/current-cmd-mediaguard-design-guidelines.zip © 2007 California Micro Devices Corp. All rights reserved.

TSSOP-38 Mechanical Specifications CM2031 de vices ar e s upplied in 38-pin T SSOP packages. Dimensions are presented below. For complete i nformation o n t he TSSOP-38, s ee the California Micro Devices TSSOP Package Information document. PACKAGE DIMENSIONS Package TSSOP JEDEC No. MO-153 (Variation BD-1) Pins 38 Dimensions Millimeters Inches Min Max Min Max A — 1.20 — 0.047 A1 0.05 0.15 0.002 0.006 b 0.17 0.27 0.007 0.011 c 0.09 0.20 0.004 0.008 D 9.60 9.80 0.378 0.386 E 6.40 BSC 0.252 BSC E1 4.30 4.50 0.169 0.177 e 0.50 BSC 0.020 BSC L 0.45 0.75 0.018 0.030 # per tape and reel 2500 pieces Controlling dimension: millimeters 16 17 18 19 23 22 21 20 Mechanical Package Diagrams D E TOP VIEW L END VIEW c eb A A1SEATING PLANE SIDE VIEW 5 6 7 8 9 10 1 2 3 4 34 33 32 31 30 29 38 37 36 35 i 11 12 13 14 28 27 26 25 Package Dimensions for TSSOP-38 © 2007 California Micro Devices Corp. All rights reserved.