CM2030 ONSEMI | Alldatasheet
Document overview
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- PDF pages: 17
Technical content
Features
- HDMI 1.3 compliant
- Supports thin dielectric and 2-layer boards
- Minimizes TMDS skew with 0.05pF matching
- Long HDMI cable support with integrated I C accelerator
- Active termination and slew rate limiting for CE C
- Supports direct connection to CEC microcontroller
- Integrated I C level shifting to CMOS level includ- ing low logic level voltages
- Integrated 8kV ESD protection and backdrive protection on all external I/O lines
- Integrated overcurrent output protection per HDMI 1.3
- Multiport I C support eliminates need for analog mux on DDC lines
- Simplified layout with matched 0.5mm trace spacing
- RoHS-compliant, lead-free packaging
Applications
- PC and consumer electronics
- Set top box, DVD RW, PC, graphics cards Product Description The CM2030 HDMI Transmitter Port Protection and Interface Device is specifically designed for next generation HDMI Host interface protection. An integrated package provides all ESD, slew rate limiting on CEC line, level shifting/isolation, overcurrent output protection and backdrive protection for an HDMI port in a single 38-pin TSSOP package. The CM2030 part is specifically designed to provide the designer with the most reliable path to HDMI 1.3 CTS compliance. The CM2030 also incorporates a silicon overcurrent protection device for +5V supply voltage output to the connector.
Rev. 5 | Page 2 of 17 | www.onsemi.com Electrical Schematic TMDS_CK+ TMDS_GND TMDS_CK- TMDS_D2+ TMDS_GND TMDS_D2- TMDS_D1+ TMDS_GND TMDS_D1- TMDS_D0+ TMDS_GND TMDS_D0- CE_REMOTE_OUT CE_REMOTE_IN DDC_CLK_OUT DDC_CLK_IN CE_SUPPLY LV_SUPPLY 5V_OUT 5V_SUPPLY 55mA OVERCURRENT SWITCH 5V_SUPPLY ACTIVE SLEW RATE LIMITING 5V_SUPPLY DDC_DAT_OUT DDC_DAT_IN LV_SUPPLY 5V_SUPPLY DYNAMIC PULLUP DYNAMIC PULLUP CMOS/I2C LEVEL SHIFT CMOS/I2C LEVEL SHIFT CE_SUPPLY LV_SUPPLY HOTPLUG_DET_OUT IS 3I S HOTPLUG_DET_IN P ACKAGE / PINOUT DIAGRAM Note: This drawing is not to scale. 38-PIN TSSOP PACKAGE TMDS_GND TMDS_D2– TMDS_D1+ TMDS_GND TMDS_D1– TMDS_D0+ TMDS_GND TMDS_D0– 5V_SUPPLY L V _SUPPL Y GND TMDS_D2+ CE_SUPPLY GND TMDS_D2+ TMDS_GND TMDS_D2– TMDS_D1+ TMDS_GND TMDS_D1– TMDS_D0+ TMDS_GND TMDS_D0– 5V_OUT TMDS_CK+ TMDS_GND TMDS_CK+ TMDS_GND TOP VIEW TMDS_CK– CE_REMO TE_IN DDC_CLK_IN TMDS_CK– CE_REMO TE_OUT DDC_CLK_OUT DDC_DAT_OUT HOTPLUG_DET_OUT DDC_DA T _IN HOTPLUG_DET_IN
Rev. 5 | Page 3 of 17 | www.onsemi.com PIN DESCRIPTIONS PI N S N A M E ESD Level DESCRIPTION 4, 35 TMDS_D2+ 8kV TMDS 0.9pF ESD protection. 6, 33 TMDS_D2– 8kV TMDS 0.9pF ESD protection. 7, 32 TMDS_D1+ 8kV TMDS 0.9pF ESD protection. 9, 30 TMDS_D1– 8kV TMDS 0.9pF ESD protection. 10, 29 TMDS_D0+ 8kV TMDS 0.9pF ESD protection. 12, 27 TMDS_D0– 8kV TMDS 0.9pF ESD protection. 13, 26 TMDS_CK+ 8kV TMDS 0.9pF ESD protection. 15, 24 TMDS_CK– 8kV TMDS 0.9pF ESD protection.
16 CE_REMOTE_IN 2kV
CE_SUPPLY referenced logic level in.
23 CE_REMOTE_OUT 8kV
5V_SUPPLY referenced logic level out plus 10pF ESD .
17 DDC_CLK_IN 2kV
LV_SUPPLY referenced logic level in.
22 DDC_CLK_OUT 8kV
5V_SUPPLY referenced logic level out plus 10pF ESD .
18 DDC_DAT_IN 2kV
LV_SUPPLY referenced logic level in.
21 DDC_DAT_OUT 8kV
5V_SUPPLY referenced logic level out plus 10pF ESD .
19 HOTPLUG_DET_IN 2kV
LV_SUPPLY referenced logic level in.
20 HOTPLUG_DET_OUT 8kV
5V_SUPPLY referenced logic level out plus 10pF ESD. A 0.1 µ F bypass ceramic capacitor is recommended on this pin.
2 LV_SUPPLY 2kV
Bias for CE / DDC / HOTPLUG level shifters.
37 CE_SUPPLY 2kV
4,2 CEC bias voltage. Previously CM2020 ESD_BYP pin. 1 5V_SUPPLY 2kV Current source for 5V_OUT, VREF for DDC I C voltage references, and bias for 8kV ESD pins. 38 5V_OUT 8kV 55mA minimum overcurrent protected 5V output. This output must be bypassed with a 0.1 µ F ceramic capacitor. 3, 5, 8, 11, 14, 25, 28, 31, 34, 36 GND / TMDS_GND N/A GND reference. Note 1: These 2 pins need to be connected together in-line on the PCB. See recommended layout diagram. Note 2: This output can be connected to an external 0.1 µ F ceramic capacitor/pads to maintain backward compa tibility with the CM2020. Note 3: Standard IEC 61000-4-2, C DISCHARGE =150pF, R DISCHARGE =330 Ω , 5V_SUPPLY and LV_SUPPLY within recommended operating conditions, GND=0V, 5V_OUT (pin 38), and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1 µ F ceramic capacitor connected to GND. Note 4: Human Body Model per MIL-STD-883, Method 30 15, C DISCHARGE =100pF, R DISCHARGE =1.5k Ω , 5V_SUPPLYand LV_SUPPLY within recommended operating conditions, GND=0V, 5V _OUT (pin 38), and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1 µ F ceramic capacitor connected to GND. Note 5: These pins should be routed directly to the associated GND pins on the HDMI connector with sin gle point ground vias at the connector. Note 6: The slew-rate control and active accelerati on circuitry dynamically offsets the system capacitive load on these pins.
entertainment systems with multiple components and several power plane domains in each system. when the DVD player is turned back on. milliamps, it could destroy one of the SOC chip’s internal DRC diodes, as they are not designed for passing DC. than 5µ A into any I/O pin when the I/O pin voltage exceeds its related operating CM2030 supply voltage . Figure 1. Backdrive Protection Diagram. C serial bus protocol for EDID configuration. even with very long and non-compliant cables.
tains a local logic “low” when no system is connect ed. Figure 7. Hotplug Detect Circuit
Rev. 5 | Page 9 of 17 | www.onsemi.com
Ordering Information
PART NUMBERING INFORMATION Pi n s Pa ck a ge Le a d- f r e e F i n i s h O r de r i ng P a r t N u m be r Pa r t M ar k i n g
38 TSSOP-38 CM2030-A0TR CM2030-A0TR
Note 1: Parts are shipped in Tape & Reel form unles s otherwise specified. Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER R A T I N G U N I TS VCC5, VCCLV 6.0 V DC Voltage at any Channel Input [GND - 0.5] to [VCC + 0.5] V Storage Temperature Range 65 to +150 ° C STANDARD (RECOMMENDED) OPERATING CONDITIONS SYMBOL PARAMETER M I N TY P M A X U N I TS 5V_SUPPLY Operating Supply Voltage 5 5.5 V LV_SUPPLY Bias Supply Voltage 1 3.3 5.5 V CE_SUPPLY Bias Supply Voltage 3 3.3 3.6 V Operating Temperature Range 40 85 ° C
Rev. 5 | Page 10 of 17 | www.onsemi.com ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ICC5 Operating Supply Current 5V_SUPPLY = 5.0V, CEC_OUT = 3.3V, LV_SUPPLY= 3.3V, CE_SUPPLY= 3.3V, DDC=5V; Note6 300 350 µ A ICCLV Bias Supply Current LV_SUPPLY=3.3V; Note 6 6 0 150 µ A ICCCE Bias Supply Current CE_SUPPLY=3.3V, CEC_OUT=0V; Notes 6 and 7 60 150 µ A ICEC Current source on CEC pin CE_SUPPLY=3.3V, 111 120 128 µ A VDROP 5V_OUT Overcurrent Out put Drop 5V_SUPPLY=5.0V, IOUT=55mA 65 100 mV ISC 5V_OUT Short Circuit Cur rent Limit 5V_SUPPLY=5.0V, 5V_OUT=GND 90 135 175 mA IOFF OFF state leakage current, level shifting NFET LV_SUPPLY=0V 0.1 5 µ A IBACKDRIVECEC Current through CE- REMOTE_OUT when powered down CE-REMOTE_IN = CE_SUPPLY < CE_REMOTE_OUT 0.1 1.8 µ A IBACKDRIVETMDS Current through TMDS pins when powered down All Supplies = 0V; TMDS_[2:0]+/, TMDS_CK+/ = 4V 0.1 5 µ A IBACKDRIVE5V_OUT Current through 5V_OUT when powered down All Supplies = 0V; 5V_OUT_PIN = 0.1 5 µ A IBACKDRIVEDDC Current through DDC_DAT/CLK_OUT when powered down All Supplies = 0V; DDC_DAT/CLK_OUT = 5V; DDC_DAT/CLK_IN = 0V 0.1 5 µ A IBACKDRIVEHOTPLUG Current through HOTPLUG_DET_OUT when powered down All Supplies = 0V; HOTPLUG_DET_OUT = 5V; HOTPLUG_IN = 0V 0.1 5 µ A CECSL CEC Slew Limit Measured from 10-90% or 90-10% 0.26 0.65 V/ µ s CECRT CEC Rise Time Measured from 10-90% Assumes a signal swing from 0- 3.3V 26.4 250 µ s CECFT CEC Fall Time Measured from 90-10% Assumes a signal swing from 0- 3.3V 4 50 µ s VACC Turn On Threshold of I2C/ DDC Accelerator Voltage is 0.3 ±10% X 5V_Supply; Note 2 1.35 1.5 1.65 V VON(DDC_OUT) Voltage drop across DDC level shifter LV_SUPPLY=3.3V, 3mA Sink at DDCIN, DDCOUT < VACC 150 225 mV VOL(DDC_IN) Logic Level (ASIC side) when I2C/DDC Logic Low Applied; (I2C pass-through compatibility) DDC_OUT=0.4V, LV_SUPPLY=3.3V, 1.5k Ω pullup on DDC_OUT to 5.0V; Note 2 0.3 0.4 V tr(DDC) DDC_OUT Line Risetime, VACC < VDDC_OUT < DDC_IN floating, LV_SUPPLY=3.3V, 1.5k Ω pullup on 1 µ s
Rev. 5 | Page 11 of 17 | www.onsemi.com (5V_Supply-0.5V) DDC_OUT to 5.0V, Bus Capacitance = 1500pF VF Diode Forward Voltage Top Diode Bottom Diode IF = 8mA, TA = 25° C 0.6 0.6 0.85 0.85 0.95 0.95 V V VESD ESD Withstand Voltage (IEC) Pins 4, 7, 10, 13, 20, 21, 22, 23, 24, 27, 30, 33, TA = 25° C; Note 2 ±8 kV VESD ESD Withstand Voltage (HBM) Pins 1, 2, 16, 17, 18, 19, 37, 38, TA = 25° C ±2 kV VCL Channel Clamp Voltage Positive Transients Negative Transients TA=25° C, IPP = 1A, tP = 8/20 µ S; Note 5 11.0 2.0 V V RDYN Dynamic Resistance Positive Transients Negative Transients TA=25° C, IPP = 1A, tP = 8/20 µ S Any I/O pin to Ground; Note5 1.4 0.9 Ω Ω ILEAK TMDS Channel Leakage Current TA = 25° C 0.01 1 µ A CIN, TMDS TMDS Channel Input Capacitance 5V_SUPPLY=5.0V, Measured at 1MHz, VBIAS=2.5V 0.9 1.2 pF ∆ CIN, TMDS TMDS Channel Input Capacitance Matching 5V_SUPPLY=5.0V, Measured at 1MHz, VBIAS=2.5V; Note 4 0.05 pF CMUTUAL Mutual Capacitance between signal pin and adja cent signal pin 5V_SUPPLY=0V, Measured at 1MHz, VBIAS=2.5V 0.07 pF CIN, DDCOUT Level Shifting Input Capaci tance, Capacitance to GND 5V_SUPPLY=0V, Measured at 100KHz, VBIAS=2.5V 10 pF CIN, CECOUT Level Shifting Input Capaci tance, Capacitance to GND 5V_SUPPLY=0V, Measured at 100KHz, VBIAS=1.65V pF CIN, HPOUT Level Shifting Input Capaci tance, Capacitance to GND 5V_SUPPLY=0V, Measured at 100KHz, VBIAS=2.5V pF Note 1: Operating Characteristics are over Standard Operating Conditions unless otherwise specified. Note 2: Standard IEC61000-4-2, C DISCHARGE =150pF, R DISCHARGE =330 Ω , 5V_SUPPLY=5V, 3.3V_SUPPLY=3.3V, LV_SUPPLY=3.3V, GND=0V. Note 3: Human Body Model per MIL-STD-883, Method 30 15, C DISCHARGE =100pF, R DISCHARGE =1.5k Ω, 5V_SUPPLY=5V, 3.3V_SUPPLY=3.3V, LV_SUPPLY=3.3V, GND=0V. Note 4: Intra-pair matching, each TMDS pair (i.e. D +, D–) Note 5 These measurements performed with no externa l capacitor on V P (V P floating) Note 6: These static measurements do not include AC activity on controlled I/O lines. Note 7: This measurement does not inclue supply cur rent for the 120 µ A current source on the CEC pin.
Figure 8. Insertion Loss vs. Frequency (TMDS_D1– t o GND)
Rev. 5 | Page 13 of 17 | www.onsemi.com
Application Information
Figure 9. Typical Application for CM2030
- Differential TMDS Pairs should be designed as n ormal 100 Ω HDMI Microstrip. Single Ended
should be tuned to match chip/connector IBIS parasi tics. includes sufficient pullups to register a logic high, then external pullups may not be needed. avoid placing any silk-screen printing over TMDS traces. the CM2020. The 100nF C BYP is recommended for all applications. CEC pullup isolation. The 27k R CEC and a Schottky D CEC provide the necessary isolation for the CEC pullup.
Rev. 5 | Page 14 of 17 | www.onsemi.com Note: This circuitry is used only in the CM2020. Depopulate the components for CM2030 applications in a CM2020/ CM2030 dual footprint layout. Footprint compatibility - The CM2030 has (built-in) internal backdrive protection. The CM2020 does not not have internal backdrive pro tection and requires the external R CEC and D CEC components. (For CM2030) If CEC firmware is not implemented, do not populate with 0 Ω resistor. If CEC firmware is implemented, then populate with 0 Ω resistor. (For CM2020) Populate with 0 Ω resistor in either case. Application Information (cont’d) Design Considerations 1. 5V out (pin 38) Maximum overcurrent protection output drop at 55mA on 5V_OUT is 100mV. To meet HDMI output require- 2. DUT On vs. DUT Off Many HDMI CTS tests require a power off condition o n the System Under Test. Many discrete ESD diode configurations can be forward biased when their VDD rail is lower than the I/O pin bias, thereby exhibiting extremely high apparent capacitance measurements, for example. The MediaGuard TM backdrive isolation circuitry limits this current to less than 5mA, and will help ensure HDMI compliance. Please review all of the current HDMI design guidel ines available at: http://www.calmicro.com/applications/customer/downl oads/current-cmd-mediaguard-design- guidelines.zip
Rev. 5 | Page 15 of 17 | www.onsemi.com Mechanical Details TSSOP-38 Mechanical Specifications CM2030 devices are supplied in 38-pin TSSOP packages. Dimensions are presented below. PACKAGE DIMENSIONS Pa ck a ge TSSOP JE D E C N o . MO-153 (Variation BD-1) Pi n s 38 D i m e n si o ns M i l l i m et e r s I n c he s M i n M a x M i n M a x A — 1.20 — 0.047 A 1 0.05 0.15 0.002 0.006 b 0.17 0.27 0.007 0.011 c 0.09 0.20 0.004 0.008 D 9.60 9.80 0.378 0.386 E 6.40 BSC 0.252 BSC E1 4.30 4.50 0.169 0.177 e 0.50 BSC 0.020 BSC L 0.45 0.75 0.018 0.030 # p er t ap e a nd r ee l 2500 pieces C o n t r o l l i ng d i m e ns i on : m i l l i m e t e r s
Rev. 5 | Page 16 of 17 | www.onsemi.com Package Dimensions for TSSOP-38 16 17 18 19 23 22 21 20 Mechanical Package Diagrams D E TOP VIEW L END VIEW c eb A A1 SEA T ING PLANE SIDE VIEW 5 6 7 8 9 10 1 2 3 4 34 33 32 31 30 29 38 37 36 35 Pin 1 Marking 11 12 13 14 28 27 26 25
Rev. 5 | Page 17 of 17 | www.onsemi.com Tape and Reel Specifications PART NUMBER PACKAGE SIZE (mm) POCKET SIZE (mm) B0 X A 0 X K 0 TAPE WIDTH W REEL DIAMETER QTY PER REEL P0 P1 ON Semiconductor and are registered trademarks of Semiconductor Componen ts Industries, LLC (SCILLC). SCILLC reserves the ri ght to make changes without further notice to any products herein. SCILLC makes no war ranty, representation or guarantee regarding the su itability of its products for any particular purpos e, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” para meters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operatin g parameters, including “Typicals” must be validate d for each customer application by customer's techn ical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use a s components in systems intended for surgical implant into the body , or other applications intended to support or sust ain life, or for any other application in which the failure of the SCILLC product could create a situation where personal inj ury or death may occur. Should Buyer purchase or u se SCILLC products for any such unintended or unaut horized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliat es, and distributors harmless against all claims, c osts, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal i njury or death associated with such unintended or u nauthorized use, even if such claim alleges that SCILLC was negligent reg arding the design or manufacture of the part. SCILL C is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT : Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone : 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax : 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support : 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website : www.onsemi.com Order Literature : http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative T op For t ape feeder reference Cover T ape P only including draf t. Concentric around B. K o Embossment User Direction of Feed ±0.2 mm P o Center Lines of Cavity W
10 Pitches Cumulative
A o B o