CM2030 CALMIRCO | Alldatasheet
Document overview
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- PDF pages: 14
Technical content
Features
- HDMI 1.3 compliant
- Supports thin dielectric and 2-layer boards
- Minimizes TMDS skew with 0.05pF matching
- Long HDMI cable support with integrated I2C accelerator
- Active termination and slew rate limiting for CEC
- Supports direct connection to CEC microcontroller
- Integrated I2C level shifting to CMOS level includ ing low logic level voltages
- Integrated 8kV ESD protection and backdrive pro tection on all external I/O lines
- Integrated overcurrent output protection per HDMI 1.3
- Multiport I2C support eliminates need for analog mux on DDC lines
- Simplified layout with matched 0.5mm trace spac ing
Applications
- PC and consumer electronics
- Set top box, DVD RW, PC, graphics cards Product Description The CM2030 HDM I T ransmitter P ort Protection and Interface Device is specifically designed for next gener ation HDMI Host interface protection. An integrated package provides all ESD, slew rate lim iting on CE C line , le vel shif ting/isolation, o vercurrent output protection and backdrive protection for an HDMI port in a single 38-Pin TSSOP package. The CM2030 pa rt is sp ecifically desig ned to pr ovide the design er with th e most reliable path to HDMI 1.3 CTS compliance. The CM2030 also inc orporates a silicon o vercurrent protection device for +5V su pply voltage output to the connector. Electrical Schematic TMDS_D2+ TMDS_GND TMDS_D2 DDC_CLK_IN HOTPLUG_DET_IN TMDS_CK+ TMDS_GND TMDS_CK TMDS_D1+ TMDS_GND TMDS_D1 TMDS_D0+ TMDS_GND TMDS_D0 CE_REMOTE_IN DDC_CLK_OUT CE_SUPPLY LV_SUPPLY 5V_SUPPLY DDC_DAT_IN LV_SUPPLY DYNAMIC PULLUP DYNAMIC PULLUP CMOS/I2C LEVEL SHIFT CMOS/I2C LEVEL SHIFT LV_SUPPLY HOTPLUG_DET_OUT IS 3IS 5V_SUPPLY 5V_SUPPLY DDC_DAT_OUT CE_SUPPLY ACTIVE SLEW RATE LIMITING CE_REMOTE_OUT 5V_SUPPLY 55mA OVERCURRENT SWITCH 5V_OUT © 2007 California Micro Devices Corp. All rights reserved. Issue A – 11/16/07
Note: This drawing is not to scale. 38-PIN TSSOP PACKAGE TMDS_GND TMDS_D2– TMDS_D1+ TMDS_GND TMDS_D1– TMDS_D0+ TMDS_GND TMDS_D0– 5V_SUPPLY LV_SUPPLY GND TMDS_D2+ CE_SUPPLY GND TMDS_D2+ TMDS_GND TMDS_D2– TMDS_D1+ TMDS_GND TMDS_D1– TMDS_D0+ TMDS_GND TMDS_D0– 5V_OUT TMDS_CK+ TMDS_GND TMDS_CK+ TMDS_GND TOP VIEW TMDS_CK– CE_REMOTE_IN DDC_CLK_IN TMDS_CK– CE_REMOTE_OUT DDC_CLK_OUT DDC_DAT_OUT HOTPLUG_DET_OUT DDC_DAT_IN HOTPLUG_DET_IN PIN DESCRIPTIONS PINS NAME ESD Level DESCRIPTION 4, 35 TMDS_D2+ 8kV3 TMDS 0.9pF ESD protection.1 6, 33 TMDS_D2– 8kV3 TMDS 0.9pF ESD protection.1 7, 32 TMDS_D1+ 8kV3 TMDS 0.9pF ESD protection.1 9, 30 TMDS_D1– 8kV3 TMDS 0.9pF ESD protection.1 10, 29 TMDS_D0+ 8kV3 TMDS 0.9pF ESD protection.1 12, 27 TMDS_D0– 8kV3 TMDS 0.9pF ESD protection.1 13, 26 TMDS_CK+ 8kV3 TMDS 0.9pF ESD protection.1 15, 24 TMDS_CK– 8kV3 TMDS 0.9pF ESD protection.1 16 CE_REMOTE_IN 2kV4 CE_SUPPLY referenced logic level in. 23 CE_REMOTE_OUT 8kV3 5V_SUPPLY referenced logic level out plus 10pF ESD.6 17 DDC_CLK_IN 2kV4 LV_SUPPLY referenced logic level in. 22 DDC_CLK_OUT 8kV3 5V_SUPPLY referenced logic level out plus 10pF ESD.6 18 DDC_DAT_IN 2kV4 LV_SUPPLY referenced logic level in. 21 DDC_DAT_OUT 8kV3 5V_SUPPLY referenced logic level out plus 10pF ESD.6 19 HOTPLUG_DET_IN 2kV4 LV_SUPPLY referenced logic level in. 20 HOTPLUG_DET_OUT 8kV3 5V_SUPPLY referenced logic level out plus 10pF ESD. A 0.1μF bypass ceramic capacitor is recommended on this pin.2 2 LV_SUPPLY 2kV4 Bias for CE / DDC / HOTPLUG level shifters. 37 CE_SUPPLY 2kV4,2 CEC bias voltage. Previously CM2020 ESD_BYP pin. 1 5V_SUPPLY 2kV4 Current source for 5V_OUT, VREF for DDC I2C voltage references, and bias for 8kV ESD pins. © 2007 California Micro Devices Corp. All rights reserved. Issue A – 11/16/07
PIN DESCRIPTIONS (CONTINUED) 38 5V_OUT 8kV3 55mA minimum overcurrent protected 5V output. This output must be bypassed with a 0.1μF ceramic capacitor. 3, 5, 8, 11, 14, 25, 28, 31, 34, GND / TMDS_GND N/A GND reference. Note 1: These 2 pins need to be connected together in-line on the PCB. See recommended layout diagram. Note 2: This output can be connected to an external 0.1 μF ceramic capacitor/pads to maintain backward comp atibility with the CM2020. Note 3: Standard IEC 61000-4-2, C DISCHARGE=150pF, R DISCHARGE=330Ω, 5V_SUPPLY an d LV_SUPPLY w ithin recommended operating conditions, GND=0V, 5V_OUT (pin 38), and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1μF ceramic capacitor connected to GND. Note 4: Human Body Model per MIL-STD-883, Method 3015, C DISCHARGE=100pF, R DISCHARGE=1.5kΩ, 5V_SUPPL Yand LV_SUPPLY within recommended operating conditions, GND=0V, 5V_OUT (pin 38), and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1μF ceramic capacitor connected to GND. Note 5: These pins should be routed directly to the associated GND pins on the HDMI connector with single point ground vias at the connector. Note 6: The slew-rate control and active acceleration circuitry dynamically offsets the system capacitive load on these pins. © 2007 California Micro Devices Corp. All rights reserved. Issue A – 11/16/07
reset properly when the DVD player is turned back on. exceeds its related operating CM2030 supply voltage. Figure 1. Backdrive Protection Diagram. cation even with very long and non-compliant cables. © 2007 California Micro Devices Corp. All rights reserved.
The CM2030 ensures that the local ASIC w ill properly local ASIC. tains a local logic “low” when no system is connected. Figure 7. Hotplug Detect Circuit © 2007 California Micro Devices Corp. All rights reserved.
Ordering Information
PART NUMBERING INFORMATION Pins Package Lead-free Finish Ordering Part Number1 Part Marking
38 TSSOP-38 CM2030-A0TR CM2030-A0TR
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS VCC5, VCCLV 6.0 V DC Voltage at any Channel Input [GND - 0.5] to [VCC + 0.5] V Storage Temperature Range –65 to +150 °C STANDARD (RECOMMENDED) OPERATING CONDITIONS SYMBOL PARAMETER MIN TYP MAX UNITS 5V_SUPPLY Operating Supply Voltage 5 5.5 V LV_SUPPLY Bias Supply Voltage 1 3.3 5.5 V CE_SUPPLY Bias Supply Voltage 3 3.3 3.6 V Operating Temperature Range –40 85 °C ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ICC5 Operating Supply Current 5V_SUPPLY = 5.0V, CEC_OUT = 3.3V, LV_SUPPLY= CE_SUPPLY= 3.3V, DDC=5V; Note 7 300 350 μA ICCLV Bias Supply Current LV_SUPPLY=3.3V; Note 7 60 150 μA ICCCE Bias Supply Current CE_SUPPLY=3.3V, CEC_OUT=0V; Note 7 60 150 μA VDROP 5V_OUT Overcurrent Out put Drop 5V_SUPPLY=5.0V, IOUT=55mA 65 100 mV ISC 5V_OUT Short Circuit Cur rent Limit 5V_SUPPLY=5.0V, 5V_OUT=GND 90 135 175 mA IOFF OFF state leakage current, level shifting NFET LV_SUPPLY=0V; Note 2 0.1 5 μA IBACKDRIVECEC Current through CE-REMOTE_OUT when powered down CE-REMOTE_IN = CE_SUPPLY < CE_REMOTE_OUT 0.1 1.8 μA IBACKDRIVETMDS Current through TMDS pins when powered down All Supplies = 0V; TMDS_[2:0]+/–, TMDS_CK+/– = 4V 0.1 5 μA © 2007 California Micro Devices Corp. All rights reserved. Issue A – 11/16/07
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) IBACKDRIVE5V_OUT Current through 5V_OUT when powered down All Supplies = 0V; 5V_OUT_PIN = 0.1 5 μA IBACKDRIVEDDC Current through DDC_DAT/CLK_OUT when powered down All Supplies = 0V; DDC_DAT/CLK_OUT = 5V; DDC_DAT/CLK_IN = 0V 0.1 5 μA IBACKDRIVEHOTPLUG Current through HOTPLUG_DET_OUT when powered down All Supplies = 0V; HOTPLUG_DET_OUT = 5V; HOTPLUG_IN = 0V 0.1 5 μA CECSL CEC Slew Limit Measured from 10-90% or 90-10% 0.26 0.65 V/μs CECRT CEC Rise Time Measured from 10-90% Assumes a signal swing from 0 3.3V 26.4 250 μs CECFT CEC Fall Time Measured from 90-10% Assumes a signal swing from 0 3.3V 4 50 μs VACC Turn On Threshold of I2C/ DDC Accelerator Voltage is 0.3 ±10% X 5V_Supply; Note 2 1.35 1.5 1.65 V VON(DDC_OUT) Voltage drop across DDC level shifter LV_SUPPLY=3.3V, 3mA Sink at DDCIN, DDCOUT < VACC 150 225 mV VOL(DDC_IN) Logic Level (ASIC side) when I2C/DDC Logic Low Applied; (I2C pass-through compatibility) DDC_OUT=0.4V, LV_SUPPLY=3.3V, 1.5kΩ pullup on DDC_OUT to 5.0V; Note 2 0.3 0.4 V tr(DDC) DDC_OUT Line Risetime, VACC < VDDC_OUT < (5V_Supply-0.5V) DDC_IN floating, LV_SUPPLY=3.3V, 1.5kΩ pullup on DDC_OUT to 5.0V, Bus Capacitance = 1500pF 1 μs VF Diode Forward Voltage Top Diode Bottom Diode IF = 8mA, TA = 25°C; Note 2 0.6 0.6 0.85 0.85 0.95 0.95 V V VESD ESD Withstand Voltage (IEC) Pins 4, 7, 10, 13, 20, 21, 22, 23, Notes 2 and 3 ±8 kV VESD ESD Withstand Voltage (HBM) Pins 1, 2, 16, 17, 18, 19, 37, 38, TA = 25°C; Note 2 ±2 kV VCL Channel Clamp Voltage Positive Transients Negative Transients TA=25°C, IPP = 1A, tP = 8/20μS; Notes 2 & 6 11.0 –2.0 V V RDYN Dynamic Resistance Positive Transients Negative Transients TA=25°C, IPP = 1A, tP = 8/20μS Any I/O pin to Ground; Note 6 1.4 0.9 Ω Ω ILEAK TMDS Channel Leakage Current TA = 25°C; Note 2 0.01 1 μA CIN, TMDS TMDS Channel Input Capacitance 5V_SUPPLY=5.0V, Measured at 1MHz, VBIAS=2.5V; Note 2 0.9 1.2 pF © 2007 California Micro Devices Corp. All rights reserved. Issue A – 11/16/07
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) ΔCIN, TMDS TMDS Channel Input Capacitance Matching 5V_SUPPLY=5.0V, Measured at 1MHz, VBIAS=2.5V; Notes 2 and 5 0.05 pF CMUTUAL Mutual Capacitance between signal pin and adja cent signal pin 5V_SUPPLY=0V, Measured at 1MHz, VBIAS=2.5V; Note 2 0.07 pF CIN, DDCOUT Level Shifting Input Capaci tance, Capacitance to GND 5V_SUPPLY=0V, Measured at 100KHz, VBIAS=2.5V; Note 2 10 pF CIN, CECOUT Level Shifting Input Capaci tance, Capacitance to GND 5V_SUPPLY=0V, Measured at 100KHz, VBIAS=1.65V; Note 2 10 pF CIN, HPOUT Level Shifting Input Capaci tance, Capacitance to GND 5V_SUPPLY=0V, Measured at 100KHz, VBIAS=2.5V; Note 2 10 pF Note 1: Operating Characteristics are over Standard Operating Conditions unless otherwise specified. Note 2: This parameter is guaranteed by design and verified by device characterization. Note 3: Standard IEC61000-4-2, CDISCHARGE=150pF, RDISCHARGE=330Ω, 5V_SUPPLY=5V, 3.3V_SUPPLY=3.3V, LV_SUPPLY=3.3V, GND=0V. Note 4: Human Body Model per MIL-STD-883, Method 3015, CDISCHARGE=100pF, RDISCHARGE=1.5kΩ, 5V_SUPPLY=5V, 3.3V_SUPPLY=3.3V, LV_SUPPLY=3.3V, GND=0V. Note 5: Intra-pair matching, each TMDS pair (i.e. D+, D–) Note 6: These measurements performed with no external capacitor on VP (VP floating) Note 7: These static measurements do not include AC activity on controlled I/O lines © 2007 California Micro Devices Corp. All rights reserved. Issue A – 11/16/07
Figure 8. Insertion Loss vs. Frequency (TMDS_D1– to GND) © 2007 California Micro Devices Corp. All rights reserved.
Application Information
ROPT(See NOTE 4) 5V_OUT CM2020/2030 TMDS_D2+ TMDS_D2– TMDS_D1+ TMDS_D1– TMDS_D0+ TMDS_D0– TMDS_CK+ TMDS_CK– EEPROM_CLK EEPROM_DAT 5V_SUPPLY CBYP ASIC_CEC2 ASIC_SCL2 ASIC_SDA2 100nF CHPRPD CVOUT RDAT RSCL NOTE 3 VCEC HOTPLUG_DETECT2 RCEC 27kΩ CEC VCEC DCEC LV_SUPPLY TMDS_D2+ TMDS_GND TMDS_D2– TMDS_D1+ TMDS_GND TMDS_D1– NOTE 1 TMDS_D0+ TMDS_GND TMDS_D0– TMDS_CK+ TMDS_GND TMDS_CK– CE_REMOTE N/C DDC_CLK DDC_DAT GND +5V OUT HOTPLUG_DET HDMI Connector 100nF 2kΩ 15kΩ 100nF 2kΩ Figure 9. Typical Application for CM2030
1 Differential T MDS P airs s hould b e de signed as
2 Level Shif ter signa ls shou ld be bia sed wit h a w eak
then external pullups may not be needed.
3 Place MediaGuardTM as close to the connector as pos
© 2007 California Micro Devices Corp. All rights reserved.
- 5V out (pin 38) Maximum overcurrent protection output drop at 55mA on 5V_OUT is 100mV. To meet HDMI output require ments of 4.8-5.3V, an input of greater than 4.9V should be used (i.e. 5.1V ±4%) 2. DUT On vs. DUT Off Many HDMI CTS tests require a power off condition on the System Under Test. Many discrete ESD diode con figurations can be forward biased when their VDD r ail is lo wer th an t he I/O pin bia s, thereby e xhibiting extremely high app arent ca pacitance measurements, for e xample. T he MediaGuardΤΜ b ackdrive isolation circuitry limits this current to less than 5μA, and will help ensure HDMI compliance. Please review all of the current HDMI design guidelines available at: http://www.calmicro.com/applications/customer/downloads/current-cmd-mediaguard-design-guidelines.zip © 2007 California Micro Devices Corp. All rights reserved. Issue A – 11/16/07
TSSOP-38 Mechanical Specifications CM2030 devices are supplied in 38-pin TSSOP pack ages. Dimensions are presented below. PACKAGE DIMENSIONS Package TSSOP JEDEC No. MO-153 (Variation BD-1) Pins 38 Dimensions Millimeters Inches Min Max Min Max A — 1.20 — 0.047 A1 0.05 0.15 0.002 0.006 b 0.17 0.27 0.007 0.011 c 0.09 0.20 0.004 0.008 D 9.60 9.80 0.378 0.386 E 6.40 BSC 0.252 BSC E1 4.30 4.50 0.169 0.177 e 0.50 BSC 0.020 BSC L 0.45 0.75 0.018 0.030 # per tape and reel 2500 pieces Controlling dimension: millimeters 16 17 18 19 23 22 21 20 Mechanical Package Diagrams D E TOP VIEW L END VIEW c e b A A1SEATING PLANE SIDE VIEW 5 6 7 8 9 10 1 2 3 4 34 33 32 31 30 29 38 37 36 35 i i 11 12 13 14 28 27 26 25 Package Dimensions for TSSOP-38 © 2007 California Micro Devices Corp. All rights reserved. Issue A – 11/16/07