CM2009

CM2009 CALMIRCO | Alldatasheet

Document overview

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Technical content

Features

Includes ESD protection, level-shifting, buffering and sync impedance matching 7 channels of ESD protection for all VGA port con- nector pins meeting IEC-61000-4-2 Level 4 ESD requirements (±8kV contact discharge) Very low loading capacitance from ESD protection diodes on VIDEO lines, 4pF maximum 5V drivers for HSYNC and VSYNC lines Integrated impedance matching resistors on sync lines Bi-directional level shifting N-channel FETs pro- vided for DDC_CLK & DDC_DATA channels Backdrive protection on DDC lines Compact 16-lead QSOP package

Applications

VGA and DVI-I ports in: - Desktop and Notebook PCs - Graphics Cards - Set Top Boxes Product Description The CM2009 connects between a video graphics con- troller embedded in a PC, graphics adapter card or set top box and the VGA or DVI-I port connector. The CM2009 incorporates ESD protection for all signals, level shifting for the DDC signals and buffering for the SYNC signals. ESD protection for the video, DDC and SYNC lines is implemented with low-capacitance cur- rent steering diodes. All ESD diodes are designed to safely handle the high current spikes specified by IEC-61000-4-2 Level 4 (±8KV contact discharge if CBYP is present, ±4KV if not). The ESD protection for the DDC signal pins are designed to prevent "back current" when the device is powered down while connected to a monitor that is powered up. Separate positive supply rails are provided for the VIDEO, DDC and SYNC channels to facilitate interfac- ing with low voltage video controller ICs to provide design flexibility in multi-supply-voltage environments. (cont’d next page) Simplified Electrical Schematic VIDEO_1 VIDEO_2 VIDEO_3 VCC_VIDEO GND SYNC_OUT2 GND VCC_DDC VCC_SYNC SYNC_OUT1 SYNC_IN2 SYNC_IN1 DDC_IN2 DDC_IN1 RT DDC_OUT2 DDC_OUT1 BYP RT

© 2004 California Micro Devices Corp. All rights reserved. 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲www.calmicro.com 08/12/04 CM2009 Product Description (cont’d) Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the video controller IC (SYNC1, SYNC2). These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and VCC_SYNC, which is typi- cally 5V. Additionally, each driver has a series termina- tion resistor (RT) connected to the SYNC_OUT pin, eliminating the external termination resistors typically required for the HSYNC and VSYNC lines of the video cable. There are three versions with different values of RT to allow termination at typically 65Ω (CM2009-00) or 55Ω (CM2009-01) or 15Ω (CM2009-02). The 15Ω (CM2009-02) version will typically require two external resistors which can be chosen to exactly match the characteristic impedance of the SYNC lines of the video cable. Two N-channel MOSFETs provide the level shifting function required when the DDC controller is operated at a lower supply voltage than the monitor. The gate terminals for these MOSFETS (VCC_DDC) should be connected to the supply rail (typically 3.3V) that sup- plies power to the transceivers of the DDC controller.

Ordering Information

Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. PACKAGE / PINOUT DIAGRAM Note: This drawing is not to scale. Top View

16 Pin QSOP

SYNC_OUT2 SYNC_IN2 SYNC_OUT1 SYNC_IN1 DDC_OUT2 DDC_IN2 DDC_IN1 VCC_SYNC VCC_VIDEO VIDEO_1 VIDEO_2 VIDEO_3 GND VCC_DDC DDC_OUT1 BYP PART NUMBERING INFORMATION ROUT Pins Package Standard Finish Lead-free Finish Ordering Part Number1 Part Marking Ordering Part Number1 Part Marking 65Ω QSOP CM2009-00QS CM2009-00QS CM2009-00QR CM2009-00QR 55Ω QSOP CM2009-01QS CM2009-01QS CM2009-01QR CM2009-01QR 15Ω QSOP CM2009-02QS CM2009-02QS CM2009-02QR CM2009-02QR

© 2004 California Micro Devices Corp. All rights reserved. 08/12/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲Tel: 408.263.3214 ▲Fax: 408.263.7846 ▲ www.calmicro.com CM2009 Pin Description Specifications PIN DESCRIPTIONS LEAD(s) NAME

DESCRIPTION

VCC_SYNC This is an isolated supply input for the SYNC_1 and SYNC_2 level shifters and their associ- ated ESD protection circuits. VCC_VIDEO This is a supply pin specifically for the VIDEO_1, VIDEO_2 and VIDEO_3 ESD protection cir- cuits. VIDEO_1 Video signal ESD protection channel. This pin is typically tied one of the video lines between the VGA controller device and the video connector. VIDEO_2 Video signal ESD protection channel. This pin is typically tied one of the video lines between the VGA controller device and the video connector. VIDEO_3 Video signal ESD protection channel. This pin is typically tied one of the video lines between the VGA controller device and the video connector. GND Ground reference supply pin. VCC_DDC This is an isolated supply input for the DDC_1 and DDC_2 level-shifting N-FET gates. BYP This input is used to connect an external 0.2uF bypass capacitor to the DDC circuits, resulting in an increased ESD withstand voltage rating for these circuits (±8kV with vs. ±4kV without). DDC_OUT1 DDC signal output. Connects to the video connector side of one of the sync lines. DDC_IN1 DDC signal input. Connects to the VGA controller side of one of the sync lines. DDC_IN2 DDC signal input. Connects to the VGA controller side of one of the sync lines. DDC_OUT2 DDC signal output. Connects to the video connector side of one of the sync lines. SYNC_IN1 Sync signal buffer input. Connects to the VGA controller side of one of the sync lines. SYNC_OUT1 Sync signal buffer output. Connects to the video connector side of one of the sync lines. SYNC_IN2 Sync signal buffer input. Connects to the VGA controller side of one of the sync lines. SYNC_OUT2 Sync signal buffer output. Connects to the video connector side of one of the sync lines. ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS VCC_VIDEO,VCC_DDC and VCC_SYNC Supply Voltage Inputs [GND - 0.5] to +6.0 V ESD Diode Forward Current (one diode conducting at a time) mA DC Voltage at Inputs VIDEO_1, VIDEO_2, VIDEO_3 DDC_IN1, DDC_IN2 DDC_OUT1, DDC_OUT2 SYNC_IN1, SYNC_IN2 [GND - 0.5] to [VCC_VIDEO + 0.5] [GND - 0.5] to 6.0 [GND - 0.5] to 6.0 [GND - 0.5] to [VCC_SYNC + 0.5] V V V V Operating Temperature Range -40 to +85 Storage Temperature Range -40 to +150 Package Power Rating (TA=25°C) 500 mW

© 2004 California Micro Devices Corp. All rights reserved. 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲www.calmicro.com 08/12/04 CM2009 Specifications (cont’d) Note 1: All parameters specified over standard operating conditions unless otherwise noted. Note 2: These parameters apply only to the SYNC drivers. Note that ROUT = RT + RBUFFER. Note 3: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. BYP, VCC_VIDEO and VCC_SYNC must be bypassed to GND via a low impedance ground plane with a 0.2µF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between the applicable pins and GND. ESD pulses can be positive or negative with respect to GND. Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SYNC_OUT2, DDC_OUT1 and DDC_OUT2. All other pins are ESD protected to the industry standard ±2kV Human Body Model (MIL-STD-883, Method 3015). The bypass capacitor at the BYP pin may optionally be omitted, in which case the max. ESD withstand voltage for the DDC_OUT1 and DDC_OUT2 pins is reduced to ±4kV. Note 4: This parameter is guaranteed by design and characterization. Note 5: The SYNC_OUT pins on the CM2009-02 are guaranteed for 2kV HBM ESD protection. ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ICC_VIDEO VCC_VIDEO Supply Current VCC_VIDEO = 5.0V; VIDEO inputs at VCC_VIDEO or GND µA ICC_DDC VCC_DDC Supply Current VCC_DDC = 5.0V µA ICC_SYNC VCC_SYNC Supply Current VCC_SYNC = 5V; SYNC inputs at GND or VCC_SYNC; SYNC outputs unloaded µA VCC_SYNC = 5V; SYNC inputs at 3.0V; SYNC outputs unloaded 2.0 mA VF ESD Diode Forward Voltage IF = 10mA 1.0 V VIH Logic High Input Voltage VCC_SYNC = 5.0V; Note 2 2.0 V VIL Logic Low Input Voltage VCC_SYNC = 5.0V; Note 2 0.6 V VOH Logic High Output Voltage IOH = 0mA, VCC_SYNC = 5.0V; Note 2 4.85 V VOL Logic Low Output Voltage IOL = 0mA, VCC_SYNC = 5.0V; Note 2 0.15 V ROUT SYNC Driver Output Resistance (CM2009-00 only) VCC_SYNC = 5.0V; SYNC Inputs at GND or 3.0V Ω ROUT SYNC Driver Output Resistance (CM2009-01 only) VCC_SYNC = 5.0V; SYNC Inputs at GND or 3.0V Ω ROUT SYNC Driver Output Resistance (CM2009-02 only) VCC_SYNC = 5.0V; SYNC Inputs at GND or 3.0V; Note 5 Ω VOH-02 Logic High Output Voltage (CM2009-02 only) IOH = 24mA; VCC_SYNC = 5.0V; Note 2 2.0 V VOL-02 Logic Low Output Voltage (CM2009-02 only) IOL = 24mA; VCC_SYNC = 5.0V; Note 2 0.8 V IIN Input Current VIDEO Inputs VCC_VIDEO = 5.0V; VIN = VCC_VIDEO or GND µA SYNC_IN1, SYNC_IN2 Inputs VCC_SYNC = 5.0V; VIN = VCC_SYNC or GND µA IOFF Level Shifting N-MOSFET "OFF" State Leakage Current (VCC_DDC - VDDC_IN) ≤ 0.4V; VDDC_OUT = VCC_DDC µA (VCC_DDC - VDDC_OUT) ≤ 0.4V; VDDC_IN = VCC_DDC µA VON Voltage Drop Across Level-shifting N-MOSFET when "ON" VCC_DDC = 2.5V; VS = GND; IDS = 3mA; 0.18 V CIN_VID VIDEO Input Capacitance VCC_VIDEO = 5.0V; VIN = 2.5V; ƒ = 1MHz; Note 4 pF VCC_VIDEO = 2.5V; VIN = 1.25V; ƒ = 1MHz; Note 4 4.5 pF tPLH SYNC Driver L => H Propagation Delay CL = 50pF; VCC = 5.0V; Input tR and tF ≤ 5ns ns tPHL SYNC Driver H => L Propagation Delay CL = 50pF; VCC = 5.0V; Input tR and tF ≤ 5ns ns tR, tF SYNC Driver Output Rise & Fall Times CL = 50pF; VCC = 5.0V; Input tR and tF ≤ 5ns ns VESD ESD Withstand Voltage VCC_VIDEO = VCC_SYNC = 5V; Notes 3, 4 & 5 kV

© 2004 California Micro Devices Corp. All rights reserved. 08/12/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲Tel: 408.263.3214 ▲Fax: 408.263.7846 ▲ www.calmicro.com CM2009

Application Information

Figure 1. Typical Application Connection Diagram The CM2009 should be placed as close to the VGA or DVI-I connector as possible. The ESD protection channels VIDEO_1, VIDEO_2, VIDEO_3 may be used interchangeably between the R, G, B signals. "VF" are external video filters for the RGB signals. capacitor should be connected between BYP and ground. The SYNC buffers may be used interchangeably between HSYNC and VSYNC. The EMI filters at the SYNC_OUT and DDC_OUT pins (C5 to C12, and Ferrite Beads FB1 to FB4) are for reference only. The component values and filter configuration may be changed to suit the application. The DDC level shifters DDC_IN, DDC_OUT, may be used interchangeably between DDCA_CLK and DDCA_DATA. VCC_5V via these resistors when VCC_5V is powered down. placed on HSYNC/VSYNC lines between the external matching resistor and the VGA connector.

© 2004 California Micro Devices Corp. All rights reserved. 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲www.calmicro.com 08/12/04 CM2009 Mechanical Details QSOP Mechanical Specifications CM2009 devices are packaged in 16-pin QSOP pack- ages. Dimensions are presented below. For complete information on the QSOP-16 package, see the California Micro Devices QSOP Package Infor- mation document. * This is an approximate number which may vary. Package Dimensions for QSOP-16 PACKAGE DIMENSIONS Package QSOP (JEDEC name is SSOP) Pins Dimensions Millimeters Inches Min Max Min Max A 1.35 1.75 0.053 0.069 0.10 0.25 0.004 0.010 B 0.20 0.30 0.008 0.012 C 0.18 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.81 3.98 0.150 0.157 e

0.64 BSC

0.025 BSC

H 5.79 6.19 0.228 0.244 L 0.40 1.27 0.016 0.050 # per tube 100 pcs* # per tape and reel 2500 pcs Controlling dimension: inches Mechanical Package Diagrams E D H TOP VIEW L END VIEW C e B A SEATING PLANE SIDE VIEW Pin 1 Marking