CM2009-05CP ONSEMI | Alldatasheet

Document overview

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Technical content

Features

  • Includes ESD protection, level-shifting, buffering and sync impedance matching  VESA VSIS Version 1 Revision 2 compatible interface  Supports both source and sink devices  Supports optional NAVI signaling requirements  Seven channels of ESD protection for all VGA port connector pins meeting IEC-61000-4-2 Level

4 ESD requirements (±8kV contact discharge)

 Very low loading capacitance from ESD protection diodes on VIDEO lines, 3pF maximum  Schmitt-triggered input buffers for HSYNC and VSYNC lines  Bi-directional level shifting N-channel FETs provided for DDC_CLK & DDC_DATA channels  Backdrive protection on all lines  RoHS-compliant, lead-free finishing in a 14- bump, 5x4x5, 0.4mm Chip Scale Package (CSP)

Applications

 Monitors  Video graphics controllers embedded in PCs  Graphics adapter cards  Set-top boxes Product Description The CM2009-05CP connects between the VGA or DVI-I port connector and the internal analog or digital flat panel controller logic. It can also be used for source devices such as a set-top box. The CM2009- 05CP incorporates ESD protection for all signals, level shifting for the DDC signals and buffering for the SYNC signals. ESD protection for the video, DDC and SYNC lines is implemented with low-capacitance current steering diodes. All connector interface pins are designed to safely handle the high current spikes specified by IEC- 61000-4-2 Level 4 ( ±8kV contact discharge). The ESD protection for the DDC, SYNC and VIDEO signal pins is designed to prevent "back current" when the device is powered down while connected to a video source or a video sink that is powered up. Positive supply rails are provided for the VIDEO / SYNC signals and DDC si gnals to facilitate interfacing with low voltage video controller ICs and microcontrollers to provide design flexibility in multi- supply-voltage environments. Two Schmitt-triggered non-inverting buffers redrive and condition the HSYNC and VSYNC signals from the video connector (SYNC1, SYNC2). These buffers accept VESA VSIS compliant TTL input signals and convert them to CMOS output levels that swing between ground and V CC. Two N-channel MOSFETs provide the level shifting function required when the DDC controller or EDID EEPROM is operated at a lower supply voltage than the monitor. The gate terminals for these MOSFETS should be connected to the supply rail (typically 3.3V, 2.5V etc.) that supplies power to the transceivers of the DDC controller.

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Rev. P2 | Page 3 of 8 | www.onsemi.com PIN DESCRIPTIONS LEAD(s) NAME DESCRIPTION A1 GND Ground reference supply pin. A2 VIDEO_1 Video signal ESD protection channel. This pin is typically tied one of the video lines between the controller device and the video connector. A3 VIDEO_2 Video signal ESD protection channel. This pin is typically tied one of the video lines between the controller device and the video connector. A4 VIDEO_3 Video signal ESD protection channel. This pin is typically tied one of the video lines between the controller device and the video connector. A5 VCC This is a supply input for the SYNC_1 and SYNC_2 level shifters, video protection and the DDC circuits. B1 DDC_OUT1 DDC signal output. Connects to the DDC logic. B2 DDC_OUT2 DDC signal output. Connects to the DDC logic. B3 SYNC_OUT1 Sync signal buffer output. Connects to the monitor Sync logic. B4 SYNC_OUT2 Sync signal buffer output. Connects to the monitor Sync logic. C1 DDC_IN1 DDC signal input. Connects to the video connector side of one of the DDC lines. C2 DDC_IN2 DDC signal input. Connects to the video connector side of one of the DDC lines. C3 LV_EN Disables the Sync buffer outputs when low. C4 SYNC_IN1 Sync signal buffer input. Connects to the video connector side of one of the Sync lines. C5 SYNC_IN2 Sync signal buffer input. Connects to the video connector side of one of the Sync lines. Note 1: Can also be connected to the VGA connector side if used for a source device. Note 2: Can also be used to connect to the Video Chip Sync Logic if it is used for a source device.

Ordering Information

PART NUMBERING INFORMATION Bumps Package Ordering Part Number Part Marking

14 CSP CM2009-05CP TJ

Note 1: Parts are shipped in Tape and Reel form.

Rev. P2 | Page 4 of 8 | www.onsemi.com Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS VCC Supply Voltage Inputs [GND - 0.5] to +6.0 V DC Voltage at Inputs VIDEO_1, VIDEO_2, VIDEO_3 DDC_IN1, DDC_IN2 DDC_OUT1, DDC_OUT2 SYNC_IN1, SYNC_IN2, LV_EN [GND - 0.5] to [V CC + 0.5] [GND - 0.5] to 6.0 [GND - 0.5] to 6.0 [GND - 0.5] to [VCC + 0.5] V V V V Operating Temperature Range -40 to +85 °C Storage Temperature Range -40 to +150 °C Package Power Rating (TA=25°C) 500 mW STANDARD OPERATING CONDITIONS PARAMETER RATING UNITS Operating Temperature Range -40 to +85 °C VCC 5 V

Rev. P2 | Page 5 of 8 | www.onsemi.com ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC = 5V; SYNC inputs at GND or VCC; SYNC outputs unloaded, DDC_In and DDC_OUT floating 1.0 mA ICC V CC Supply Current VCC = 5V; SYNC inputs at 3.0V; SYNC outputs unloaded, DDC_In and DDC_OUT floating 2.0 mA VF ESD Diode Forward Voltage I F = 10mA 1.1 V VIH Logic High Input Voltage V CC = 5.0V; Note 2 2.0 V VIL Logic Low Input Voltage V CC = 5.0V; Note 2 0.55 V VHYS Hysteresis Voltage V CC = 5.0V; Note 2 450 mV VOH Logic High Output Voltage I OH = 0mA, VCC = 5.0V; Note 2 4.0 V VOL Logic Low Output Voltage I OL = 0mA, VCC = 5.0V; Note 2 0.15 V ROUT SYNC Driver Output Resistance V CC = 5.0V; SYNC Inputs at GND or 3.0V 65 Ω Input Current VIDEO Inputs VCC = 5.0V; VIN = VCC or GND ±10 μA IIN SYNC_IN1, SYNC_IN2 Inputs VCC = 5.0V; VIN = VCC or GND ±10 μA (LV_EN - VDDC_IN) 0.4V; VDDC_OUT = LV_EN 10 μA IOFF Level Shifting N-MOSFET "OFF" State Leakage Current (LV_EN - VDDC_OUT) 0.4V; VDDC_IN = LV_EN 10 μA IBACKDRIVE Current conducted from input pins when Vcc is powered down. VCC < VINPUT_PIN 10 μA VON Voltage Drop Across Level-shifting N-MOSFET when "ON" LV_EN = 2.5V; VS = GND; IDS = 3mA 0.18 V VCC = 5.0V; VIN = 2.5V; f = 1MHz 3 pF CIN_VID VIDEO Input Capacitance VCC = 2.5V; VIN = 1.25V; f = 1MHz 3.5 pF tPLH SYNC Driver L => H Propagation Delay CL = 50pF; VCC = 5.0V; Input tR and tF 5ns 12 ns tPHL SYNC Driver H => L Propagation Delay CL = 50pF; VCC = 5.0V; Input tR and tF 5ns 12 ns tR, tF SYNC Driver Output Rise & Fall Times V CC = 5V 7 ns VESD ESD Withstand Voltage V CC = 5V; Note 3 ±8 kV Note 1: All parameters specified over standard operating conditions unless otherwise noted. Note 2: These parameters apply only to the SYNC drivers. Note that ROUT = RT + RBUFFER. Note 3: Per the IEC-61000-4-2 International ESD Standar d, Level 4 contact discharge method. V CC must be bypassed to GND via a low impedance ground plane with a 0.22 μF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between the applicable pins and GND. ESD pulses can be positive or negative with respect to GND.

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Application Information

Figure 1. Typical Application Connection Diagram 1 The CM2009-05CP should be placed as close to the VGA or DVI-I connector as possible.

2 The ESD protection channels VIDEO_1, VIDEO_2, VIDEO_3 may be used interchangeably between the R, G, B

4 "VF" are external video filters for the RGB signals. 5 Supply bypass capacitors C1 and C2 must be placed immediately adjacent to the corresponding Vcc pins. 5mm) for best ESD protection. bypass capacitor should be connected between BYP and ground. 7 The SYNC buffers may be used interchangeably between HSYNC and VSYNC. only. The component values and filter configuration may be changed to suit the application. 9 The DDC level shifters DDC_IN, DDC_OUT, may be used interchangeably between DDCA_CLK and DDCA_DATA. pins and VCC_5V via these resistors when VCC_5V is powered down.

The CM2009-05CP is supplied in 14-bump, 5-4-5 Chip Scale Package (CSP). Figure 2. Package Dimensions for

Figure 3. Tape and Reel Mechanical Data Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.