CM2006 ONSEMI | Alldatasheet

Document overview

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  • PDF pages: 9

Technical content

Features

  • Includes ESD protection, level-shifting, buffering and sync impedance matching
  • VESA VSIS Version 1 Revision 2 compatible interface
  • Supports optional NAVI signalling requirements
  • 7 channels of ESD protection for all VGA port connector pins. All pins meet IEC-61000-4-2 Level

4 ESD requirements ( ±8kV contact discharge)

  • Very low loading capacitance from ESD protection diodes on VIDEO lines (3pF maximum)
  • Schmitt-triggered input buffers for HSYNC and VSYNC lines
  • Bidirectional level shifting N-channel FETs provided for DDC_CLK and DDC_DATA channels
  • Backdrive protection on all lines
  • Compact 16-lead QSOP package
  • RoHS-compliant, lead-free finishing

Applications

VGA and DVI-I ports in:

  • Monitors
  • TVs Product Description The CM2006 connects between the VGA or DVI-I port connector and the internal analog or digital flat p anel controller logic. The CM2006 incorporates ESD protection for all signals, level shifting for the DDC signals and buffering for the SYNC signals. ESD protection for the video, DDC and SYNC lines is implemented with low-capacitance current steering diodes. All connector interface pins are designed to safely handle the high current spikes specified by IEC-610 00- 4-2 Level 4 ( ±8kV contact discharge). The ESD protection for the DDC, SYNC and VIDEO signal pins is designed to prevent "backdrive current" when the de vice is powered down while connected to a video source t hat is powered up. Separate positive supply rails are provided for the VIDEO / SYNC signals and DDC signals to facilitate interfacing with low voltage video controller ICs a nd microcontrollers to provide design flexibility in m ulti- supply-voltage environments. Two Schmitt-triggered non-inverting buffers redrive and condition the HSYNC and VSYNC signals from the video connector (SYNC1, SYNC2). These buffers accept VESA VSIS compliant TTL input signals and convert them to CMOS output levels that swing betwe en ground and V CC. Two N-channel MOSFETs provide the level shifting function required when the DDC controller or EDID EEPROM is operated at a lower supply voltage than t he monitor. The gate terminals for these MOSFETS CC_DDC ) should be connected to the supply rail (typically 3.3V, 2.5V etc.) that supplies power to the transce ivers of the DDC controller. The CM1693 is housed in space saving, low profile, 0.40mm pitch uDFN packages in a RoHS compliant, lead-free format.

Rev. 2 | Page 2 of 9 | www.onsemi.com VIDEO_1 VIDEO_2 VIDEO_3 GND SYNC_OUT2 GND VCC_DDC VCC SYNC_OUT1 SYNC_IN2 SYNC_IN1 DDC_IN2 DDC_IN1 RT DDC_OUT2 DDC_OUT1 BYP RT ENABLE 2 Electrical Schematic

Rev.2 | Page 3 of 9 | www.onsemi.com PIN DESCRIPTIONS LEAD(s) NAME DESCRIPTION

1 V CC This is a supply input for the SYNC_1 and SYNC_2 l evel shifters, video protection and the

DDC circuits. 2 ENABLE Active high enable. Disables the Sync buff er outputs when low. 3 VIDEO_1 Video signal ESD protection channel. This pin is typically tied one of the video lines between the controller device and the video connector.

4 VIDEO_2

Video signal ESD protection channel. This pin is typically tied one of the video lines between the controller device and the video connector.

5 VIDEO_3

Video signal ESD protection channel. This pin is typically tied one of the video lines between the controller device and the video connector. 6 GND Ground reference supply pin. 7 V CC_DDC This is an isolated supply input for the DDC_1 and DDC_2 level-shifting N-FET gates. 8 BYP An external 0.22uF bypass capacitor is requir ed on this pin. 9 DDC_IN1 DDC signal input. Connects to the video c onnector side of one of the DDC lines.signal output. 10 DDC_OUT1 DDC signal output. Connects to the moni tor DDC logic. 11 DDC_OUT DDC signal output. Connects to the monit or DDC logic. 12 DDC_IN2 DDC signal input. Connects to the video connector side of one of the DDC lines 13 SYNC_IN1 Sync signal buffer input. Connects to t he video connector side of one of the sync lines. 14 SYNC_OUT1 Sync signal buffer output. Connects to the monitor SYNC logic. 15 SYNC_IN2 Sync signal buffer input. Connects to t he video connector side of one of the sync lines. 16 SYNC_OUT2 Sync signal buffer output. Connects to the monitor SYNC logic.

Ordering Information

PART NUMBERING INFORMATION Pins Package Ordering Part Number Part Marking

16 QSOP CM2006-02QR CM2006-02QR

Note 1: Parts are shipped in Tape and Reel form unless otherwise specified.

Rev. 2 | Page 4 of 9 | www.onsemi.com Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS VCC_DDC and VCC Supply Voltage Inputs [GND - 0.5] to +6.0 V DC Voltage at Inputs VIDEO_1, VIDEO_2, VIDEO_3 DDC_IN1, DDC_IN2 DDC_OUT1, DDC_OUT2 SYNC_IN1, SYNC_IN2, ENABLE [GND - 0.5] to [V CC + 0.5] [GND - 0.5] to 6.0 [GND - 0.5] to 6.0 [GND - 0.5] to [V CC + 0.5] V V V V Operating Temperature Range -40 to +85 ° C Storage Temperature Range -40 to +150 ° C Package Power Rating (T A=25° C) 500 mW STANDARD OPERATING CONDITIONS PARAMETER RATING UNITS Operating Temperature Range -40 to +85 ° C VCC 5 V

Rev.2 | Page 5 of 9 | www.onsemi.com ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ICC_DDC V CC_DDC Supply Current V CC_DDC = 5.0V 10 µ A VCC = 5V; SYNC inputs at GND or V CC ; SYNC outputs unloaded 1 mA ICC V CC Supply Current VCC = 5V; SYNC inputs at 3.0V; SYNC outputs unloaded 2.0 mA VF ESD Diode Forward Voltage I F = 10mA 1.0 V VIH Logic High Input Voltage V CC = 5.0V; Note 2 2.0 V VIL Logic Low Input Voltage V CC = 5.0V; Note 2 0.5 V VHYS Hysteresis Voltage V CC = 5.0V; Note 2 400 mV VOH Logic High Output Voltage I OH = 0mA, V CC = 5.0V; Note 2 4.0 V VOL Logic Low Output Voltage I OL = 0mA, V CC = 5.0V; Note 2 0.15 V ROUT SYNC Driver Output Resistance V CC = 5.0V; SYNC Inputs at GND or 3.0V 7 15 24 Ω Input Current VIDEO Inputs V CC = 5.0V; V IN = V CC or GND ±10 µ A IIN SYNC_IN1, SYNC_IN2 Inputs VCC = 5.0V; V IN = V CC or GND ±10 µ A (V CC_DDC - V DDC_IN ) 0.4V; V DDC_OUT = V CC_DDC 10 µ A IOFF Level Shifting N-MOSFET "OFF" State Leakage Current (V CC_DDC - V DDC_OUT ) 0.4V; V DDC_IN = V CC_DDC 10 µ A IBACKDRIVE Current conducted from input pins when Vcc is powered down. VCC < V INPUT_PIN ; Note 5 10 µ A VON Voltage Drop Across Level-shifting N-MOSFET when "ON" VCC_DDC = 2.5V; V S = GND; I DS = 3mA; 0.18 V VCC = 5.0V; V IN = 2.5V; f = 1MHz 3 pF CIN_VID VIDEO Input Capacitance VCC = 2.5V; V IN = 1.25V; f = 1MHz 3.5 pF tPLH SYNC Driver L => H Propagation Delay CL = 50pF; V CC = 5.0V; Input t R and t F 5ns 12 ns tPHL SYNC Driver H => L Propagation Delay CL = 50pF; V CC = 5.0V; Input t R and t F 5ns 12 ns tR, tF SYNC Driver Output Rise & Fall Times CL = 50pF; V CC = 5.0V; Input t R and t F 5ns 3 ns VESD1 ESD Withstand Voltage, Sync_out pins only V CC = 5V; Notes 3 and 4 ±2 kV VESD ESD Withstand Voltage V CC = 5V; Notes 3 and 5 ±8 kV Note 1: All parameters specified over standard oper ating conditions unless otherwise noted. Note 2: These parameters apply only to the SYNC dri vers. Note that R OUT = R T + R BUFFER . Note 3: Per the IEC-61000-4-2 International ESD Sta ndard, Level 4 contact discharge method. BYP and V CC must be bypassed to GND via a low impedance ground plane with a 0.22 µ F, low inductance, chip ceramic capacitor at each s upply pin. ESD pulse is applied between the applicable pins and GN D. ESD pulses can be positive or negative with resp ect to GND. Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYN C_IN1, SYNC_IN2, DDC_IN1 and DDC_IN2. All pins are ESD protected to the industry standard ±2kV Human Body Model (MIL-STD-883, Method 3015). Note 4: This specification applies to the SYNC_OUT pins only. Note 5: Applicable pins are: VIDEO_1, VIDEO_2, VIDE O_3, SYNC_IN1, SYNC_IN2, DDC_IN1 and DDC_IN2.

Rev. 2 | Page 6 of 9 | www.onsemi.com

Application Information

Figure 1. Typical Application Connection Diagram 1 The CM2006 should be placed as close to the VGA or DVI-I connector as possible. 4 "VF" are external video filters for the RGB sign als. bypass capacitor should be connected between BYP and ground. 7 The SYNC buffers may be used interchangeably bet ween HSYNC and VSYNC. only. The component values and filter configuration may be changed to suit the application. 9 The DDC level shifters DDC_IN, DDC_OUT, may be u sed interchangeably between DDCA_CLK and DDCA_DATA. pins and VCC_5V via these resistors when VCC_5V is powered down.

Rev.2 | Page 7 of 9 | www.onsemi.com Mechanical Details QSOP Mechanical Specifications CM2006 devices are packaged in 16-pin QSOP packages . Dimensions are presented below. PACKAGE DIMENSIONS Package QSOP (JEDEC name is SSOP) Pins 16 Millimeters Inches Dimensions Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 B 0.20 0.30 0.008 0.012 C 0.18 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.81 3.98 0.150 0.157 e 0.64 BSC 0.025 BSC H 5.79 6.19 0.228 0.244 L 0.40 1.27 0.016 0.050 # per tube 100 pcs* # per tape and reel 2500 pcs Controlling dimension: inches * This is an approximate number which may vary. Package Dimensions for QSOP-16

Rev. 2 | Page 8 of 9 | www.onsemi.com Tape and Reel Specifications PART NUMBER PACKAGE SIZE (mm) POCKET SIZE (mm) B0 X A 0 X K 0 TAPE WIDTH W REEL DIAMETER QTY PER REEL P 0 P 1

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