CM2006

CM2006 CALMIRCO | Alldatasheet

Document overview

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Technical content

Features

Includes ESD protection, level-shifting, buffering and sync impedance matching VESA VSIS Version 1 Revision 2 Compatible Inter- face Supports Optional NAVI Signalling requirements 7 channels of ESD protection for all VGA port con- nector pins meeting IEC-61000-4-2 Level 4 ESD requirements (±8kV contact discharge) Very low loading capacitance from ESD protection diodes on VIDEO lines, 3pF maximum Schmitt triggered input buffers for HSYNC and VSYNC lines Bi-directional level shifting N-channel FETs pro- vided for DDC_CLK & DDC_DATA channels Backdrive protection on all lines Compact 16-lead QSOP package

Applications

VGA and DVI-I ports in: - Monitors - Set Top Boxes Product Description The CM2006 connects between the VGA or DVI-I port connector and the internal analog or digital flat panel controller logic. The CM2006 incorporates ESD protec- tion for all signals, level shifting for the DDC signals and buffering for the SYNC signals. ESD protection for the video, DDC and SYNC lines is implemented with low-capacitance current steering diodes. All connector interface pins are designed to safely han- dle the high current spikes specified by IEC-61000-4-2 Level 4 (±8kV contact discharge). The ESD protection for the DDC, SYNC and VIDEO signal pins is designed to prevent "back current" when the device is powered down while connected to a video source that is pow- ered up. Separate positive supply rails are provided for the VIDEO / SYNC signals and DDC signals to facilitate interfacing with low voltage video controller ICs and microcontrollers to provide design flexibility in multi- supply-voltage environments. Two Schmitt-Triggered non-inverting buffers redrive and condition the HSYNC and VSYNC signals from the video Connector (SYNC1, SYNC2). These buffers accept VESA VSIS compliant TTL input signals and convert them to CMOS output levels that swing between Ground and VCC. (cont’d next page) Simplified Electrical Schematic VIDEO_1 VIDEO_2 VIDEO_3 GND SYNC_OUT2 GND VCC_DDC VCC SYNC_OUT1 SYNC_IN2 SYNC_IN1 DDC_IN2 DDC_IN1 RT DDC_OUT2 DDC_OUT1 BYP RT ENABLE

© 2006 California Micro Devices Corp. All rights reserved. 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 02/21/06 CM2006 PRELIMINARY Product Description (cont’d) Two N-channel MOSFETs provide the level shifting function required when the DDC controller or EDID EEPROM is operated at a lower supply voltage than the monitor. The gate terminals for these MOSFETS (VCC_DDC) should be connected to the supply rail (typi- cally 3.3V, 2.5V etc.) that supplies power to the trans- ceivers of the DDC controller. PIN DESCRIPTIONS LEAD(s) NAME

DESCRIPTION

This is a supply input for the SYNC_1 and SYNC_2 level shifters, video protection and the DDC circuits. ENABLE Active high enable. Disables the Sync buffer outputs when low. VIDEO_1 Video signal ESD protection channel. This pin is typically tied one of the video lines between the controller device and the video connector. VIDEO_2 Video signal ESD protection channel. This pin is typically tied one of the video lines between the controller device and the video connector. VIDEO_3 Video signal ESD protection channel. This pin is typically tied one of the video lines between the controller device and the video connector. GND Ground reference supply pin. VCC_DDC This is an isolated supply input for the DDC_1 and DDC_2 level-shifting N-FET gates. BYP An external 0.22uF bypass capacitor is required on this pin. DDC_IN1 DDC signal input. Connects to the video connector side of one of the DDC lines.signal output. DDC_OUT1 DDC signal output. Connects to the monitor DDC logic. DDC_OUT DDC signal output. Connects to the monitor DDC logic. DDC_IN2 DDC signal input. Connects to the video connector side of one of the DDC lines SYNC_IN1 Sync signal buffer input. Connects to the video connector side of one of the sync lines. SYNC_OUT1 Sync signal buffer output. Connects to the monitor SYNC logic. SYNC_IN2 Sync signal buffer input. Connects to the video connector side of one of the sync lines. SYNC_OUT2 Sync signal buffer output. Connects to the monitor SYNC logic. PACKAGE / PINOUT DIAGRAM Note: This drawing is not to scale. Top View

16 Pin QSOP

SYNC_OUT2 SYNC_IN2 SYNC_OUT1 SYNC_IN1 DDC_IN2 DDC_OUT2 DDC_OUT1 VCC ENABLE VIDEO_1 VIDEO_2 VIDEO_3 GND VCC_DDC DDC_IN1 BYP

© 2006 California Micro Devices Corp. All rights reserved. 02/21/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com CM2006 PRELIMINARY

Ordering Information

Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Specifications PART NUMBERING INFORMATION Pins Package Standard Finish Lead-free Finish Ordering Part Number1 Part Marking Ordering Part Number1 Part Marking QSOP CM2006-02QS CM2006-02QS CM2006-02QR CM2006-02QR ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS VCC_DDC and VCC Supply Voltage Inputs [GND - 0.5] to +6.0 V DC Voltage at Inputs VIDEO_1, VIDEO_2, VIDEO_3 DDC_IN1, DDC_IN2 DDC_OUT1, DDC_OUT2 SYNC_IN1, SYNC_IN2, ENABLE [GND - 0.5] to [VCC + 0.5] [GND - 0.5] to 6.0 [GND - 0.5] to 6.0 [GND - 0.5] to [VCC + 0.5] V V V V Operating Temperature Range -40 to +85 Storage Temperature Range -40 to +150 Package Power Rating (TA=25°C) 500 mW STANDARD OPERATING CONDITIONS PARAMETER RATING UNITS Operating Temperature Range -40 to +85 VCC V

© 2006 California Micro Devices Corp. All rights reserved. 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 02/21/06 CM2006 PRELIMINARY Specifications Note 1: All parameters specified over standard operating conditions unless otherwise noted Note 2: These parameters apply only to the SYNC drivers. Note that ROUT = RT + RBUFFER. Note 3: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. BYP and VCC must be bypassed to GND via a low impedance ground plane with a 0.22μF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between the applicable pins and GND. ESD pulses can be positive or negative with respect to GND. Appli- cable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_IN1, SYNC_IN2, DDC_IN1 and DDC_IN2. All pins are ESD pro- tected to the industry standard ±2kV Human Body Model (MIL-STD-883, Method 3015). Note 4: This parameter is guaranteed by design and characterization. Note 5: This specification applies to the SYNC_OUT pins only. Note 6: Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_IN1, SYNC_IN2, DDC_IN1 and DDC_IN2. ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ICC_DDC VCC_DDC Supply Current VCC_DDC = 5.0V μA ICC VCC Supply Current VCC = 5V; SYNC inputs at GND or VCC; SYNC outputs unloaded mA VCC = 5V; SYNC inputs at 3.0V; SYNC outputs unloaded 2.0 mA VF ESD Diode Forward Voltage IF = 10mA 1.0 V VIH Logic High Input Voltage VCC = 5.0V; Note 2 2.0 V VIL Logic Low Input Voltage VCC = 5.0V; Note 2 0.5 V VHYS Hysteresis Voltage VCC = 5.0V; Note 2 400 mV VOH Logic High Output Voltage IOH = 0mA, VCC = 5.0V; Note 2 4.0 V VOL Logic Low Output Voltage IOL = 0mA, VCC = 5.0V; Note 2 0.15 V ROUT SYNC Driver Output Resistance VCC = 5.0V; SYNC Inputs at GND or 3.0V Ω IIN Input Current VIDEO Inputs VCC = 5.0V; VIN = VCC or GND ±10 μA SYNC_IN1, SYNC_IN2 Inputs VCC = 5.0V; VIN = VCC or GND ±10 μA IOFF Level Shifting N-MOSFET "OFF" State Leakage Current (VCC_DDC - VDDC_IN) < 0.4V; VDDC_OUT = VCC_DDC μA (VCC_DDC - VDDC_OUT) < 0.4V; VDDC_IN = VCC_DDC μA IBACKDRIVE Current conducted from input pins when Vcc is powered down. VCC < VINPUT_PIN ; Note 6 μA VON Voltage Drop Across Level-shifting N-MOSFET when "ON" VCC_DDC = 2.5V; VS = GND; IDS = 3mA; 0.18 V CIN_VID VIDEO Input Capacitance VCC = 5.0V; VIN = 2.5V; f = 1MHz; Note 4 pF VCC = 2.5V; VIN = 1.25V; f = 1MHz; Note 4 3.5 pF tPLH SYNC Driver L => H Propagation Delay CL = 50pF; VCC = 5.0V; Input tR and tF < 5ns ns tPHL SYNC Driver H => L Propagation Delay CL = 50pF; VCC = 5.0V; Input tR and tF < 5ns ns tR, tF SYNC Driver Output Rise & Fall Times CL = 50pF; VCC = 5.0V; Input tR and tF < 5ns ns VESD1 ESD Withstand Voltage, Sync_out pins only VCC = 5V; Notes 3, 4, & 5 ± 2 kV VESD ESD Withstand Voltage VCC = 5V; Notes 3, 4, & 6 ± 8 kV

© 2006 California Micro Devices Corp. All rights reserved. 02/21/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com CM2006 PRELIMINARY

Application Information

Figure 1. Typical Application Connection Diagram The CM2006 should be placed as close to the VGA or DVI-I connector as possible. The ESD protection channels VIDEO_1, VIDEO_2, VIDEO_3 may be used interchangeably between the R, G, B signals. "VF" are external video filters for the RGB signals. capacitor should be connected between BYP and ground. The SYNC buffers may be used interchangeably between HSYNC and VSYNC. The EMI filters at the SYNC_OUT and DDC_OUT pins (C5 to C12, and Ferrite Beads FB1 to FB4) are for reference only. The component values and filter configuration may be changed to suit the application. The DDC level shifters DDC_IN, DDC_OUT, may be used interchangeably between DDCA_CLK and DDCA_DATA. VCC_5V via these resistors when VCC_5V is powered down.

© 2006 California Micro Devices Corp. All rights reserved. 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 Tel: 408.263.3214 Fax: 408.263.7846 www.cmd.com 02/21/06 CM2006 PRELIMINARY Mechanical Details QSOP Mechanical Specifications CM2006 devices are packaged in 16-pin QSOP pack- ages. Dimensions are presented below. For complete information on the QSOP-16 package, see the California Micro Devices QSOP Package Infor- mation document. * This is an approximate number which may vary. Package Dimensions for QSOP-16 PACKAGE DIMENSIONS Package QSOP (JEDEC name is SSOP) Pins Dimensions Millimeters Inches Min Max Min Max A 1.35 1.75 0.053 0.069 0.10 0.25 0.004 0.010 B 0.20 0.30 0.008 0.012 C 0.18 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.81 3.98 0.150 0.157 e

0.64 BSC

0.025 BSC

H 5.79 6.19 0.228 0.244 L 0.40 1.27 0.016 0.050 # per tube 100 pcs* # per tape and reel 2500 pcs Controlling dimension: inches Mechanical Package Diagrams E D H TOP VIEW L END VIEW C e B A SEATING PLANE SIDE VIEW Pin 1 Marking