CM066B

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/C0067/C0068/C0052/C0048/C0054/C0054/C0066 /C0067/C0077/C0079/C0083 /C0081/C0085/C0065/C0068 /C0066/C0073/C0076/C0065/C0084/C0069/C0082/C0065/C0076 /C0083/C0087/C0073/C0084/C0067/C0072 SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C006815-V Digital or ±7.5-V Peak-to-Peak Switching /C0068125-Ω Typical On-State Resistance for 15-V Operation /C0068Switch On-State Resistance Matched to Within 5 Ω Over 15-V Signal-Input Range /C0068On-State Resistance Flat Over Full Peak-to-Peak Signal Range /C0068High On/Off Output-Voltage Ratio: 80 dB Typical at f is = 10 kHz, RL = 1 kΩ /C0068High Degree of Linearity: <0.5% Distortion Typical at fis = 1 kHz, Vis = 5 V p-p, VDD − VSS ≥ 10 V, RL = 10 kΩ /C0068Extremely Low Off-State Switch Leakage, Resulting in Very Low Offset Current and High Effective Off-State Resistance: 10 pA Typical at V DD − VSS = 10 V, TA = 25°C /C0068Extremely High Control Input Impedance (Control Circuit Isolated From Signal Circuit): 10 12 Ω Typical /C0068Low Crosstalk Between Switches: −50 dB Typical at fis = 8 MHz, RL = 1 kΩ /C0068Matched Control-Input to Signal-Output Capacitance: Reduces Output Signal Transients /C0068Frequency Response, Switch On = 40 MHz Typical /C0068100% Tested for Quiescent Current at 20 V /C00685-V, 10-V, and 15-V Parametric Ratings /C0068Meets All Requirements of JEDEC Tentative Standard No. 13-B, Standard Specifications for Description of “B” Series CMOS Devices /C0068Applications: − Analog Signal Switching/Multiplexing: Signal Gating, Modulator, Squelch Control, Demodulator, Chopper, Commutating Switch − Digital Signal Switching/Multiplexing − Transmission-Gate Logic Implementation − Analog-to-Digital and Digital-to-Analog Conversion − Digital Control of Frequency, Impedance, Phase, and Analog-Signal Gain description/ordering information The CD4066B is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition, the on-state resistance is relatively constant over the full signal-input range. The CD4066B consists of four bilateral switches, each with independent controls. Both the p and the n devices in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well of the n-channel device on each switch is tied to either the input (when the switch is on) or to V SS (when the switch is off). This configuration eliminates the variation of the switch-transistor threshold voltage with input signal and, thus, keeps the on-state resistance low over the full operating-signal range. The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold applications, the CD4016B is recommended. Copyright  2003, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SIG A IN/OUT SIG A OUT/IN SIG B OUT/IN SIG B IN/OUT CONTROL B CONTROL C V SS VDD CONTROL A CONTROL D SIG D IN/OUT SIG D OUT/IN SIG C OUT/IN SIG C IN/OUT E, F, M, NS, OR PW PACKAGE (TOP VIEW)

/C0067/C0068/C0052/C0048/C0054/C0054/C0066 /C0067/C0077/C0079/C0083 /C0081/C0085/C0065/C0068 /C0066/C0073/C0076/C0065/C0084/C0069/C0082/C0065/C0076 /C0083/C0087/C0073/C0084/C0067/C0072 SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

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description/ordering information (continued)

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING CDIP − F Tube of 25 CD4066BF3A CD4066BF3A PDIP − E Tube of 25 CD4066BE CD4066BE Tube of 50 CD4066BM −55°C to 125°C SOIC − M Reel of 2500 CD4066BM96 CD4066BM−55°C to 125°C SOIC − M Reel of 250 CD4066BMT CD4066BM SOP − NS Reel of 2000 CD4066BNSR CD4066B TSSOP − PW Tube of 90 CD4066BPW CM066BTSSOP − PW Reel of 2000 CD4066BPWR CM066B † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. † All control inputs are protected by the CMOS protection network. NOTES: A. All p substrates are connected to VDD . B. Normal operation control-line biasing: switch on (logic 1), VC = VDD ; switch off (logic 0), VC = VSS C. Signal-level range: VSS ≤ Vis ≤ VDD Control VC † VDD VSS VSS n n p Out Vos Control Switch In 92CS-29113 np Vis Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry

/C0067/C0068/C0052/C0048/C0054/C0054/C0066 /C0067/C0077/C0079/C0083 /C0081/C0085/C0065/C0068 /C0066/C0073/C0076/C0065/C0084/C0069/C0082/C0065/C0076 /C0083/C0087/C0073/C0084/C0067/C0072 SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Lead temperature (during soldering): † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions MIN MAX UNIT VDD Supply voltage 3 18 V TA Operating free-air temperature −55 125 °C

/C0067/C0068/C0052/C0048/C0054/C0054/C0066 /C0067/C0077/C0079/C0083 /C0081/C0085/C0065/C0068 /C0066/C0073/C0076/C0065/C0084/C0069/C0082/C0065/C0076 /C0083/C0087/C0073/C0084/C0067/C0072 SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

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electrical characteristics

LIMITS AT INDICATED TEMPERATURES PARAMETER TEST CONDITIONS VIN VDD −55°C −40°C 85°C 125°C 25°C UNITPARAMETER TEST CONDITIONS VIN (V) VDD (V) −55°C −40°C 85°C 125°C TYP MAX UNIT IDD Quiescent device 0, 10 10 0.5 0.5 15 15 0.01 0.5 AIDD Quiescent device current 0, 15 15 1 1 30 30 0.01 1 µAcurrent 0, 20 20 5 5 150 150 0.02 5 Signal Inputs (Vis) and Outputs (Vos) VC = VDD , R L = 10 kΩ returned 5 800 850 1200 1300 470 1050 ron On-state resistance (max) R L = 10 kΩ returned to , /C0466V DD /C0042V SS /C0467 10 310 330 500 550 180 400 Ωon (max) to , Vis = VSS to VDD 15 200 210 300 320 125 240 On-state resistance 5 15 ∆ron On-state resistance difference between any two switches R L = 10 kΩ, VC = VDD 10 10 Ω∆ron difference between any two switches R L = 10 kΩ, VC = VDD 15 5 Ω THD Total harmonic distortion VC = VDD = 5 V, VSS = −5 V, Vis(p-p) = 5 V (sine wave centered on 0 V), R L = 10 kΩ, fis = 1-kHz sine wave 0.4 % −3-dB cutoff frequency (switch on) VC = VDD = 5 V, VSS = −5 V, Vis(p-p) = 5 V (sine wave centered on 0 V), RL = 1 kΩ 40 MHz −50-dB feedthrough frequency (switch off) VC = VSS = −5 V, Vis(p-p) = 5 V (sine wave centered on 0 V), RL = 1 kΩ 1 MHz Iis Input/output leakage current (switch off) (max) VC = 0 V, Vis = 18 V, Vos = 0 V; and VC = 0 V, Vis = 0 V, Vos = 18 V −50-dB crosstalk frequency VC (A) = VDD = 5 V, VC (B) = VSS = −5 V, Vis(A) = 5 Vp-p, 50-Ω source, R L = 1 kΩ

8 MHz

R L = 200 kΩ, VC = VDD , VSS = GND, CL = 50 pF, 5 20 40 tpd Propagation delay (signal input to signal output) VSS = GND, CL = 50 pF, Vis = 10 V (square wave centered on 5 V), 10 10 20 nspd (signal input to signal output) is (square wave centered on 5 V), tr, tf = 20 ns 15 7 15 C is Input capacitance VDD = 5 V, VC = VSS = −5 V 8 pF C os Output capacitance VDD = 5 V, VC = VSS = −5 V 8 pF C ios Feedthrough VDD = 5 V, VC = VSS = −5 V 0.5 pF

/C0067/C0068/C0052/C0048/C0054/C0054/C0066 /C0067/C0077/C0079/C0083 /C0081/C0085/C0065/C0068 /C0066/C0073/C0076/C0065/C0084/C0069/C0082/C0065/C0076 /C0083/C0087/C0073/C0084/C0067/C0072 SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics (continued) LIMITS AT INDICATED TEMPERATURES CHARACTERISTIC TEST CONDITIONS VDD −55°C −40°C 85°C 125°C 25°C UNITCHARACTERISTIC TEST CONDITIONS VDD (V) −55°C −40°C 85°C 125°C TYP MAX UNIT Control (VC ) Control input, |Iis| < 10 µA, 5 1 1 1 1 1 VILC Control input, low voltage (max) |Iis| < 10 µA, Vis = VSS , VOS = VDD , and V = V , V = V 10 2 2 2 2 2 VVILC low voltage (max) Vis = VSS , VOS = VDD , and Vis = VDD , VOS = VSS 15 2 2 2 2 2 V Control input, 5 3.5 (MIN) VIHC Control input, high voltage See Figure 6 10 7 (MIN) VVIHC high voltage See Figure 6 15 11 (MIN) V IIN Input current (max) Vis ≤ VDD , VDD − VSS = 18 V, VCC ≤ VDD − VSS Crosstalk (control input to signal output) VC = 10 V (square wave), tr, tf = 20 ns, RL = 10 kΩ 10 50 mV Turn-on and turn-offVIN = VDD , tr, tf = 20 ns, 5 35 70 Turn-on and turn-off propagation delay VIN = VDD , tr, tf = 20 ns, C L = 50 pF, RL = 1 kΩ 10 20 40 nspropagation delay C L = 50 pF, RL = 1 kΩ 15 15 30 ns Vis = VDD , VSS = GND, R L = 1 kΩ to GND, CL = 50 pF, 5 6 Maximum control input repetition rate R L = 1 kΩ to GND, CL = 50 pF, VC = 10 V (square wave centered on 5 V), tr, tf = 20 ns, 10 9 MHzrepetition rate C centered on 5 V), tr, tf = 20 ns, Vos = 1/2 Vos at 1 kHz 15 9.5 C I Input capacitance 5 7.5 pF switching characteristics VDD SWITCH INPUT SWITCH OUTPUT, V osVDD (V) Vis (V) Iis (mA) OUTPUT, V os (V)(V) Vis (V) −55°C −40°C 25°C 85°C 125°C MIN MAX

/C0067/C0068/C0052/C0048/C0054/C0054/C0066 /C0067/C0077/C0079/C0083 /C0081/C0085/C0065/C0068 /C0066/C0073/C0076/C0065/C0084/C0069/C0082/C0065/C0076 /C0083/C0087/C0073/C0084/C0067/C0072 SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

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Vis − Input Signal Voltage − V 600 500 400 300 200 100 −4 −3 −2 −1 0 1 2 3 4 TYPICAL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) 92CS-27326RI Figure 2 TA = 125°C +25°C −55°C Supply Voltage (VDD − VSS ) = 5 V − Channel On-State Resistance − on Ωr Figure 3 TYPICAL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) 300 250 200 150 100 Supply Voltage (VDD − VSS ) = 10 V TA = 125°C Vis − Input Signal Voltage − V +25°C −55°C 92CS-27327RI − Channel On-State Resistance − on Ωr Vis − Input Signal Voltage − V TYPICAL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) Figure 4 300 250 200 150 100 Supply Voltage (VDD − VSS ) = 15 V TA = 125°C +25°C −55°C 92CS-27329RI − Channel On-State Resistance − on Ωr Vis − Input Signal Voltage − V Figure 5 TYPICAL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) 600 500 400 300 200 100 Supply Voltage (VDD − VSS ) = 5 V TA = 125°C 10 V −15 V 92CS-27330RI − Channel On-State Resistance − on Ωr

Figure 6. Determination of ron as a Test Condition for Control-Input High-Voltage (VIHC) Specification

160 Digital

Figure 7. Channel On-State Resistance Measurement Circuit

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test-fixture capacitance nulled out. Figure 10. Typical On Characteristics Figure 11. Off-Switch Input or Output Leakage All unused terminals are connected to VSS . Figure 12. Propagation Delay Time Signal Input All unused terminals are connected to VSS . Figure 13. Crosstalk-Control Input All unused terminals are connected to VSS .

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Measure inputs sequentially to both VDD and VSS . Connect all unused inputs to either VDD or VSS . Measure control inputs only. Figure 16. Input Leakage-Current Test Circuit Figure 17. Four-Channel PAM Multiplex System Diagram

5 V CD4066B

Figure 18. Bidirectional Signal Transmission Via Digital Control Logic

/C0067/C0068/C0052/C0048/C0054/C0054/C0066 /C0067/C0077/C0079/C0083 /C0081/C0085/C0065/C0068 /C0066/C0073/C0076/C0065/C0084/C0069/C0082/C0065/C0076 /C0083/C0087/C0073/C0084/C0067/C0072 SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

In applications that employ separate power sources to drive VDD and the signal inputs, the VDD current capability should exceed VDD /RL (RL = effective external load of the four CD4066B bilateral switches). This provision avoids any permanent current flow or clamp action on the VDD supply when power is applied or removed from the CD4066B. In certain applications, the external load-resistor current can include both VDD and signal-line components. To avoid drawing VDD current when switch current flows into terminals 1, 4, 8, or 11, the voltage drop across the bidirectional switch must not exceed 0.8 V (calculated from ron values shown). No VDD current will flow through RL if the switch current flows into terminals 2, 3, 9, or 10.

www.ti.com 18-Oct-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CD4066BE ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD4066BE CD4066BEE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD4066BE CD4066BF ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD4066BF CD4066BF3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD4066BF3A CD4066BF3AS2283 OBSOLETE CDIP J 14 TBD Call TI Call TI CD4066BF3AS2534 OBSOLETE CDIP J 14 TBD Call TI Call TI CD4066BM ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM CD4066BM96 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 CD4066BM CD4066BM96E4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM CD4066BM96G4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM CD4066BME4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM CD4066BMG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM CD4066BMT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM CD4066BMTE4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM CD4066BMTG4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM CD4066BNSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066B CD4066BNSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066B CD4066BNSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066B

www.ti.com 18-Oct-2013 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CD4066BPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM066B CD4066BPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM066B CD4066BPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM066B CD4066BPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM066B CD4066BPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM066B CD4066BPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM066B JM38510/05852BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 05852BCA M38510/05852BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 05852BCA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

www.ti.com 18-Oct-2013 Addendum-Page 3 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD4066B, CD4066B-MIL :

• Catalog: CD4066B
• Automotive: CD4066B-Q1 , CD4066B-Q1
• Military: CD4066B-MIL NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Military - QML certified for Military and Defense Applications

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 7-Dec-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD4066BM96 SOIC D 14 2500 367.0 367.0 38.0 CD4066BM96 SOIC D 14 2500 333.2 345.9 28.6 CD4066BM96G4 SOIC D 14 2500 367.0 367.0 38.0 CD4066BM96G4 SOIC D 14 2500 333.2 345.9 28.6 CD4066BMT SOIC D 14 250 367.0 367.0 38.0 CD4066BNSR SO NS 14 2000 367.0 367.0 38.0 CD4066BPWR TSSOP PW 14 2000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 7-Dec-2013 Pack Materials-Page 2

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