SN74LVTH16373-EP TI1 | Alldatasheet
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/C0083/C0078/C0055/C0052/C0076/C0086/C0084/C0072/C0049/C0054/C0051/C0055/C0051/C0262/C0069/C0080 /C0051/C0046/C0051/C0262/C0086 /C0065/C0066/C0084 /C0049/C0054/C0262/C0066/C0073/C0084 /C0084/C0082/C0065/C0078/C0083/C0080/C0065/C0082/C0069/C0078/C0084 /C0068/C0262/C0084/C0089/C0080/C0069 /C0076/C0065/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Controlled Baseline − One Assembly/Test Site, One Fabrication Site /C0068Enhanced Diminishing Manufacturing Sources (DMS) Support /C0068Enhanced Product-Change Notification /C0068Qualification Pedigree† /C0068Member of the Texas Instruments Widebus Family /C0068State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation /C0068Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V CC ) /C0068Supports Unregulated Battery Operation Down to 2.7 V /C0068Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C /C0068Ioff and Power-Up 3-State Support Hot Insertion /C0068Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors /C0068Distributed VCC and GND Pins Minimize High-Speed Switching Noise † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. /C0068Flow-Through Architecture Optimizes PCB Layout /C0068Latch-Up Performance Exceeds 500 mA Per JESD 17 /C0068ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) description/ordering information The SN74LVTH16373 is a 16-bit transparent D-type latch with 3-state outputs designed for low-voltage (3.3-V) V CC operation, but with the capability to provide a TTL interface to a 5-V system environment. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. Copyright 2004, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Widebus is a trademark of Texas Instruments. DGG OR DL PACKAGE (TOP VIEW) 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 V CC 2Q5 2Q6 GND 2Q7 2Q8 2OE 1LE 1D1 1D2 GND 1D3 1D4 V CC 1D5 1D6 GND 1D7 1D8 2D1 2D2 GND 2D3 2D4 V CC 2D5 2D6 GND 2D7 2D8 2LE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
/C0083/C0078/C0055/C0052/C0076/C0086/C0084/C0072/C0049/C0054/C0051/C0055/C0051/C0262/C0069/C0080 /C0051/C0046/C0051/C0262/C0086 /C0065/C0066/C0084 /C0049/C0054/C0262/C0066/C0073/C0084 /C0084/C0082/C0065/C0078/C0083/C0080/C0065/C0082/C0069/C0078/C0084 /C0068/C0262/C0084/C0089/C0080/C0069 /C0076/C0065/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued) A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When V CC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. terminal assignments 123456 A 1OE NC NC NC NC 1LE B 1Q2 1Q1 GND GND 1D1 1D2 C 1Q4 1Q3 VCC VCC 1D3 1D4 D 1Q6 1Q5 GND GND 1D5 1D6 E 1Q8 1Q7 1D7 1D8 F 2Q1 2Q2 2D2 2D1 G 2Q3 2Q4 GND GND 2D4 2D3 H 2Q5 2Q6 VCC VCC 2D6 2D5 J 2Q7 2Q8 GND GND 2D8 2D7 K 2OE NC NC NC NC 2LE NC − No internal connection
ORDERING INFORMATION
TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING SSOP − DL Tape and reel CLVTH16373IDLREP LH16373EP TSSOP − DGG Tape and reel CLVTH16373IDGGREP LH16373EP −40°C to 85°C VFBGA − GQL CLVTH16373IGQLREP−40 C to 85C VFBGA − ZQL (Pb-free) Tape and reel CLVTH16373IZQLREP LL373EP † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. GQL OR ZQL PACKAGE (TOP VIEW) A B C D E F G H J K 123456
/C0083/C0078/C0055/C0052/C0076/C0086/C0084/C0072/C0049/C0054/C0051/C0055/C0051/C0262/C0069/C0080 /C0051/C0046/C0051/C0262/C0086 /C0065/C0066/C0084 /C0049/C0054/C0262/C0066/C0073/C0084 /C0084/C0082/C0065/C0078/C0083/C0080/C0065/C0082/C0069/C0078/C0084 /C0068/C0262/C0084/C0089/C0080/C0069 /C0076/C0065/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FUNCTION TABLE (each 8-bit section) INPUTS OUTPUT OE LE D OUTPUT Q L H H H L HL L L LX Q 0 H X X Z logic diagram (positive logic) 1OE 1LE 1D1 To Seven Other Channels 1Q1 2OE 2LE 2D1 2Q1 To Seven Other Channels 132C1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Voltage range applied to any output in the high-impedance † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC . 3. The package thermal impedance is calculated in accordance with JESD 51-7.
/C0083/C0078/C0055/C0052/C0076/C0086/C0084/C0072/C0049/C0054/C0051/C0055/C0051/C0262/C0069/C0080 /C0051/C0046/C0051/C0262/C0086 /C0065/C0066/C0084 /C0049/C0054/C0262/C0066/C0073/C0084 /C0084/C0082/C0065/C0078/C0083/C0080/C0065/C0082/C0069/C0078/C0084 /C0068/C0262/C0084/C0089/C0080/C0069 /C0076/C0065/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4) MIN MAX UNIT VCC Supply voltage 2.7 3.6 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V VI Input voltage 5.5 V IOH High-level output current −32 mA IOL Low-level output current 64 mA ∆t/∆v Input transition rise or fall rateOutputs enabled 10 ns/V ∆t/∆VCC Power-up ramp rate 200 µs/V TA Operating free-air temperature −40 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
/C0083/C0078/C0055/C0052/C0076/C0086/C0084/C0072/C0049/C0054/C0051/C0055/C0051/C0262/C0069/C0080 /C0051/C0046/C0051/C0262/C0086 /C0065/C0066/C0084 /C0049/C0054/C0262/C0066/C0073/C0084 /C0084/C0082/C0065/C0078/C0083/C0080/C0065/C0082/C0069/C0078/C0084 /C0068/C0262/C0084/C0089/C0080/C0069 /C0076/C0065/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIK VCC = 2.7 V, II = −18 mA −1.2 V VCC = 2.7 V to 3.6 V, IOH = −100 µA VCC −0.2 VOH VCC = 2.7 V, IOH = −8 mA 2.4 VVOH VCC = 3 V, IOH = −32 mA 2 V VCC = 2.7 V IOL = 100 µA 0.2 VCC = 2.7 V IOL = 24 mA 0.5 VOL IOL = 16 mA 0.4 VVOL VCC = 3 V IOL = 32 mA 0.5 V VCC = 3 V IOL = 64 mA 0.55 VCC = 0 or 3.6 V, VI = 5.5 V 10 II Control inputs VCC = 3.6 V, VI = VCC or GND ±1 µAII Data inputs VCC = 3.6 V VI = VCC 1 µA Data inputs VCC = 3.6 V VI = 0 −5 Ioff VCC = 0, VI or VO = 0 to 4.5 V ±100 µA VCC = 3 V VI = 0.8 V 75 II(hold) Data inputs VCC = 3 V VI = 2 V −75 µAII(hold) Data inputs VCC = 3.6 V‡, VI = 0 to 3.6 V ±500 µA IOZH VCC = 3.6 V, VO = 3 V 5 µA IOZL VCC = 3.6 V, VO = 0.5 V −5 µA IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don’t care ±100 µA IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don’t care ±100 µA Outputs high 0.19 ICC VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs low 5 mAICC VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs disabled 0.19 mA ∆ICC § VCC = 3 V to 3.6 V, One input at VCC − 0.6 V, Other inputs at VCC or GND 0.2 mA C i VI = 3 V or 0 3 pF C o VO = 3 V or 0 9 pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. § This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 3.3 V ± 0.3 V VCC = 2.7 V UNIT MIN MAX MIN MAX UNIT tw Pulse duration, LE high 3 3 ns tsu Setup time, data before LE↓ 1 0.6 ns th Hold time, data after LE↓ 1 1.1 ns
/C0083/C0078/C0055/C0052/C0076/C0086/C0084/C0072/C0049/C0054/C0051/C0055/C0051/C0262/C0069/C0080 /C0051/C0046/C0051/C0262/C0086 /C0065/C0066/C0084 /C0049/C0054/C0262/C0066/C0073/C0084 /C0084/C0082/C0065/C0078/C0083/C0080/C0065/C0082/C0069/C0078/C0084 /C0068/C0262/C0084/C0089/C0080/C0069 /C0076/C0065/C0084/C0067/C0072 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V VCC = 2.7 V UNITPARAMETER (INPUT) (OUTPUT) MIN TYP † MAX MIN MAX UNIT tPLH D Q 1.5 2.7 3.8 4.2 nstPHL D Q 1.5 2.5 3.6 4 ns tPLH LE Q 2.1 3 4.3 4.8 nstPHL LE Q 2.1 2.9 4 4 ns tPZH OE Q 1.5 2.8 4.3 5.1 nstPZL OE Q 1.5 2.8 4.3 4.7 ns tPHZ OE Q 2.4 3.5 5 5.4 ns tPLZ OE Q 2 3.2 4.7 4.8 ns tsk(o) 0.5 ns † All typical values are at VCC = 3.3 V, TA = 25°C.
NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CLVTH16373IDGGREP ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CLVTH16373IDLREP ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CLVTH16373IZQLREP ACTIVE BGA MI CROSTA R JUNI OR ZQL 56 1000 Pb-Free (RoHS) SNAGCU Level-1-260C-UNLIM V62/04712-01XE ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04712-01YE ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04712-01ZA ACTIVE BGA MI CROSTA R JUNI OR GQL 56 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVTH16373-EP :
- Catalog:SN74LVTH16373
- Military:SN54LVTH16373 NOTE: Qualified Version Definitions: PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 Addendum-Page 1
- Catalog - TI's standard catalog product
- Military - QML certified for Military and Defense Applications PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 Addendum-Page 2
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant CLVTH16373IZQLREP BGA MI CROSTA R JUNI OR PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CLVTH16373IDGGREP TSSOP DGG 48 2000 367.0 367.0 45.0 CLVTH16373IDLREP SSOP DL 48 1000 367.0 367.0 55.0 CLVTH16373IZQLREP BGA MICROSTAR JUNIOR ZQL 56 1000 333.2 345.9 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2
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