SN74LVTH162240-EP TI1 | Alldatasheet

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/C0083/C0078/C0055/C0052/C0076/C0086/C0084/C0072/C0049/C0054/C0050/C0050/C0052/C0048/C0262/C0069/C0080 /C0051/C0046/C0051/C0262/C0086 /C0065/C0066/C0084 /C0049/C0054/C0262/C0066/C0073/C0084 /C0066/C0085/C0070/C0070/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCBS780 − NOVEMBER 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Controlled Baseline − One Assembly/Test Site, One Fabrication Site /C0068Enhanced Diminishing Manufacturing Sources (DMS) Support /C0068Enhanced Product-Change Notification /C0068Qualification Pedigree† /C0068Member of the Texas Instruments Widebus  Family /C0068State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation /C0068Output Ports Have Equivalent 22-Ω Series Resistors, So No External Resistors Are Required /C0068Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V CC ) /C0068Supports Unregulated Battery Operation Down To 2.7 V /C0068Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C /C0068Ioff and Power-Up 3-State Support Hot Insertion /C0068Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors /C0068Distributed VCC and GND Pins Minimize High-Speed Switching Noise † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. /C0068Flow-Through Architecture Optimizes PCB Layout /C0068Latch-Up Performance Exceeds 250 mA Per JESD 17 /C0068ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) description/ordering information The SN74LVTH162240 is a 16-bit buffer/driver designed specifically for low-voltage (3.3-V) VCC operation and to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. It has the capability to provide a TTL interface to a 5-V system environment. This device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer and provide inverting outputs and symmetrical active-low output-enable (OE ) inputs. Copyright  2003, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. 1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 V CC 4Y1 4Y2 GND 4Y3 4Y4 4OE 2OE 1A1 1A2 GND 1A3 1A4 V CC 2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 V CC 4A1 4A2 GND 4A3 4A4 3OE DGG PACKAGE (TOP VIEW)

/C0083/C0078/C0055/C0052/C0076/C0086/C0084/C0072/C0049/C0054/C0050/C0050/C0052/C0048/C0262/C0069/C0080 /C0051/C0046/C0051/C0262/C0086 /C0065/C0066/C0084 /C0049/C0054/C0262/C0066/C0073/C0084 /C0066/C0085/C0070/C0070/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCBS780 − NOVEMBER 2003

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description/ordering information (continued) The outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ω series resistors to reduce overshoot and undershoot. When V CC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. This device is fully specified for hot-insertion applications using I off and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING −40°C to 85°C TSSOP − DGG Tape and reel CLVTH162240IDGGREP LH162240EP † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each 4-bit buffer) INPUTS OUTPUT OE A OUTPUT Y L H L L LH H X Z

/C0083/C0078/C0055/C0052/C0076/C0086/C0084/C0072/C0049/C0054/C0050/C0050/C0052/C0048/C0262/C0069/C0080 /C0051/C0046/C0051/C0262/C0086 /C0065/C0066/C0084 /C0049/C0054/C0262/C0066/C0073/C0084 /C0066/C0085/C0070/C0070/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCBS780 − NOVEMBER 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 1Y1 1Y2 1Y3 1Y4 2OE 2A1 2A2 2A3 2A4 2Y1 2Y2 2Y3 2Y4 3OE 3A1 3A2 3A3 3A4 3Y1 3Y2 3Y3 3Y4 4OE 4A1 4A2 4A3 4A4 4Y1 4Y2 4Y3 4Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Voltage range applied to any output in the high-impedance † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC . 3. The package thermal impedance is calculated in accordance with JESD 51.

/C0083/C0078/C0055/C0052/C0076/C0086/C0084/C0072/C0049/C0054/C0050/C0050/C0052/C0048/C0262/C0069/C0080 /C0051/C0046/C0051/C0262/C0086 /C0065/C0066/C0084 /C0049/C0054/C0262/C0066/C0073/C0084 /C0066/C0085/C0070/C0070/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCBS780 − NOVEMBER 2003

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recommended operating conditions (see Note 4) MIN MAX UNIT VCC Supply voltage 2.7 3.6 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V VI Input voltage 5.5 V IOH High-level output current −12 mA IOL Low-level output current 12 mA ∆t/∆v Input transition rise or fall rate Outputs enabled 10 ns/V ∆t/∆VCC Power-up ramp rate 200 µs/V TA Operating free-air temperature −40 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIK VCC = 2.7 V, II = −18 mA −1.2 V VOH VCC = 3 V, IOH = −12 mA 2 V VOL VCC = 3 V, IOL = 12 mA 0.8 V VCC = 0 or 3.6 V, VI = 5.5 V 10 II Control inputsVCC = 3.6 V, VI = VCC or GND ±1 AII Data inputs VCC = 3.6 V VI = VCC 1 µA Data inputs VCC = 3.6 V VI = 0 −5 Ioff VCC = 0, VI or VO = 0 to 4.5 V ±100 µA VCC = 3 V VI = 0.8 V 75 II(hold) Data inputs VCC = 3 V VI = 2 V −75 µAII(hold) Data inputs VCC = 3.6 V‡, VI = 0 to 3.6 V 500 −750 µA IOZH VCC = 3.6 V, VO = 3 V 5 µA IOZL VCC = 3.6 V, VO = 0.5 V −5 µA IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don’t care ±100 µA IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don’t care ±100 µA Outputs high 0.19 ICC VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs low 5 mAICC VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs disabled 0.19 mA ∆ICC § VCC = 3 V to 3.6 V, One input at VCC − 0.6 V, Other inputs at VCC or GND 0.2 mA C i VI = 3 V or 0 4 pF C o VO = 3 V or 0 9 pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. § This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.

/C0083/C0078/C0055/C0052/C0076/C0086/C0084/C0072/C0049/C0054/C0050/C0050/C0052/C0048/C0262/C0069/C0080 /C0051/C0046/C0051/C0262/C0086 /C0065/C0066/C0084 /C0049/C0054/C0262/C0066/C0073/C0084 /C0066/C0085/C0070/C0070/C0069/C0082/C0047/C0068/C0082/C0073/C0086/C0069/C0082 /C0087/C0073/C0084/C0072 /C0051/C0262/C0083/C0084/C0065/C0084/C0069 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCBS780 − NOVEMBER 2003 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V VCC = 2.7 V UNITPARAMETER (INPUT) (OUTPUT) MIN TYP † MAX MIN MAX UNIT tPLH A Y 1 2.5 4 4.6 nstPHL A Y 1 2.9 4 4.6 ns tPZH OE Y 1 2.8 4.8 5.7 nstPZL OE Y 1 2.8 4.7 4.9 ns tPHZ OE Y 2 3.5 4.7 5.2 nstPLZ OE Y 2 3.4 4.5 4.5 ns tsk(o) 0.5 0.5 ns † All typical values are at VCC = 3.3 V, TA = 25°C.

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CLVTH162240IDGGREP ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04707-01XE ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVTH162240-EP :

  • Catalog:SN74LVTH162240 NOTE: Qualified Version Definitions:
  • Catalog - TI's standard catalog product PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 5-Aug-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CLVTH162240IDGGREP TSSOP DGG 48 2000 346.0 346.0 41.0 PACKAGE MATERIALS INFORMATION www.ti.com 5-Aug-2008 Pack Materials-Page 2

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