Logic IC

CLV8T164QWBQARQ1

Texas Instruments

SN74LV8T164-Q1 Automotive 8-Bit Parallel-Load Shift Register With Logic-Level Shifter MARCH 2024

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SN74LV8T164-Q1 Automotive 8-Bit Parallel-Load Shift Register With Logic-Level Shifter

1 Features

AEC-Q100 qualified for automotive applications: – Device temperature grade 1: -40°C to +125°C – Device HBM ESD classification level 2 – Device CDM ESD classification level C4B
Available in wettable flank QFN package
Latching logic with known power-up state provides consistent start-up behavior
Wide operating range of 1.65V to 5.5V
5.5V tolerant input pins
Single-supply voltage translator (refer to LVxT Enhanced Input Voltage): – Up translation:
1.2V to 1.8V
1.5V to 2.5V
1.8V to 3.3V
3.3V to 5.0V – Down translation:
5.0V, 3.3V to 2.5V
5.0V to 3.3V
Up to 150Mbps with 5V or 3.3V VCC
Supports standard function pinout
Latch-up performance exceeds 250mA per JESD 17

2 Applications

Digital signage
Controlling an indicator LED
Increase the number of outputs on a microcontroller

3 Description

The SN74LV8T164-Q1 device contains an 8-bit shift register with AND-gated serial inputs and an asynchronous clear ( CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK. The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE (NOM) (3) SN74LV8T164-Q1 PW (TSSOP, 14) 5mm × 6.4mm 5 mm × 4.4mm BQA (WQFN, 14) 3.5mm × 2.5mm 3.5mm × 2.5mm (1) For more information, see Section 11. (2) The package size (length × width) is a nominal value and includes pins, where applicable. (3) The body size (length × width) is a nominal value and does not include pins. CLR A CLK D R Q

5 Additional

B D R Q QHQGQFQEQDQCQBQA D R Q Simplified Logic Diagram (Positive Logic) SN74LV8T164-Q1 SCAS987 – MARCH 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

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4 Pin Configuration and Functions

A B GND QE CLR CLK QA QB QC QD VCC QH QG QF Figure 4-1. PW Package, 14-Pin TSSOP (Top View) B QA QB QC QD GND QH QG QF QE CLR CLK PAD A V CC 1 14 Figure 4-2. BQA Package, 14-Pin WQFN (Transparent Top View) Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. A 1 I Serial input A B 2 I Serial input B QA 3 O Parallel output A QB 4 O Parallel output B QC 5 O Parallel output C QD 6 O Parallel output D GND 7 G Ground CLK 8 I Clock, rising edge triggered CLR 9 I Clear, active-low QE 10 O Parallel output E QF 11 O Parallel output F QG 12 O Parallel output G QH 13 O Parallel output H VCC 14 P Power supply Thermal Pad(2) — The thermal pad can be connect to GND or left floating. Do not connect to any other signal or supply. (1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power (2) BQA package only www.ti.com SN74LV8T164-Q1 SCAS987 – MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: SN74LV8T164-Q1

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage range –0.5 7 V VI Input voltage range(2) –0.5 7 V VO Voltage range applied to any output in the high-impedance or power-off state(2) –0.5 7 V VO Output voltage range(2) –0.5 VCC + 0.5 V IIK Input clamp current VI < -0.5V -20 mA IOK Output clamp current VO < -0.5V or VO > VCC + 0.5V ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA Continuous output current through VCC or GND ±75 mA TJ Junction temperature 150 °C Tstg Storage temperature -65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime. (2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002 HBM ESD Classification Level 2(1) ±2000 VCharged device model (CDM), per AEC Q100-011 CDM ESD Classification Level C4B ±1000 (1) AEC Q100-002 indicate that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) Specification Description Condition MIN MAX UNIT VCC Supply voltage 1.65 5.5 V VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VIH High-level input voltage VCC = 1.65V to 2V 1.1 V VCC = 2.25V to 2.75V 1.28 VCC = 3V to 3.6V 1.45 VCC = 4.5V to 5.5V 2 VIL Low-Level input voltage VCC = 1.65V to 2V 0.51 V VCC = 2.25V to 2.75V 0.65 VCC = 3V to 3.6V 0.75 VCC = 4.5V to 5.5V 0.8 IO Output current VCC = 1.65V to 2V ±8 mAVCC = 2.25V to 2.75V ±15 VCC = 3.3V to 5.0V ±25 Δt/Δv Input transition rise or fall rate VCC = 1.65V to 5.0V 20 ns/V Δt/ΔVCC Safe supply ramp rate for POR VCC = 1.65V to 5.5V 6 µs/V SN74LV8T164-Q1 SCAS987 – MARCH 2024 www.ti.com

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5.3 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted) Specification Description Condition MIN MAX UNIT TA Operating free-air temperature -40 125 °C

5.4 Thermal Information

THERMAL METRIC(1) WBQB (WQFN) PW (TSSOP) UNIT

16 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 105.6 135.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 96.6 70.3 °C/W RθJB Junction-to-board thermal resistance 75.4 81.3 °C/W ΨJT Junction-to-top characterization parameter 19.1 22.5 °C/W ΨJB Junction-to-board characterization parameter 75.4 80.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 56.1 N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C -40°C to 125°C UNIT MIN TYP MAX MIN TYP MAX VOH IOH = -50μA 1.65V to 5.5V VCC-0.1 VCC-0.1 V IOH = -2mA 1.65V to 2V 1.28 1.7 (1) 1.21 IOH = -3mA 2.25V to 2.75V 2 2.4(1) 1.93 VOL IOL = 50µA 1.65V to 5.5V 0.1 0.1 V IOL = 2mA 1.65V to 2V 0.1(1) 0.2 0.25 II VI = 0V or VCC 0V to 5.5V ±0.1 ±1 µA ICC VI = 0V or VCC, IO = 0; open on loading 1.65V to 5.5V 2 20 µA ΔICC One input at 0.3V or 3.4V, other inputs at 0 or VCC, IO = 0 5.5V 1.35 1.5 mA One input at 0.3V or 1.1V, other inputs at 0 or VCC, IO = 0 1.8V 10 20 µA CI VI = VCC or GND 5V 4 10 10 pF CO VO = VCC or GND 5V 3 pF CPD No load, F = 1MHz 5V 106 pF VPOR VCC ramp rate of 6µs/V to 100ms/V 1.65V to 5.5V 1.5 1.5 V (1) Typical value at nearest nominal voltage (1.8V, 2.5V, 3.3V, and 5V) www.ti.com SN74LV8T164-Q1 SCAS987 – MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: SN74LV8T164-Q1

5.6 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER DESCRIPTION CONDITION VCC TA = 25°C -40°C to 125°C UNIT MIN MAX MIN MAX tH Hold time Data after CLK↑ 1.8V 0 0 ns tSU Setup time CLR inactive 1.8V 6.9 8.8 ns tSU Setup time Data before CLK↑ 1.8V 7.7 9.5 ns tW Pulse duration CLK high or low 1.8V 5.9 7 ns tW Pulse duration CLR low 1.8V 4.3 5.2 ns tH Hold time Data after CLK↑ 2.5V 0 0 ns tSU Setup time CLR inactive 2.5V 3.7 5.4 ns tSU Setup time Data before CLK↑ 2.5V 4.5 5.8 ns tW Pulse duration CLK high or low 2.5V 4.3 4.3 ns tW Pulse duration CLR low 2.5V 4.3 4.3 ns tH Hold time Data after CLK↑ 3.3V 0 0 ns tSU Setup time CLR inactive 3.3V 2.5 3.4 ns tSU Setup time Data before CLK↑ 3.3V 3.2 3.9 ns tW Pulse duration CLK high or low 3.3V 4.3 4.3 ns tW Pulse duration CLR low 3.3V 4.3 4.3 ns tH Hold time Data after CLK↑ 5V 0 0 ns tSU Setup time CLR inactive 5V 1.7 2.3 ns tSU Setup time Data before CLK↑ 5V 1.3 1.7 ns tW Pulse duration CLK high or low 5V 4.3 4.3 ns tW Pulse duration CLR low 5V 4.3 4.3 ns

5.7 Switching Characteristics

over operating free-air temperature range(unless otherwise noted). See Parameter Measurement Information PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE VCC TA = 25°C -40°C to 125°C UNIT MIN TYP MAX MIN TYP MAX FMAX - - CL = 15pF 1.8V 46. 3 60 39.

4 MHz

tPLH CLK Q CL = 15pF 1.8V 7.5 20.7 1 23.8 ns tPHL CLK Q CL = 15pF 1.8V 7.5 24.1 1 27.1 ns tPHL CLR Q CL = 15pF 1.8V 7.7 24.7 1 28 ns FMAX - - CL = 50pF 1.8V 38. 11 48 32.

6 MHz

tPLH CLK Q CL = 50pF 1.8V 10.8 25.5 1 29 ns tPHL CLK Q CL = 50pF 1.8V 10.8 29.2 1 32.3 ns tPHL CLR Q CL = 50pF 1.8V 11 29.7 1 33.2 ns FMAX - - CL = 15pF 2.5V 66. 2 85.8 56. tPLH CLK Q CL = 15pF 2.5V 5.7 12.2 1 14.7 ns tPHL CLK Q CL = 15pF 2.5V 5.7 13.2 1 16 ns tPHL CLR Q CL = 15pF 2.5V 5.9 14.4 1 17.3 ns FMAX - - CL = 50pF 2.5V 58. 8 68.6 46. tPLH CLK Q CL = 50pF 2.5V 8.3 15.2 1 18.1 ns SN74LV8T164-Q1 SCAS987 – MARCH 2024 www.ti.com

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5.7 Switching Characteristics (continued)

5 MHz

tPLH CLK Q CL = 15pF 3.3V 4.4 9.5 1 11.1 ns tPHL CLK Q CL = 15pF 3.3V 4.4 9.2 1 11.2 ns tPHL CLR Q CL = 15pF 3.3V 4.6 10.4 1 12.5 ns FMAX - - CL = 50pF 3.3V 84 98 66. tPLH CLK Q CL = 50pF 3.3V 6.4 11.6 1 13.6 ns tPHL CLK Q CL = 50pF 3.3V 6.4 12.3 1 14.5 ns tPHL CLR Q CL = 50pF 3.3V 6.5 13.5 1 15.8 ns FMAX - - CL = 15pF 5V 135 175 115 MHz tPLH CLK Q CL = 15pF 5V 3.4 8.3 1 9.3 ns tPHL CLK Q CL = 15pF 5V 3.4 7 1 8.4 ns tPHL CLR Q CL = 15pF 5V 3.5 7.1 1 8.6 ns FMAX - - CL = 50pF 5V 120 140 95 MHz tPLH CLK Q CL = 50pF 5V 4.9 9.7 1 11 ns tPHL CLK Q CL = 50pF 5V 4.9 9.4 1 11 ns tPHL CLR Q CL = 50pF 5V 5 9.5 1 11.2 ns

5.8 Noise Characteristics

VCC = 5 V, CL = 50 pF, TA = 25°C PARAMETER DESCRIPTION MIN TYP MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.2 0.8 V VOL(V) Quiet output, minimum dynamic VOL -0.9 -0.2 V VOH(V) Quiet output, minimum dynamic VOH 4.4 4.7 V VIH(D) High-level dynamic input voltage 2 V VIL(D) Low-level dynamic input voltage 0.8 V www.ti.com SN74LV8T164-Q1 SCAS987 – MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: SN74LV8T164-Q1

5.9 Typical Characteristics

TA = 25°C (unless otherwise noted) IOH (mA) VOH (V) 1.5 2.5 3.5 4.5 1.8 V 2.5 V 3.3 V 5.0 V Figure 5-1. Output Voltage vs Current in HIGH State IOL (mA) VOL (V) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 1.8 V 2.5 V 3.3 V 5.0 V Figure 5-2. Output Voltage vs Current in LOW State IOH (mA) VOH (V) 4.3 4.35 4.4 4.45 4.5 4.55 4.6 4.65 4.7 4.75 4.8 4.85 4.9 4.95 -40°C 25°C 125°C Figure 5-3. Output Voltage vs Current in HIGH State; 5V Supply IOL (mA) VOL (V) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -40°C 25°C 125°C Figure 5-4. Output Voltage vs Current in LOW State; 5V Supply IOH (mA) VOH (V) 2.5 2.55 2.6 2.65 2.7 2.75 2.8 2.85 2.9 2.95 3.05 3.1 3.15 3.2 3.25 3.3 -40°C 25°C 125°C Figure 5-5. Output Voltage vs Current in HIGH State; 3.3V Supply IOL (mA) VOL (V) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 -40°C 25°C 125°C Figure 5-6. Output Voltage vs Current in LOW State; 3.3V Supply SN74LV8T164-Q1 SCAS987 – MARCH 2024 www.ti.com

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5.9 Typical Characteristics (continued)

TA = 25°C (unless otherwise noted) IOH (mA) VOH (V) 1.9 1.95 2.05 2.1 2.15 2.2 2.25 2.3 2.35 2.4 2.45 2.5 -40°C 25°C 125°C Figure 5-7. Output Voltage vs Current in HIGH State; 2.5V Supply IOL (mA) VOL (V) 0 2 4 6 8 10 12 14 16 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 -40°C 25°C 125°C Figure 5-8. Output Voltage vs Current in LOW State; 2.5V Supply IOH (mA) VOH (V) 1.4 1.425 1.45 1.475 1.5 1.525 1.55 1.575 1.6 1.625 1.65 1.675 1.7 1.725 1.75 1.775 1.8 -40°C 25°C 125°C Figure 5-9. Output Voltage vs Current in HIGH State; 1.8V Supply IOL (mA) VOL (V) 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22 0.24 0.26 0.28 -40°C 25°C 125°C Figure 5-10. Output Voltage vs Current in LOW State; 1.8V Supply www.ti.com SN74LV8T164-Q1 SCAS987 – MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: SN74LV8T164-Q1

6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily for the examples listed in the following table. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω, tt < 2.5ns. For clock inputs, fmax is measured when the input duty cycle is 50%. The outputs are measured individually with one input transition per measurement. CL (1) From Output Under Test Test Point (1) CL includes probe and test-fixture capacitance. Figure 6-1. Load Circuit for Push-Pull Outputs 50% tw Input 50% VCC 0 V Figure 6-2. Voltage Waveforms, Pulse Duration Clock Input 50% VCC 0 V 50% 50% VCC 0 V tsu Data Input th Figure 6-3. Voltage Waveforms, Setup and Hold Times 50%Input 50% VCC 0 V 50% 50% VOH VOL tPLH (1) tPHL (1) VOH VOL tPHL (1) tPLH (1) Output Output 50% 50% (1) The greater between tPLH and tPHL is the same as tpd. Figure 6-4. Voltage Waveforms Propagation Delays VOH VOL Output VCC 0 V Input tf (1)tr (1) 90% 10% 90% 10% tr (1) 90% 10% tf (1) 90% 10% (1) The greater between tr and tf is the same as tt. Figure 6-5. Voltage Waveforms, Input and Output Transition Times Quiet Output VOH(P), VOL(P) VOL(V) Noise values measured with all other outputs simultaneously switching. Figure 6-6. Voltage Waveforms, Noise SN74LV8T164-Q1 SCAS987 – MARCH 2024 www.ti.com

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7 Detailed Description

7.1 Overview

The SN74LV8T164-Q1 is an 8-bit shift register with 2 serial inputs (A and B) connected through an AND gate, as well as an asynchronous clear (CLR). The device requires a high signal on both A and B to set the input data line high; a low signal on either input will set the input data line low. Data at A and B can be changed while CLK is high or low, provided that the minimum set-up time requirements are met. The CLK pin of the SN74LV8T164-Q1 is rising-edge triggered, activating on the transition from LOW to HIGH. Upon a positive-edge trigger, the device will store the result of the (A ● B) input data line in the first register and propagate each register’s data to the next register. The data of the last register, Q H, will be discarded at each clock trigger. If a low signal is applied to the CLR pin, then the SN74LV8T164-Q1 will set all registers to a logical low value immediately.

7.2 Functional Block Diagram

A B D R D R D R D R D R D R D R D R QA QB QC QD QE QF QG QH 3 4 5 6 10 11 12 13 Q Q Q Q Q Q Q Q

7.3 Feature Description

7.3.1 Balanced CMOS Push-Pull Outputs

This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink and source similar currents. The drive capability of this device may create fast edges into light loads, so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important to limit the output power of the device to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times. Unused push-pull CMOS outputs should be left disconnected.

7.3.2 Latching Logic with Known Power-Up State

This device includes latching logic circuitry. Latching circuits commonly include D-type latches and D-type flip-flops, but include all logic circuits that act as volatile memory. In typical logic devices, the output state of each latching circuit is unknown after power is initially applied; however, this device includes an added Power On Reset (POR) circuit which sets the states of all included latching circuits during the power-up ramp prior to the device starting normal functionality. VPOR(min) VPOR(max) t VCC Figure 7-1. Supply (VCC) Ramp Characteristics for Known Power-Up State Figure 7-1 shows a correct supply voltage turn-on ramp and defines values used in the Recommended Operating Conditions and Electrical Characteristics tables. www.ti.com SN74LV8T164-Q1 SCAS987 – MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: SN74LV8T164-Q1

Prior to starting the power-on ramp, the supply must be completely off (VCC ≤ VPOR(min)). The supply voltage must ramp at a rate within the range provided in the Recommended Operating Conditions table. The output state of each latching logic circuit only remains stable as long as power is applied to the device (V CC ≥ VPOR(max)). Variation from these recommendations will result in the device having an unknown power-up state.

7.3.3 LVxT Enhanced Input Voltage

The SN74LV8T164-Q1 belongs to TI's LVxT family of logic devices with integrated voltage level translation. This family of devices was designed with reduced input voltage thresholds to support up-translation, and inputs tolerant of signals with up to 5.5V levels to support down-translation. For proper functionality, input signals must remain at or above the specified V IH(MIN) level for a HIGH input state, and at or below the specified V IL(MAX) for a LOW input state. Figure 7-2 shows the typical V IH and VIL levels for the LVxT family of devices, as well as the voltage levels for standard CMOS devices for comparison. The inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings , and the maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I). Input signals must transition between valid logic states quickly, as defined by the input transition rate in the Recommended Operating Conditions table. Failing to meet this specification will result in excessive power consumption and could cause oscillations. For more details, see the Implications of Slow or Floating CMOS Inputs application report. Do not leave inputs floating at any time during operation. Unused inputs must be terminated at a valid high or low voltage level. If a system will not be actively driving an input at all times, then a pull-up or pull-down resistor can be added to provide a valid input voltage during these times. The resistor value will depend on multiple factors; however, a 10kΩ resistor is recommended and will typically meet all requirements. SN74LV8T164-Q1 SCAS987 – MARCH 2024 www.ti.com

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7.3.4 Wettable Flanks

This device includes wettable flanks for at least one package. See the Features section on the front page of the data sheet for which packages include this feature. Package We able Flank Lead PCB Pad Standard Lead Package Solder Figure 7-3. Simplified Cutaway View of Wettable-Flank QFN Package and Standard QFN Package After Soldering Wettable flanks help improve side wetting after soldering, which makes QFN packages easier to inspect with automatic optical inspection (AOI). As shown in Figure 7-3 , a wettable flank can be dimpled or step-cut to provide additional surface area for solder adhesion which assists in reliably creating a side fillet. See the mechanical drawing for additional details.

7.3.5 Clamp Diode Structure

As Figure 7-4 shows, the outputs to this device have both positive and negative clamping diodes, and the inputs to this device have negative clamping diodes only. CAUTION Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input and output voltage ratings may be exceeded if the input and output clamp- current ratings are observed. Figure 7-4. Electrical Placement of Clamping Diodes for Each Input and Output SN74LV8T164-Q1 SCAS987 – MARCH 2024 www.ti.com

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7.4 Device Functional Modes

Function Table lists the functional modes of the SN74LV8T164-Q1. Table 7-1. Function Table INPUTS(1) FUNCTION A B CLR CLK X X L X Shift register is cleared. L X H ↑ First stage of the shift register goes low. Other stages store the data of previous stage, respectively. X L H ↑ First stage of the shift register goes low. Other stages store the data of previous stage, respectively. H H H ↑ First stage of the shift register goes high. Other stages store the data of previous stage, respectively. (1) H = High Voltage Level, L = Low Voltage Level, X = Don't Care www.ti.com SN74LV8T164-Q1 SCAS987 – MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: SN74LV8T164-Q1

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

In this application, the SN74LV8T164-Q1 is used to control seven-segment displays. Unlike other I/O expanders, the SN74LV8T164-Q1 does not need a communication interface for control. It can easily operate with simple GPIO pins. Additional control is provided with two serial inputs that feed into an AND gate. At power-up, the initial state of the shift registers is unknown. To give them a defined state, the shift register needs to be cleared. An RC can be connected to the CLR pin as shown in Figure 8-1 to initialize the shift register to all zeros.

8.2 Typical Application

g f a b DP c d e a b c d e f g DP GND VCC A B CLK MCU VCC Figure 8-1. Typical Application Block Diagram

8.2.1 Design Requirements

8.2.1.1 Power Considerations

Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics. The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the SN74LV8T164-Q1 plus the maximum static supply current (I CC) listed in the Electrical Characteristics, and any transient current required for switching. The logic device can only source as much current as is provided by the positive supply source. Ensure the maximum total current through V CC listed in the Absolute Maximum Ratings is not exceeded. The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the SN74LV8T164-Q1 plus the maximum supply current, I CC, listed in the Electrical Characteristics , and any transient current required for switching. The logic device can only sink as much current as can be sunk into SN74LV8T164-Q1 SCAS987 – MARCH 2024 www.ti.com

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its ground connection. Ensure the maximum total current through GND listed in the Absolute Maximum Ratings is not exceeded. The SN74LV8T164-Q1 can drive a load with a total capacitance less than or equal to 50pF while still meeting all of the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed 50pF. The SN74LV8T164-Q1 can drive a load with total resistance described by R L ≥ VO / I O, with the output voltage and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the high state, the output voltage in the equation is defined as the difference between the measured output voltage and the supply voltage at the VCC pin. Total power consumption can be calculated using the information provided in CMOS Power Consumption and Cpd Calculation. Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices. CAUTION The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum Ratings. These limits are provided to prevent damage to the device.

8.2.1.2 Input Considerations

Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do not exceed the maximum input voltage range found in the Absolute Maximum Ratings. Unused inputs must be terminated to either V CC or ground. These can be directly terminated if the input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the SN74LV8T164-Q1 (as specified in the Electrical Characteristics), and the desired input transition rate. A 10k Ω resistor value is often used due to these factors. The SN74LV8T164-Q1 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined in the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power consumption, and reduction in device reliability. Refer to the Feature Description section for additional information regarding the inputs for this device. www.ti.com SN74LV8T164-Q1 SCAS987 – MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: SN74LV8T164-Q1

8.2.1.3 Output Considerations

The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will decrease the output voltage as specified by the V OH specification in the Electrical Characteristics. The ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as specified by the VOL specification in the Electrical Characteristics. Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected directly together. This can cause excessive current and damage to the device. Two channels within the same device with the same input signals can be connected in parallel for additional output drive strength. Unused outputs can be left floating. Do not connect outputs directly to VCC or ground. Refer to Feature Description section for additional information regarding the outputs for this device.

8.2.2 Detailed Design Procedure

Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout section. 2. Ensure the capacitive load at the output is ≤ 50pF. This is not a hard limit; by design, however, it will optimize performance. This can be accomplished by providing short, appropriately sized traces from the SN74LV8T164-Q1 to one or more of the receiving devices. 3. Ensure the resistive load at the output is larger than (VCC / IO(max))Ω. Doing this will prevent the maximum output current from the Absolute Maximum Ratings from being violated. Most CMOS inputs have a resistive load measured in MΩ; much larger than the minimum calculated previously. 4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however, can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation. SN74LV8T164-Q1 SCAS987 – MARCH 2024 www.ti.com

18 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: SN74LV8T164-Q1

8.2.3 Application Curves

A B CLR QA QB QC QD QE QF QG QH Clear Clear Serial Inputs Outputs Figure 8-2. Application Timing Diagram www.ti.com SN74LV8T164-Q1 SCAS987 – MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: SN74LV8T164-Q1

8.3 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions . Each V CC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. The 0.1 μF and 1μF capacitors are commonly used in parallel. As shown in the following layout example, install the bypass capacitor as close to the power terminal as possible for best results.

8.4 Layout

8.4.1 Layout Guidelines

When using multiple-input and multiple-channel logic devices inputs must never be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or V CC, whichever makes more sense for the logic function or is more convenient.

8.4.2 Layout Example

A CLK CLR GND VCC B QB QD 0.1 F Bypass capacitor placed close to the device Avoid 90° corners for signal lines Recommend GND flood f ill for improved signal isolation, noise reduction, and thermal dissipation Unused output left floating Unused inputs tie to GND or VCC QH Figure 8-3. Example Layout for the SN74LV8T164-Q1 in TSSOP SN74LV8T164-Q1 SCAS987 – MARCH 2024 www.ti.com

Product Folder Links: SN74LV8T164-Q1

9 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.

9.1 Documentation Support

9.1.1 Related Documentation

For related documentation, see the following:

Texas Instruments, CMOS Power Consumption and Cpd Calculation application report
Texas Instruments, Designing With Logic application report
Texas Instruments, Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices application report

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. DATE REVISION NOTES March 2024 * Initial Release

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com SN74LV8T164-Q1 SCAS987 – MARCH 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: SN74LV8T164-Q1

www.ti.com 18-May-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CLV8T164QWBQARQ1 ACTIVE WQFN BQA 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LT164Q Samples SN74LV8T164QPWRQ1 ACTIVE TSSOP PW 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVT164Q Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 18-May-2024 OTHER QUALIFIED VERSIONS OF SN74LV8T164-Q1 :

Catalog : SN74LV8T164 NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product Addendum-Page 2

www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.19 TYP6.6 6.2

1.2 MAX

0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 5.1 4.9 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WQFN - 0.8 mm max heightBQA 14 PLASTIC QUAD FLATPACK - NO LEAD2.5 x 3, 0.5 mm pitch 4227145/A

www.ti.com PACKAGE OUTLINE 2.6 2.4 3.1 2.9 0.8 0.6 0.05 0.00 2X 2 8X 0.5 2X 0.5 14X 0.5 0.3 14X 0.3 0.2 1.5 0.1 1 0.1

0.1 MIN

(0.2) TYP (0.16) TYP (0.13) WQFN - 0.8 mm max heightBQA0014B PLASTIC QUAD FLATPACK - NO LEAD 4227062/B 09/2021 0.08 C 0.05 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID SYMM EXPOSED THERMAL PAD SYMM 7 8 141 SCALE 4.500 A-A 35.000 SECTION A-A TYPICAL AB C

www.ti.com EXAMPLE BOARD LAYOUT 10X (0.5) (0.5) (R0.05) TYP

0.07 MAX

0.07 MIN

14X (0.6) 14X (0.25) (2.3) (2.8) (1.5) (1) ( 0.2) TYP VIA WQFN - 0.8 mm max heightBQA0014B PLASTIC QUAD FLATPACK - NO LEAD 4227062/B 09/2021 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X SEE SOLDER MASK DETAIL 7 8 141 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 14X (0.6) 14X (0.25) 10X (0.5) (2.3) (2.8) (1.38) (0.95) (R0.05) TYP WQFN - 0.8 mm max heightBQA0014B PLASTIC QUAD FLATPACK - NO LEAD 4227062/B 09/2021 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 20X EXPOSED PAD 15 87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SYMM SYMM 7 8 141

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