CLC030VEC

CLC030 NSC | Alldatasheet

Document overview

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Technical content

Features

n SDTV/HDTV serial digital video standard compliant n Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.4835Gbps and 1.485 Gbps SDV data rates with auto-detection n LSB dithering option n No external serial data rate setting or VCO filtering components required* n Fast PLL lock time:< 150µs typical at 1.485 Gbps n Adjustable depth video FIFO for timing alignment n Built-in self-test (BIST) and video test pattern generator (TPG)* n Automatic EDH/CRC word and flag generation and insertion n On-chip ancilliary data FIFO and insertion control circuitry n Flexible control and configuration I/O port n LVCMOS compatible data and control inputs and outputs n 75Ω ECL-compatible, differential, serial cable-driver outputs n 3.3V I/O power supply, 2.5V logic power supply operation n Low power: typically 430mW n 64-pin TQFP package n Commercial temperature range 0˚C to +70˚C * Patent applications made or pending.

Applications

n SDTV/HDTV parallel-to-serial digital video interfaces for: — Video cameras — VTRs — Telecines — Digital video routers and switchers — Digital video processing and editing equipment — Video test pattern generators and digital video test equipment — Video signal generators Order Number CLC030VEC 64-Pin TQFP NS Package Number VEC-64A PRELIMINARY February 2002 CLC030 SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver © 2002 National Semiconductor Corporation DS200003 www.national.com

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See NS Package Number VEC-64A CLC030 www.national.com 4

Absolute Maximum Ratings(Note 1) It is anticipated that this device will not be offered in a military qualified version.If Military/Aerospace speci- fied devices are required, please contact the National Semiconductor Sales Office / Distributors for availability and specifications. CMOS I/O Supply Voltage DDIO –V SSIO ): 4.0V SDO Supply Voltage (VDDSD –V SSSD ): 4.0V Digital Logic Supply Voltage (VDDD –V SSD ): 3.0V PLL Supply Voltage (VDDPLL –V SSPLL ): 3.0V CMOS Input Voltage (Vi): VSSIO −0.15V to VDDIO +0.15V CMOS Output Voltage (Vo): VSSIO −0.15V to VDDIO +0.15V CMOS Input Current (single input): V i=VSSIO −0.15V: −5 mA V i=VDDIO +0.15V: +5 mA CMOS Output Source/Sink Current: ±10 mA SDO Output Sink Current: 40 mA Package Thermal Resistance θ JA @ 0 LFM Airflow 47˚C/W θJA @ 500 LFM Airflow 27˚C/W θJC 6.5˚C/W Storage Temp. Range: −65˚C to +150˚C Junction Temperature: +150˚C Lead Temperature (Soldering 4 Sec): +260˚C ESD Rating (HBM): 2 kV ESD Rating (MM): 250V Recommended Operating Conditions Symbol Parameter Conditions Reference Min Typ Max Units VDDIO CMOS I/O Supply Voltage VDDIO −V SSIO 3.150 3.300 3.450 V VDDSD SDO Supply Voltage V DDSD −VSSSD 3.150 3.300 3.450 V VDDD Digital Logic Supply Voltage VDDD –V SSD 2.375 2.500 2.625 V VDDPLL PLL Supply Voltage V DDPLL –V SSPLL 2.375 2.500 2.625 V VIL CMOS Input Voltage, Low Level VSSIO V VIH CMOS Input Voltage High Level VDDIO V TA Operating Free Air Temperature 0 +70 ˚C tJIT Video Clock Jitter V CLK 100 ps P-P Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3). Symbol Parameter Conditions Reference Min Typ Max Units VIH Input Voltage High Level All LVCMOS Inputs

2.0 V DDIO V

VIL Input Voltage Low Level V SSIO 0.8 V IIH Input Current High Level VIH =V DDIO +90 +150 µA IIL Input Current Low Level VIL =V SSIO −1 −20 µA VOH CMOS Output Voltage High Level IOH = −6.6 mA All LVCMOS Outputs 2.4 2.7 V DDIO V VOL CMOS Output Voltage Low Level IOL = +6.6 mA VSSIO VSSIO +0.3 VSSIO +0.5V V VSDO Serial Driver Output Voltage Test Circuit, Test Loads Shall Apply SDO, SDO 720 800 880 mV P-P IDD (3.3V) Power Supply Current, 3.3V Supply, Total VCLK = 27 MHz, NTSC Colour Bar Pattern, Test Circuit, Test Loads Shall Apply V DDIO ,V DDSD 48 65 mA IDD (3.3V) Power Supply Current, 3.3V Supply, Total VCLK = 74.25 MHz, NTSC Colour Bar Pattern, Test Circuit, Test Loads Shall Apply V DDIO ,V DDSD 66 90 mA CLC030 www.national.com5

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3). Symbol Parameter Conditions Reference Min Typ Max Units IDD (2.5V) Power Supply Current, 2.5V Supply, Total VCLK = 27 MHz, NTSC Colour Bar Pattern, Test Circuit, Test Loads Shall Apply V DDD ,V DDZ , VDDPLL 66 85 mA IDD (2.5V) Power Supply Current, 2.5V Supply, Total VCLK = 74.25 MHz, NTSC Colour Bar Pattern, Test Circuit, Test Loads Shall Apply V DDD ,V DDZ , VDDPLL 85 110 mA Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3). Symbol Parameter Conditions Reference Min Typ Max Units fVCLK Parallel Video Clock Frequency VCLK 27 74.25 MHz DC V Video Clock Duty Cycle VCLK 45 50 55 % fACLK Ancilliary Clock Frequency ACLK VCLK MHz DC A Ancilliary Clock Duty Cycle ACLK 45 50 55 % tr,tf Input Clock and Data Rise Time, Fall Time 10%–90% V CLK ,A CLK , DV N ,A DN 1.0 1.5 3.0 ns BR SDO Serial Data Rate (Notes 5, 6) SDO, SDO 270 1,485 M bps tr,tf Rise Time, Fall Time 20%–80%, (Note 6) SDO, SDO 270 ps tr,tf Rise Time, Fall Time 20%–80%, (Note 5) SDO, SDO 500 ps Output Overshoot (Note 4) SDO, SDO 5% tj Serial Output Jitter, Intrinsic

270 Mbps, (Notes 5, 9, 10) SDO, SDO 200 ps P-P

tj Serial Output Jitter, Intrinsic 1,485 Mbps, (Notes 6, 9, 10) SDO, SDO 120 ps P-P tLOCK Lock Time (Notes 5, 7) (SD Rates) 15 ms tLOCK Lock Time (Notes 6, 7) (HD Rates) 15 ms tS Setup Time, Video Data Timing Diagram, (Note 4) DV N to VCLK 1.5 2.0 ns tH Hold Time, Video Data Timing Diagram, (Note 4) V CLK to DVN 1.5 2.0 ns tS Setup Time, Anc. Data Port Timing Diagram, (Note 4) AD N to ACLK 1.5 2.0 ns tH Hold Time, Anc. Data Port Timing Diagram, (Note 4) A CLK to ADN 1.5 2.0 ns Note 1:“Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of “Electrical Characteristics” specifies acceptable device operating conditions. Note 2:Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced to VSS =0 V . Note 3:Typical values are stated for VDDIO =V DDSD = +3.3V, VDDD =V DDPLL = +2.5V and TA = +25˚C. Note 4:Spec. is guaranteed by design. Note 5:R L =7 5Ω , AC-coupled@ 270 Mbps,R REF LVL = RREF PRE = 4.75 kΩ 1%, See Test Loadsand Test Circuit. Note 6:R L =7 5Ω , AC-coupled@ 1,485 Mbps,R REF LVL = RREF PRE = 4.75 kΩ 1%, See Test Loadsand Test Circuit. Note 7:Measured from rising-edge of first DVCLK cycle until Lock Detect output goes high (true). Lock time includes format detection time plus PLL lock time. Note 8:Average value measured between rising edges computed over at least one video field. Note 9:Intrinsic timing jitter is measured in accordance with SMPTE RP 184-1996, SMPTE RP 192-1996 and the applicable serial data transmission standard, SMPTE 259M-1997 or SMPTE 292M (proposed). A colour bar test pattern is used. The value of fSCLK is 270 MHz or 360 MHz for SMPTE 259M, 540MHz for SMPTE 344M or 1,485 MHz for SMPTE 292M serial data rates. SeeTiming Jitter Bandpasssection. CLC030 www.national.com 6

Note 10:Intrinsic jitter is defined in accordance with SMPTE RP 184-1996 as: jitter at an equipment output in the absence of input jitter. As applied to this device, the input port is VCLK and the output port is SDO or SDO. Test Loads Timing Jitter Bandpass DS200003-4 DS200003-6 CLC030 www.national.com7

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The CLC030 SDTV/HDTV Serializer is used in digital video signal origination equipment: cameras, video tape recorders, telecines and video test and other equipment. It converts parallel SDTV or HDTV component digital video signals into serial format. Logic levels within this equipment are normally produced by LVCMOS logic devices. The encoder produces serial digital video (SDV) signals conforming to SMPTE 259M, SMPTE 344M (proposed) or SMPTE 292M. The CLC030 operates at parallel data rates of 27.0 MHz, 36.0 MHz, 54.0 MHz, 74.176MHz and 74.25 MHz. Corresponding serial data rates are 270 Mbps, 360 Mbps, 540 Mbps, 1.4835Gbps and 1.485 Gbps. Segmented frame formats are not supported. VIDEO DATA PATH The input data registeraccepts 10-bit standard definition or 20-bit high definition parallel data and associated clock sig- nals having LVCMOS-compatible signal levels. All parallel video data inputs,DV[19:0], have internal pull-down de- vices.VCLK does not have an internal pull-down device. Parallel video data may conform to any of several SMPTE standards: 125M, 267M, 260M, 274M, 295M or 296M. Seg- mented frame formats are not supported. For HDTV data, the upper 10 bits of the DV input are luminance (luma) information and the lower 10 bits are colour difference (chrominance or chroma) information. For SDTV data, the lower order 10 bits contain both luma and chroma informa- tion. Output from this register feeds the video FIFO, video format detection circuit, TRS character detector, SMPTE scrambler, EDH/CRC generators, serializer/NRZI converter and the device control system. Data from the input data register passes into a 4-register deep video FIFO prior to encoding and other processing. The depth of this FIFO is set by a word written into the VIDEO FIFO Depth[2:0]bits in theANC 0 control register. The video format detectorautomatically determines the raster characteristics (video data format) of the parallel input data and configures the CLC030 to properly handle the data. This assures that the data will be properly formatted, that the correct data rate is selected and that ancilliary data, line numbers (HD) and CRC/EDH data are correctly inserted. Indication of the standard being processed is stored in the FORMAT[4:0] bits in theFORMAT 1 control data register. This format data can be programmed for output on the multi-function I/O port. The CLC030 may be configured to operate at a single video format by writing the appropriateFORMAT SET[4:0] control data into theFORMAT 0 control register. Also, the CLC030 may be configured to handle only the standard-definition data formats by setting theSD ONLY bit or only the high- definition data formats by setting theHD ONLY bit in the FORMAT 0 control register. When both of these bits are reset the part automatically detects the data rate and range. The TRS character detectorprocesses the timing refer- ence signals which control raster framing. The TRS detector supplies control signals to the system controller to identify the presence of the valid video data. The system controller supplies necessary control signals to the EDH/CRC control block. TRS character LSB-clipping as prescribed in ITU-R BT.601 is used. LSB-clipping causes all TRS characters with a value between 000h and 003h to be forced to 000h and all TRS characters with a value between 3FCh and 3FFh to be forced to 3FFh. Clipping is done prior to scrambling and EDH/CRC character generation. The CLC030 incorporates circuitry that implements the pro- posed SMPTE recommended practice and method forLSB dithering. Control of this circuitry is via theDither Enablebit in theVIDEO INFO 0 control register. Dithering can be selectively enabled during the vertical blanking interval by use of theV Dither Enablebit in theVIDEO INFO 0 control register. The initial condition ofDither Enableand V Dither Enable is OFF. The SMPTE scrambler accepts 10-bit standard definition or 20-bit high definition parallel video data and encodes it using the polynomial X 9 +X 4 + 1 as specified in the respective standard in SMPTE 259M, SMPTE 344M (proposed) or SMPTE 292M. The data is then serialized and sent to the NRZ-to-NRZI converter before being output. The transmis- sion bit order is LSB-first. The NRZ-to-NRZI converteraccepts NRZ serial data from the SMPTE scrambler. The data is converted to NRZI format using the polynomial (X + 1). The converter’s output goes to the output cable driver amplifier. ANCILLIARY/CONTROL DATA PATH The Ancilliary and Control Data Portserves two functions in the CLC030. It is used to selectively load ancilliary data into the Ancilliary Data FIFO for insertion into the video data stream. The utilization and flow of ancilliary data within the device is managed by a system of control bits, masks and IDs in the control data registers. This port also provides read/write access to contents of the configuration and con- trol registers. Configuration of the multi-function I/O Port is also controlled by information stored in the control data registers. Ancilliary and control data are input via the 10-bit Ancilliary/Control Data Port,AD[9:0]. The signalsRD/WR , ANC/CTRL and ACLK control data flow through the port. The operation and frequency ofACLK is completely inde- DS200003-8 CLC030 www.national.com9

Device Operation(Continued) the CLC030 has detected the video format being received. This format detect function involves determination of the major raster parameters such as line length, number of video lines in a frame, and so forth. This is done so that information like line numbering can be correctly inserted. The PLL itself will have locked in 200 microseconds (HD rates) or less. However, resolution of all raster parameters may take the majority of a frame. SERIAL DATA OUTPUT DRIVER The serial data outputsprovide low-skew complimentary or differential signals. The output buffer is a current-mode de- sign and is intended to drive AC-coupled and terminated, 75Ω coaxial cables. The driver automatically adjusts rise and fall times depending upon the data rate being processed. Output levels are 800 mV P-P ±10% into 75Ω AC-coupled loads. The 75Ω resistors connected to the SDO outputs function both as drain-load and back-matching resistors. Series back-matching resistors are not used with this output type. The serial output level is controlled by the value of R REF LVL and RREF PRE connected to pin 53 and pin 52, respectively. The R REF LVL resistor sets the peak-to-peak level of the output signal to the required SMPTE nominal level. The R REF PRE resistor sets the value of a pre-emphasis current which is active during the rise and fall times of the HD-rate output signal. The value of R REF LVL is normally 4.75 KΩ , ±1%. The value of RREF PRE is normally 4.75 KΩ ,±1%. The voltage present at these pins is approximately +1.3Vdc. The rise and fall times of this output buffer design automatically adjust and are different for the HD and SD data rate condi- tions. The output buffer is quiescent when the device is in an out-of-lock condition. The output will become active after the PLL is locked and a valid format has been detected. Sepa- rate power feeds are provided for the serial output driver: V SSSD , pins 54, 55, and 59; VDDSD , pin 51; and VDDLS , pin 57. CAUTION: This output buffer is not designed or specified for driving 50Ω or other impedance loads. POWER SUPPLIES, POWER-ON-RESET AND RESET INPUT The CLC030 requires two power supplies, 2.5V for the core logic functions and 3.3V for the I/O functions. The supplies must be applied to the device in proper sequence. The 3.3V supply must be applied prior to or coincident with the 2.5V supply. Application of the 2.5V supply must not precede the 3.3V supply. It is recommended that the 3.3V supply be configured or designed so as to control application of the 2.5V supply in order to satisfy this sequencing requirement. The CLC030 has an automatic,power-on-resetcircuit. Re- set initializes the device and clears TRS detection circuitry, all latches, registers, counters and polynomial generators, sets the EDH/CRC characters to 00h and disables the serial output. Table 1lists the initial conditions of the configuration and control registers. An active-HIGH-true, manualreset inputis available at pin 64. The reset input has an internal pull-down device and may be considered inactive when unconnected. Important:When power is first applied to the device or following a reset, theAncilliary and Control Data Port must be initialized to receive data. This is done by toggling ACLK three times. TEST PATTERN GENERATOR (TPG) AND BUILT-IN SELF-TEST (BIST) The CLC030 includes a built-intest pattern generator (TPG). Four test pattern types are available for all data rates, all HD and SD formats, NTSC and PAL standards, and 4x3 and 16x9 raster sizes. The test patterns are: flat-field black, PLL pathological, equalizer (EQ) pathological and a 75%, 8-colour vertical bar pattern. The pathologicals follow the recommendations of SMPTE RP 178-1996 regarding the test data used. The colour bar pattern has optional band- width limiting coding in the chroma and luma data transitions between bars. TheVPG FILTER ENABLE bit in theVIDEO INFO 0 control register enables the colour bar filter function. The default condition ofVPG FILTER ENABLE is OFF. The TPG also functions as abuilt-in self-test (BIST)which can verify device functionality. The BIST function performs a comprehensive go/no-go test of the device. The test may be run using any of the HD colour bar test patterns or one of two SD test patterns, either a 270 Mb/s NTSC full-field colour bar or a PAL PLL pathological, as the test data pattern. Data is supplied internally in the input data register, processed through the device and tested for errors using either the EDH system for SD or the CRC system for HD. A go/no-go indi- cation is logged in thePass/Failbit of theTEST 0 control register set. This bit may be assigned as an output on the multifunction I/O port. TPG and BIST operation is initiated by loading the code for the desired test pattern into theTest Pattern Select [5:0] bits of theTEST 0 register.Table 5gives the available test patterns and codes. (Recall also the requirement to initialize the ancilliary data port control logic by clockingACLK at least three (3) complete cycles before attempting to load the first register address). In the default power-on state,TPG Enable appears as bit 7 on the multi-function I/O port. The TPG is run by applying the appropriate frequency at the VCLK input for the format and rate selected and then setting theTPG Enable input on the multi-function I/O port, or by setting theTPG Enable bit in theTEST 0 register. Important:If theTPG Enable input of the I/O port is in its default mapping and is not being used to enable the TPG mode, attempting to enable TPG operation by setting bit 6 of theTEST 0 register will not cause the TPG to operate. This is because the low logic level at the I/O port input pulldown overrides the high level being written to the register. The result is the TPG does not run. The Pass/Failbit in theTEST 0 control register indicates the test status. If no errors have been detected, this bit will be set to logic-1 approximately 2 field intervals afterTPG En- able is set. If errors have been detected in the internal circuitry of the CLC030,Pass/Failwill remain reset to a logic-0. The TPG or BIST is halted by resettingTPG Enable. The serial output data is present at the SDO outputs during TPG or BIST operation. Caution !When attempting to use the TPG or BIST imme- diately after applying power or resetting the device, the TPG defaults to the 270Mbps SD rate and expects a VCLK clock frequency of 27MHz as input. This is because the code for the test pattern in theTEST 0 register is set to 00h (525 line, 30 frame, 27MHz, NTSC 4x3 reference black). Attempting to apply a VCLK frequency higher than the device expects, according to the setting in theTEST 0 register, may result in the PLL locking up while attempting to slew to its maximum possible frequency. This situation is not recoverable by the use of the deviceRESET input. To recover from this condi- tion, power must be removed and re-applied to the device. Proper conditioning of the VCLK input, which does not have CLC030 www.national.com13

Device Operation(Continued) an internal pull down device, is mandatory to prevent admis- sion of noise or unwanted signals at any time, especially during power-up or reset sequences. It is strongly recom- mended that VCLK not be applied until device initialization and configuration is completed. Example: Enable the TPG Mode to use the NTSC 270Mbps colour bars as the BIST and TPG pattern. Enable TPG operation using the I/O port. 1. Set ANC/CTRL to a logic-low. 2. Set RD/WR to a logic-low. 3. Present 00Dh toAD[9:0]as theTEST 0 register ad- dress. 4. ToggleACLK . 5. Present 303h toAD[9:0]as the register data (525 line, 30 frame, 27MHz, NTSC 4x3, colour bars (SMPTE 125M)). 6. ToggleACLK . 7. Set TPG ENABLE (I/O Port, bit 7) to a logic-high. 8. ToggleACLK . 9. The PASS/FAIL indicator (I/O Port, bit 6) is monitored for the result of the test. Alternatively, theTEST 0 regis- ter may be read. Bit 7 is the Pass/Fail indicator bit. CONFIGURATION AND CONTROL REGISTERS The configuration and control registers store data which configures the operational modes of the CLC030 or which result from its operation. Many of these registers may be mapped to the multi-function I/O bus to make them available as external I/O functions. These functions and initial values are summarized in Table 1and detailed inTable 2. The power-on default condition for the multi-function I/O port is indicated in Table 1and detailed inTable 6. CLC030 www.national.com 14

TABLE 1. Configuration and Control Data Register Summary

TABLE 1. Configuration and Control Data Register Summary(Continued) Note 11:Connected to multifunction I/O port at power-on. Note 12:ON = logic-1, OFF = logic-0 (positive logic). TABLE 2. Control Register Bit Assignments

TABLE 2. Control Register Bit Assignments(Continued)

TABLE 3. Control Register Addresses sums (SD) or CRC checkwords (HD). data by setting theEDH Force bit in the control registers. of the CRC check characters is 00h. the EDH function is enabled and data is being received. and EDA flags of the EDH checkwords. CHROMA bits in the control registers. ite data back into the register. are available in the configuration and control register set. vertent loss of ancilliary packet data could occur. CHECKSUM ERROR bit in the control registers. output on the multifunction I/O port.

and theANC ID[15:0]is 0000h. insertion of data into the serial data stream. registers, when set, enables tracking of packets in the FIFO. FLUSH STAT ,MSG FLUSH DYN , andMSG FLUSH STAT . will be set.FIFO FLUSH DYN remains set until cleared. FLUSH DYN remains set until cleared. reset after this operation is complete. data stream. This function is not affected byMSG TRACK . may be specified by the user. ordering holds for theProtect[4:0]bits. for the vertical switching point line for Field 1. be used to confine device operation to a range of standards. processing of data at 74.25MHz or 74.176MHz. Table 4. Bit with one of the sub-standards given in the table.

TABLE 4. Video Raster Format Parameters

00001 SDTV, 54 SMPTE 344M 60I 525 507/487 3432 2880

00010 SDTV, 36 SMPTE 267M 60I 525 507/487 2288 1920

00011 SDTV, 27 SMPTE 125M 60I 525 507/487 1716 1440

the device operates in SD/HD mode. duration of the applicable field. Built-in Self-Test (BIST) mode is enabled. PAL, 27MHz, 4x3 PLL Pathological. ten into the remapped location. mapped to I/O port bit 6 in the default condition. eters may take the majority of a frame.

Device Operation(Continued) out-of-band frequency products which can be produced by abrupt transitions in the chroma and luma data when fed to D-to-A converters and picture monitors. The default condi- tion of this bit is reset (off). I/O PIN 0 THROUGH 7 CONFIGURATION REGISTERS (Addresses 0Fh through 16h) The Multi-function I/O Bus Pin Configurationregisters are used to map the bits of the multi-function I/O port to selected bits of the Configuration and Control Registers. Table 6 details the available Configuration and Control register bit functions that may be mapped to the port and their corre- sponding mapping addresses.Pin # SEL[5]in each register indicates whether the port pin is input or output. The port pin will be an input when this bit is set and an output when reset. Input-only functions may not be configured as outputs and vice versa. The remaining lower-order five address bits dis- tinguish the particular function. Example: Program, via the AD port, I/O port bit 0 as output for the CRC Luma Error bit in the control registers. 1. Set ANC/CTRL to a logic-low. 2. Set RD/WR to a logic-low. 3. Present 00Fh toAD[9:0] as the I/O PIN 0 CONFIG register address. 4. ToggleACLK . 5. Present 310h toAD[9:0]as the register data, the bit address of the CRC Luma Error bit in the control regis- ters. 6. ToggleACLK . TEST MODE 0 REGISTER (Address 55h) The four bits of this register are intended for use as test mode functions. They are not normal operating modes. The bits may be set (enabled) or reset (disabled) by writing to the register. Reading this register sets (enables) all bits to their default ON condition. The Scrambler_Enablebit enables operation of the SMPTE scrambler function. This bit is normally ON. The NRZI_Enable bit enables operation of the NRZ-to-NRZI conversion function. This bit is normally ON. The LSB_Clipping bit enables operation of the LSB clipping function. This bit is normally ON. The Sync_Detect_Enablebit enables operation of the TRS detector function. This bit is normally ON. CLC030 www.national.com21

TABLE 5. Test Pattern Selection Codes

TABLE 5. Test Pattern Selection Codes(Continued)

525 Line, 30 Frame, 27 MHz, NTSC 4x3 (SMPTE 125M)

525 Line, 30 Frame, 36 MHz, NTSC 16x9 (SMPTE 125M)

525 Line, 30 Frame, 54 MHz (NTSC)

625 Line, 25 Frame, 54 MHz (PAL)

Note:SD BIST patterns are NTSC 4x3 Colour Bars and PAL 4x3 PLL Pathological. HD BIST patterns are colour bars for each format.

TABLE 6. I/O Configuration Register Addresses for Control Register Functions

TABLE 6. I/O Configuration Register Addresses for Control Register Functions(Continued)

1V DDPLLD Positive Power Supply Input (2.5V supply, PLL Logic) 2V SSPLLD Negative Power Supply Input (2.5V supply, PLL Logic)

3 IO0 Multi-Function I/O Port

4 IO1 Multi-Function I/O Port

5 DV0 Parallel Video Input (HD=Chroma, SD=Luma & Chroma)

6 DV1 Parallel Video Input (HD=Chroma, SD=Luma & Chroma)

7 DV2 Parallel Video Input (HD=Chroma, SD=Luma & Chroma)

8 DV3 Parallel Video Input (HD=Chroma, SD=Luma & Chroma)

9 DV4 Parallel Video Input (HD=Chroma, SD=Luma & Chroma)

SSD Negative Power Supply Input (2.5V supply, Digital Logic)

11 DV5 Parallel Video Input (HD=Chroma, SD=Luma & Chroma)

12 DV6 Parallel Video Input (HD=Chroma, SD=Luma & Chroma)

13 DV7 Parallel Video Input (HD=Chroma, SD=Luma & Chroma)

14 DV8 Parallel Video Input (HD=Chroma, SD=Luma & Chroma)

15 DV9 Parallel Video Input (HD=Chroma, SD=Luma & Chroma)

DDD Positive Power Supply Input (2.5V supply, Digital Logic) 17 V SSD Negative Power Supply Input (2.5V supply, Digital Logic)

18 DV10 Parallel Video Input (HD=Luma)

19 DV11 Parallel Video Input (HD=Luma)

20 DV12 Parallel Video Input (HD=Luma)

21 DV13 Parallel Video Input (HD=Luma)

22 DV14 Parallel Video Input (HD=Luma)

DDIO Positive Power Supply Input (3.3V supply, I/O)

24 DV15 Parallel Video Input (HD=Luma)

25 DV16 Parallel Video Input (HD=Luma)

26 DV17 Parallel Video Input (HD=Luma)

27 DV18 Parallel Video Input (HD=Luma)

28 DV19 Parallel Video Input (HD=Luma)

SSIO Negative Power Supply Input (3.3V supply, I/O)

30 IO2 Multi-Function I/O Port

31 IO3 Multi-Function I/O Port

32 IO4 Multi-Function I/O Port

33 IO5 Multi-Function I/O Port

34 IO6 Multi-Function I/O Port

35 IO7 Multi-Function I/O Port

36 ACLK Ancilliary/Control Clock Input

DDD Positive Power Supply Input (2.5V supply, Digital Logic)

38 AD0 Ancilliary/Control Data Input

39 AD1 Ancilliary/Control Data Input

40 AD2 Ancilliary/Control Data Input

41 AD3 Ancilliary/Control Data Input

42 AD4 Ancilliary/Control Data Input

SSD Negative Power Supply Input (2.5V supply, Digital Logic)

44 AD5 Ancilliary/Control Data Input

45 AD6 Ancilliary/Control Data Input

46 AD7 Ancilliary/Control Data Input

47 AD8 Ancilliary/Control Data Input

48 AD9 Ancilliary/Control Data Input

49 RD/WR

Ancilliary/Control Data Port Read/Write Control Input CLC030 www.national.com 26

Pin Descriptions(Continued) Pin Name Description

50 ANC/CTRL Ancilliary/Control Data Port Function Control Input

51 V DDSD Positive Power Supply Input (3.3V supply, Output Driver) 52 R REF PRE Output Preemphasis Reference Resistor (4.75 K Ω , 1% Nom.) 53 R REF LVL Output Level Reference Resistor (4.75 K Ω , 1% Nom.) 54 V SSSD Negative Power Supply Input (3.3V supply, Output Driver) 55 V SSSD Negative Power Supply Input (3.3V supply, Output Driver)

56 SDO Serial Data True Output

DDLS Positive Power Supply Input (3.3V supply, Level Shift)

58 SDO Serial Data Complement Output

59 V SSLS Negative Power Supply Input (3.3V supply, Level Shift) 60 V DDZ Positive Power Supply Input (2.5V supply, Serializer) 61 V SSPLLA Negative Power Supply Input (2.5V supply, PLL Analog) 62 V DDPLLA Positive Power Supply Input (2.5V supply, PLL Analog)

63 VCLK Video Data Clock Input

64 Reset Manual Reset Input (High True)

Note:All LVCMOS inputs except VCLK and ACLK have internal pull-down devices. CLC030 www.national.com27

Application Information

Complete details for the SD130ASM evaluation PCB are available on National’s WEB site. This circuit demonstrates the capabilities of the CLC030 and allows its evaluation in a native configuration. An assembled demonstration board kit, part number SD130EVK, complete with operating instruc- tions, drawing package and list of materials is available. Contact the Interface Products Group or the Serial Digital Video and Interface Applications Group for ordering informa- tion. Complete circuit board layouts, schematics and other information for the SD130EVK are also available on Nation- al’s WEB site in the application information for this device. For latest product details and availability information, please see: www.national.com/appinfo/interface. PCB Layout and Power System Bypass Recommendations Circuit board layout and stack-up for the CLC030 should be designed to provide noise-free power to the device. Good layout practice also will separate high frequency or high level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic ca- pacitance of the PCB power system which improves power supply filtering, especially at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range 0.01 µF to 0.1 µF. Tantalum capaci- tors may be in the range 2.2 µF to 10 µF. Voltage rating for tantalum capacitors should be at least 5X the power supply voltage being used. It is recommended practice to use two vias at each power pin of the CLC030 as well as all RF bypass capacitor terminals. Dual vias reduce the intercon- nect inductance by up to half, thereby reducing interconnect inductance and extending the effective frequency range of the bypass components. The outer layers of the PCB may be flooded with additional V SS (ground) plane. These planes will improve shielding and isolation as well as increase the intrinsic capacitance of the power supply plane system. Naturally, to be effective, these planes must be tied to the V SS power supply plane at fre- quent intervals with vias. Frequent via placement also im- proves signal integrity on signal transmission lines by pro- viding short paths for image currents which reduces signal distortion. The planes should be pulled back from all trans- mission lines and component mounting pads a distance equal to the width of the widest transmission line or the thickness of the dielectric separating the transmission line from the internal power or ground plane(s) whichever is greater. Doing so minimizes effects on transmission line impedances and reduces unwanted parasitic capacitances at component mounting pads. The CLC030 uses two power supply voltages, 2.5 and 3.3 volts. These supplies connect to the device through seven sets of independent power input pins. The function and system supplied through these is given in the Pin Description Table. The power supply voltages normally share a common 0 volt or ground return system. Either a split plane or sepa- rate power planes can be used to supply the positive volt- ages to the device. In especially noisy power supply environments, such as is often the case when using switching power supplies, sepa- rate filtering may be used at the CLC030’s PLL analog, PLL digital and serial output driver power pins. The CLC030 was designed for this situation. The digital section, PLL and output driver power supply feeds are independent. See the Pin Description Table and the Connection Diagram for de- tails. Supply filtering may take the form of L-section or pi- section, L-C filters in series with these V DD inputs. Such filters are available in a single package from several manu- facturers. Despite being independent feeds, all device power supplies should be applied simultaneously as from a com- mon source. Processing Non-Supported Raster Formats The number and type of HD raster formats has proliferated greatly since the CLC030 was designed. Though not specifi- cally capable of fully or automatically processing these new formats, the CLC030 may still be capable of serializing them. The user is encouraged to experiment with processing of these formats keeping in mind that the CLC030 has not been tested to handle raster formats other than those detailed in Table 4. Therefore, the results from attempts to process

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