CLC021_14 TI1 | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 25

Technical content

www.ti.com SNLS068H –MAY 2000–REVISED APRIL 2013 CLC021SMPTE259MDigitalVideoSerializerwithEDHGenerationandInsertion Check forSamples: CLC021 1FEATURES APPLICATIONS 2• SMPTE 259M SerialDigitalVideo Standard • SMPTE 259M Parallel-to-SerialDigitalVideo Compliant Interfacesfor:

  • Supports AllNTSC and PAL Standard – Video Cameras Component and Composite SerialVideo Data – VTRs Rates – Telecines
  • No ExternalSerialData Rate Settingor VCO – Video TestPatternGeneratorsand DigitalFilteringComponents Required (1) Video TestEquipment
  • FastVCO Lock Time: <75 µs at270 Mbps – Video SignalGenerators
  • Built-InSelf-Test(BIST)and Video TestPattern • Non-SMPTE Video ApplicationsGenerator(TPG) with16 InternalPatterns(1)
  • Other High Data Rate Parallel/SerialVideo and• Automatic EDH Characterand FlagGeneration Data Applicationsand Insertionper SMPTE RP 165
  • Non-SMPTE Mode Operationas Parallel-to- DESCRIPTION SerialConverter The CLC021 SMPTE 259M DigitalVideo Serializer
  • NRZ-to-NRZI Conversion Control withEDH Generationand Insertionis a monolithic integratedcircuitthat encodes, serializesand• HCMOS/LSTTL-Compatible Data and Control transmitsbit-paralleldigitaldata conforming toInputsand Outputs forCLC021AVGZ-5.0, SMPTE 125M and 267M component video andLVCMOS forCLC021AVGZ-3.3 SMPTE 244M composite video standards.The
  • 75Ω ECL-Compatible,Differential,SerialCable- CLC021 can alsoserializeother8- or 10-bitparallel DriverOutputs data.The CLC021 operatesatdataratesfrombelow 100 Mbps to over 400 Mbps. The serialdata clock• SinglePower Supply Operation:5V frequencyis internallygenerated and requiresno(CLC021AVGZ-5.0) or 3.3V(CLC021AVGZ-3.3) externalfrequency setting,trimming or filteringinTTL or ECL Systems components*.• Low Power: Typically235 mW
  • JEDEC 44-Lead MetricPQFP Package
  • Commercial Temperature Range 0°C to+70°C (1) PatentsApplicationsMade orPending. TYPICAL APPLICATION Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2000–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNLS068H –MAY 2000–REVISED APRIL 2013 www.ti.com DESCRIPTION (CONTINUED) Functionsperformedby the CLC021 include:parallel-to-serialdata conversion,ITU-R BT.601-4 inputdata clipping,data encodingusingthe SMPTE polynomial(X9+X4+1),data formatconversionfrom NRZ to NRZI, paralleldataclockfrequencymultiplicationand encodingwiththeserialdata,and differential,serialoutputdata driving.The CLC021 has circuitryforautomaticEDH characterand flaggenerationand insertionperSMPTE RP- 165. The CLC021 has an exclusivebuilt-inself-test(BIST)and videotestpatterngenerator(TPG) with16 component videotestpatterns:referenceblack,PLL and EQ pathologicalsand modifiedcolourbarsin4:3and 16:9rasterformatsforNTSC and PAL formats*. The CLC021 has inputsforenablingsync detection,non-SMPTE mode operation,enablingthe EDH function, NRZ/NRZI mode controland an externalresetcontrol.OutputsareprovidedforH, V and F bits,new TRS sync characterpositionindication,ancilliarydataheader detection,NTSC/PAL rasterindicationand PLL lockdetect. Separatepower pinsfortheoutputdriver,VCO and theserializerimprovepower supplyrejection,outputjitter and noiseperformance. The CLC021AVGZ-5.0V ispowered by a single+5V supply.The CLC021AVGZ-3.3V ispowered by a single +3.3V supply.Power dissipationistypically235 mW includingtwo 75Ω back-matchedoutputloads.The deviceis packaged ina JEDEC metric44-leadPQFP. BLOCK DIAGRAM

2 SubmitDocumentationFeedback Copyright© 2000–2013,Texas InstrumentsIncorporated

ProductFolderLinks:CLC021

www.ti.com SNLS068H –MAY 2000–REVISED APRIL 2013 CONNECTION DIAGRAM Figure1. 44-PinMetricPQFP See Package Number PGB0044A Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:CLC021

SNLS068H –MAY 2000–REVISED APRIL 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. ABSOLUTE MAXIMUM RATINGS (1)(2) SupplyVoltage(VDD −VSS ) CLC021AVGZ-5.0V 6.0V CLC021AVGZ-3.3V 4.0V CMOS/TTL InputVoltage(VI) CLC021AVGZ-5.0V −0.5VtoVDD +0.5V CLC021AVGZ-3.3V -0.3VtoVDD +0.3V CMOS/TTL OutputVoltage(VO ) CLC021AVGZ-5.0V −0.5VtoVDD +0.5V CLC021AVGZ-3.3V -0.3VtoVDD +0.3V CMOS/TTL InputCurrent(singleinput) VI= VSS −0.5V: −5 mA VI= VDD +0.5V: +5 mA InputCurrent,OtherInputs ±1 mA CMOS/TTL OutputSource/SinkCurrent ±16 mA SDO OutputSourceCurrent 22 mA Package Thermal θJA 44-leadMetricPQFP (@ 0 LFM airflow) 60°C/W Resistance (@ 500 LFM airflow) 43°C/W θJC 44-leadMetricPQFP 17°C/W StorageTemp. Range −65°C to+150°C JunctionTemperature +150°C Lead Temperature Soldering4 Sec +260°C ESD Rating(HBM) 2 kV ESD Rating(MM) 150V TransistorCount 33,400 (1) AbsoluteMaximum Ratingsarethoseparametervaluesbeyond whichthelifeand operationofthedevicecannotbe ensured.The statinghereinofthesemaximums shallnotbe construedtoimplythatthedevicecan orshouldbe operatedatorbeyond thesevalues. The tableofElectricalCharacteristicsspecifiesacceptabledeviceoperatingconditions. (2) Itisanticipatedthatthisdevicewillnotbe offeredina militaryqualifiedversion.IfMilitary/Aerospacespecifieddevicesarerequired, pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. RECOMMENDED OPERATING CONDITIONS SupplyVoltage(VDD −VSS ) CLC021AVGZ-5.0 5.0V±10% CLC021AVGZ-3.3 3.3V±10% CMOS/TTL InputVoltage VSS toVDD Maximum DC Biason SDO pins CLC021AVGZ-5.0 3.0V±10% CLC021AVGZ-3.3 1.3V±10% PCLK FrequencyRange 10 to40MHz PCLK DutyCycle 45 to55% D N and PCLK Rise/FallTime 1.0to3.0ns OperatingFreeAirTemperature(TA) 0°C to+70°C

4 SubmitDocumentationFeedback Copyright© 2000–2013,Texas InstrumentsIncorporated

ProductFolderLinks:CLC021

www.ti.com SNLS068H –MAY 2000–REVISED APRIL 2013 DC ELECTRICAL CHARACTERISTICS — CLC021AVGZ-5.0 Over SupplyVoltageand OperatingTemperatureranges,unlessotherwisespecified(1)(2). Symbol Parameter Conditions Reference Min Typ Max Units VIH InputVoltageHighLevel 2.0 VDD V VIL InputVoltageLow Level VSS 0.8 V AllCMOS Inputs IIH InputCurrentHighLevel VIH = VDD +40 +60 µA IIL InputCurrentLow Level VIL= VSS -1 -20 µA VOH CMOS OutputVoltageHigh IOH = −10 mA 2.4 4.7 VDD VLevel AllCMOS Outputs VOL CMOS OutputVoltageLow IOL = +10 mA 0.0 0.3 VSS + 0.5V VLevel VSDO SerialDriverOutputVoltage R L = 75Ω 1%, R REF = 1.69kΩ 1%, SDO, SDO 700 800 900 mV P-P See Figure3 IDD Power SupplyCurrent,Total R L = 75Ω 1%, R REF = 1.69kΩ 1%, PCLK = 27 MHz, NTSC 47 60 mA ColourBar Pattern, See Figure3 (1) Currentflowintodevicepinsisdefinedas positive.Currentflowoutofdevicepinsisdefinedas negative.Allvoltagesarestated referencedtoVSS = 0V. DC ELECTRICAL CHARACTERISTICS — CLC021AVGZ-3.3 Over SupplyVoltageand OperatingTemperatureranges,unlessotherwisespecified(1)(2). Symbol Parameter Conditions Reference Min Typ Max Units VIH InputVoltageHighLevel 2.0 VDD V VIL InputVoltageLow Level VSS 0.6 V AllCMOS Inputs IIH InputCurrentHighLevel VIH = VDD +22 +60 µA IIL InputCurrentLow Level VIL= VSS -1 -20 µA VOH CMOS OutputVoltageHigh IOH = −8 mA 2.4 3.0 VDD VLevel AllCMOS Outputs VOL CMOS OutputVoltageLow IOL = +8 mA 0.0 0.3 VSS + 0.5V VLevel VSDO SerialDriverOutputVoltage R L = 75Ω 1%, R REF = 1.69kΩ 1%, SDO, SDO 720 800 880 mV P-P See Figure3 IDD Power SupplyCurrent,Total R L = 75Ω 1%, R REF = 1.69kΩ 1%, PCLK = 27 MHz, NTSC 33 55 mA ColourBar Pattern, See Figure3 (1) Currentflowintodevicepinsisdefinedas positive.Currentflowoutofdevicepinsisdefinedas negative.Allvoltagesarestated referencedtoVSS = 0V. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:CLC021

SNLS068H –MAY 2000–REVISED APRIL 2013 www.ti.com AC ELECTRICAL CHARACTERISTICS — CLC021AVGZ-5.0 Over SupplyVoltageand OperatingTemperatureranges,unlessotherwisespecified(1). Symbol Parameter Conditions Reference Min Typ Max Units BR SDO SerialData Rate See (2) SDO, SDO 100 400 Mbps ReferenceClockFPCLK PCLK 10 40 MHzInputFrequency ReferenceClockDuty PCLK 45 50 55 %Cycle tr,tf RiseTime,FallTime D N ,PCLK 1.0 1.5 3.0 ns tj SerialOutputJitter 270 Mbps (3),See Figure3 220 psP-P tjit SerialOutputJitter See (2)(4) 100 200 psP-P SDO, SDO tr,tf RiseTime,FallTime 20% –80% (2)(4) 500 800 1500 ps OutputOvershoot See (4) 1 % tLOCK Lock Time See (2)(5) 75 µs tSU SetupTime See (4)and Figure4 D N toPCLK 3 2 ns tHLD HoldTime See (4)and Figure4 D N fromPCLK 3 2 ns LGEN OutputInductance See (4) 6 nH SDO, SDO R GEN OutputResistance See (4) 25k Ω (2) R L = 75Ω,AC-coupled@ 270 M bps,R REF = 1.69kΩ 1%, See TEST LOADS and Figure3. (3) CLC021 mounted intheSD021EVK board,configuredinBIST mode (NTSC colourbars)withPCLK = 27 MHz derivedfromTektronix TG2000 black-burstreference.Timingjittermeasured withTektronixVM700T usingjittermeasurement FFT mode, framerate,1 kHz filterbandwidth,Hanningwindow. (4) Specificationisensuredby design. (5) Measured fromrising-edgeoffirstPCLK cycleuntilLock Detectoutputgoes high(true). AC ELECTRICAL CHARACTERISTICS — CLC021AVGZ-3.3 Over SupplyVoltageand OperatingTemperatureranges,unlessotherwisespecified(1). Symbol Parameter Conditions Reference Min Typ Max Units BR SDO SerialData Rate See (2) SDO, SDO 100 400 Mbps ReferenceClockFPCLK PCLK 10 40 MHzInputFrequency ReferenceClockDuty PCLK 45 50 55 %Cycle tr,tf RiseTime,FallTime D N ,PCLK 1.0 1.5 3.0 ns tj SerialOutputJitter 270 Mbps (3),See Figure3 220 psP-P tjit SerialOutputJitter See (2)(4) 100 200 psP-P SDO, SDO tr,tf RiseTime,FallTime 20% –80% (2)(4) 500 800 1500 ps OutputOvershoot See (4) 1 % tLOCK Lock Time See (2)(5) 75 µs tSU SetupTime See (4)and Figure4 D N toPCLK 4 2 ns tHLD HoldTime See (4)and Figure4 D N fromPCLK 4 2 ns LGEN OutputInductance See (4) 6 nH SDO, SDO R GEN OutputResistance See (4) 25k Ω (2) R L = 75Ω,AC-coupled@ 270 M bps,R REF = 1.69kΩ 1%, See TEST LOADS and Figure3. (3) CLC021 mounted intheSD021EVK board,configuredinBIST mode (NTSC colourbars)withPCLK = 27 MHz derivedfromTektronix TG2000 black-burstreference.Timingjittermeasured withTektronixVM700T usingjittermeasurement FFT mode, framerate,1 kHz filterbandwidth,Hanningwindow. (4) Specificationisensuredby design. (5) Measured fromrising-edgeoffirstPCLK cycleuntilLock Detectoutputgoes high(true).

6 SubmitDocumentationFeedback Copyright© 2000–2013,Texas InstrumentsIncorporated

ProductFolderLinks:CLC021

www.ti.com SNLS068H –MAY 2000–REVISED APRIL 2013 TEST LOADS Figure2. TestLoads Figure3. TestCircuit Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:CLC021

SNLS068H –MAY 2000–REVISED APRIL 2013 www.ti.com TIMING DIAGRAM Figure4. Setup and Hold Timing

8 SubmitDocumentationFeedback Copyright© 2000–2013,Texas InstrumentsIncorporated

ProductFolderLinks:CLC021

www.ti.com SNLS068H –MAY 2000–REVISED APRIL 2013 DEVICE OPERATION The CLC021 SMPTE 259M SerialDigitalVideo Serializerisused indigitalvideosignaloriginationequipment: cameras,videotaperecorders,telecinesand videotestand otherequipment.Itconvertsparallelcomponent or compositedigitalvideosignalsintoserialformat.LogiclevelswithinthisequipmentarenormallyTTL-compatible as producedby CMOS orbipolarlogicdevices.The encoderproducesECL-compatibleserialdigitalvideo(SDV) signalsconformingtoSMPTE 259M-1997.The CLC021 operatesatallstandardSMPTE and ITU-R paralleldata rates.Inaddition,theCLC021 can serializeother8-and 10-bitdata. VIDEO DATA PROCESSING CIRCUITS The inputdata registeraccepts8- or 10-bitparalleldataand clocksignalshavingHCMOS/LSTTL-compatible signallevels.Paralleldata may conform to any of severalstandards:SMPTE 125M, SMPTE 267M, SMPTE 244M orITU-R BT.601.Ifthedatais8-bit,itisconvertedtoa 10-bitrepresentationaccordingtothetypeofdata being input:component 4:2:2per SMPTE 259M paragraph7.1.1,compositeNTSC per paragraph8.1.1or compositePAL perparagraph9.1.1.Eight-bitvideodatacorrespondstotheupper8 bitsofthe10-bitvideodata word and isMSB-aligned.OutputfromthisregisterfeedstheTRS (sync)characterdetector,SMPTE polynomial generator/serializerand theEDH polynomialgenerators/serializersand controlsystem.Allparalleldataand clock inputshave internalpull-downdevices. The sync detectoror TRS characterdetectorreceivesdata from the inputregister.The detectionfunctionis controlledby Sync DetectEnable,a low-true,TTL-compatible,externalsignal.Synchronizationwords,thetiming referencesignals(TRS),start-of-active-video(SAV) and end-of-active-video(EAV) aredefinedinSMPTE 125M and 244M. The sync detectorsuppliescontrolsignalsto the SMPTE polynomialgeneratorto identifythe presenceof validvideodata,and to the EDH controlblock.In SMPTE mode, TRS characterLSB-clippingas prescribedinITU-R BT.601 isenabled.LSB-clippingcauses allTRS characterswitha valuebetween 000h and 003h tobe forcedto000h and allTRS characterswitha valuebetween 3FCh and 3FFh tobe forcedto3FFh. Clippingisdone priortoencodingor EDH charactergeneration.Thisfunctionisdisabledinnon-SMPTE mode operation. Outputsfromthesyncdetectorare: 1. H, V, and F or Line/FieldID— For component video,theseare registeredoutputscorrespondingto input TRS databits6,7 and 8,respectively.These outputsare disabledinnon-SMPTE mode. The outputsare activeHIGH-true.For compositevideo,theseoutputscorrespondtothelineand fieldID encoded as input paralleldatabits2 (MSB) through0.These outputsareregisteredforthedurationoftheapplicablefield. 2. NSP — New Sync Position:A functionand outputindicatingthata new or out-of-placeTRS characterhas been detected.Thisoutputremainsactiveforatleastone horizontallineperiod(resetby EAV) orunlessre- activatedby a subsequentnew or out-of-placeTRS. Activationofthisfunctionflushestheexistingstateof themachine resetingtheEDH generator,SMPTE polynomialgenerator,serializerand NRZ-NRZI converter. Thisfunctionisdisabledinnon-SMPTE mode operation.The outputisactiveHIGH-true. 3. ANC — Ancilliarydata locationoutput:Indicatesthat the ancilliarydata header (component) or flag (composite)has been detected.The outputisa pulsehavinga durationofone PCLK period.The outputis activeHIGH-true. SMPTE POLYNOMIAL GENERATOR AND CONTROLS The SMPTE Mode inputallowstheCLC021 tofunctionbothas a fullSMPTE 259M encoderorgeneral-purpose 8-or10-bitserializer.SMPTE mode isenabledwhen thisinputisLOW. Non-SMPTE mode isenabledwhen this pin is HIGH. This pin is pulledinternallyto VSS when unconnected.When in SMPTE mode, the SMPTE polynomialgenerator;TRS sync detectioncircuitry;EDH controlcircuitry;H, V, F and NSP outputsand TRS clippingareenabled. The SMPTE polynomialgeneratoracceptstheparallelvideodataand encodes itusingthepolynomialX9 + X4 + 1 as specifiedinSMPTE 259M (1997rev.),paragraph5 and Annex C. The transmissionbitorderisLSB-first, perparagraph6. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:CLC021

SNLS068H –MAY 2000–REVISED APRIL 2013 www.ti.com NRZ-TO-NRZI CONVERTER The NRZ-to-NRZI converteracceptsNRZ serialdata from the SMPTE and EDH polynomialgenertorsand convertsittoNRZI usingthepolynomial(X + 1)perSMPTE 259M, paragraph5.2and Annex C. The converter's outputgoes to the outputbufferamplifier.The NRZ/NRZI inputenablesthisconversionfunction.Conversion fromNRZ toNRZI isenabledwhen theinputisa logicLOW. ConversiontoNRZI isdisabledwhen thisinputisa logic-HIGH.Thisfunctionisnotaffectedby theSMPTE mode controlinput.The inputpinispulledinternallyto VSS (NRZI enabled)when unconnected. EDH SYSTEM OPERATION The CLC021 has EDH characterand flaggenerationand insertioncircuitrywhich operatesas proposed in SMPTE RP-165.Inputsand circuitryareprovidedtocontrolgenerationand automaticinsertionoftheEDH check words atproperlocationsintheserialdataoutput. The EDH polynomialgeneratorsacceptparalleldatafrom theinputregisterand generate16-bitserialcheck words usingthe polynomialX16 + X12 + X6 + 1. Separatecalculationsare made foreach videofieldpriorto serialization.SeparateCRCs forthefull-fieldand activepicturealongwithstatusflagsare insertedand serially transmittedwiththeotherdata.Upon beingreset,theinitialstateofallEDH checkcharactersis00h. The EDH controlsystem acceptsinputfrom thesync detectorand controlstheEDH polynomialgeneratorand SMPTE/EDH polynomialinsertionmultiplexer.EDH Enable,an externalTTL-compatible,low-trueinput,enables thiscircuitry.The controllerinsertstheEDH check words intheserialdatastreamatthecorrectpositionsinthe space isformattedperSMPTE 291M. The EDH Force controlinputcauses the insertionof new EDH checkwords and flagsintothe serialoutput regardlessofthepreviousconditionofEDH checkwordsand flagsintheinputparalleldata.Thisfunctionmay be used insituationswhere videocontenthas been edittedthusmaking thepreviousEDH informationinvalid. The NTSC/PAL outputindicatesthetypeofcomponent orcompositedatastandardbeinginputtotheCLC021. Thisoutputisusefulfortroubleshootingormay be used todrivea panelindicator.The outputishighwhen 625- linePAL dataisbeinginputand lowwhen 525-lineNTSC dataisbeinginput. PHASE-LOCKED LOOP AND VCO The phase-locked loop (PLL) system generatesthe outputserialdata clockat 10× the paralleldata clock frequency.Thissystem consistsofa VCO, dividerchain,phase-frequencydetectorand internalloopfilter.The VCO free-runningfrequencyisinternallyset.The PLL automaticallygeneratestheappropriatefrequencyforthe serialclockrateusingtheparalleldataclock(PCLK ) frequencyas itsreference.Loop filteringisinternaltothe CLC021. The VCO haltswhen no PCLK signalispresentorisinactive.PCLK shouldbe appliedafterpower tothe device. The VCO has separateVSSO and VDDO power supplyfeeds,pins27 and 28,whichmay be suppliedpower viaan externallow-passfilter,ifdesired.The PLL acquisition(lock)timeislessthan75 µs @ 270 Mbps. LOCK DETECT The lockdetectoutput(pin26) ofthephase-frequencydetectorisa logicHIGH when theloopislocked.The outputisCMOS/TTL-compatibleand issuitablefordrivingotherCMOS devicesor an LED indicator.The Lock DetectpinreportsthestatusofthePLL.When PCLK islost,itwillswitchlowattheevent. SERIAL DATA OUTPUT BUFFER The current-modeserialdata outputsprovidelow-skewcomplimentaryordifferentialsignals.The outputbuffer designcan drive75Ω coaxialcables(AC-coupled)or 10K/100K ECL/PECL-compatibledevices(DC-coupled). Outputlevelsare 800 mV P-P ±10% into75Ω AC-coupled,back-matchedloads.The outputlevelis400 mV P-P ±10% when DC-coupledinto75Ω.(See APPLICATION INFORMATION fordetails.)The 75Ω resistorsconnected totheSDO outputsareback-matchingresistors.No seriesback-matchingresistorsshouldbe used.Outputlevel iscontrolledby thevalueofR REF connectedtopin35.The valueofR REF isnormally1.69kΩ,±1%. The output bufferisstaticwhen thedeviceisinan out-of-lockcondition.SeparateVSSSD and VDDSD power feeds,pins,37 and 40 areprovidedfortheserialoutputdriver.

10 SubmitDocumentationFeedback Copyright© 2000–2013,Texas InstrumentsIncorporated

ProductFolderLinks:CLC021

10% 90% 10% 90% RESET VDD VDD min VSS VSS 10% PCLK VDD 30Ps min CLC021 www.ti.com SNLS068H –MAY 2000–REVISED APRIL 2013 POWER-ON RESET AND RESET INPUT The CLC021 has an internallycontrolled,automatic,power-on-resetcircuit.Reset clearsTRS detection circuitry,alllatches,registers,countersand polynomialgenerators,setstheEDH charactersto00h and disables the serialoutput.The SDO outputsare tri-statedduringpower-on reset.The partwillremain in the reset conditionuntiltheparallelinputclockisapplied. An active-HIGH-true,manual resetinputisavailableatpin1.Itresetsboththedigitaland PLL blocks.The reset inputhas an internalpull-downdeviceand isinactivewhen unconnected. Itisrecommended thatPCLK notbe asserteduntilatleast30 µs afterpower has reachedVDD min.See Figure5. Ifmanual resetisused duringpower-on,thenPCLK may be assertedatany timeas longas manual resetisnot de-asserteduntilVDD min isreached.See Figure6. Figure5. Power-On Reset Sequence Figure6. Power-On Reset Sequence withManual Reset Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:CLC021

SNLS068H –MAY 2000–REVISED APRIL 2013 www.ti.com BUILT-INSELF-TEST (BIST) The CLC021 has a built-inself-test(BIST)function.The BIST performsa comprehensivego/no-gotestofthe device.The testuses eithera full-fieldcolourbar forNTSC or a PLL pathologicalforPAL as the testdata pattern.Data isinputinternallyintheinputdataregister,processedthroughthedeviceand testedforerrors.A go/no-goindicationisgivenattheTest_Output.Table1 givesdevicepinfunctionsand Table2 givesthetest patterncodes used forthisfunction.The signallevelatTest_Output,pin3,indicatesa pass orfailcondition. The BIST isinitiatedby applyingthecode forthedesiredBIST toD0 throughD3 (D9 throughD4 are00h)and a 27 MHz clockatthePCLK input.Sinceallparalleldatainputsareequippedwithan internalpull-downdevice,only thoseinputsD0 throughD3 whichrequirea logic-1need be pulledhigh.AftertheLock_Detectoutputgoes high indicatingtheVCO islockedon frequency,TPG_Enable, pin29,istakentoa logichigh.The Lock_Detectoutput may be temporarilyconnectedtoTPG_Enable toautomateBIST operation.Test_Output,pin3,ismonitoredfor a pass/failindication.Ifno errorshave been detected,thisoutputwillgo toa logichighlevelapproximately2 field intervalsafterTPG_Enable istakenhigh.Iferrorshave been detectedinthe internalcircuitryof the CLC021, Test_Outputwillremainlow untilthetestisterminated.The BIST isterminatedby takingTPG _Enabletoa logic low.Continuousserialdataoutputisavailableduringthetest. Figure7. Built-InSelf-TestControlSequence TEST PATTERN GENERATOR The CLC021 includesan on-boardtestpatterngenerator(TPG).Four full-fieldcomponent videotestpatterns forbothNTSC and PAL standards,and 4x3 and 16x9 rastersizesareproduced.The testpatternsare:flat-field black,PLL pathological,equalizer(EQ) pathologicaland a modified75%, 8-colourverticalbar pattern.The pathologicalsfollowrecommendationscontainedin SMPTE RP 178–1996 regardingthe testdata used. The colourbarpatterndoes notincorporatebandwidthlimitingcodinginthechroma and luma datawhen transitioning between thebars.Forthisreason,itmay notbe suitableforuse as a visualtestpatternorforinputtovideoD-to- A conversiondevicesunlessmeasures aretakentorestricttheproductionofout-of-bandfrequencycomponents. The TPG isoperatedby applyingthe code forthe desiredtestpatternto D0 throughD3 (D4 throughD9 are 00h).Sinceallparalleldatainputsareequippedwithinternalpull-downdevices,onlythoseinputsD0 throughD3 which requirea logic-1need be pulledhigh.Next,applya 27 MHz or 36 MHz signal,appropriatetotheraster sizedesired,atthePCLK inputand waituntiltheLock_Detectoutputgoes trueindicatingtheVCO islockedon frequency.Then, takeTPG_Enable, pin29, to a logichigh.The serialtestpatterndata appears on the SDO outputs.The Lock_Detectoutputmay be temporarilyconnectedtoTPG_Enable toautomateTPG operation.The TPG mode isexitedby takingTPG_Enable to a logiclow.Table 1 givesdevicepinfunctionsforthismode. Table2 givestheavailabletestpatternsand selectioncodes.

12 SubmitDocumentationFeedback Copyright© 2000–2013,Texas InstrumentsIncorporated

ProductFolderLinks:CLC021

www.ti.com SNLS068H –MAY 2000–REVISED APRIL 2013 Figure8. TestPatternGeneratorControlSequence Table1.BIST and TestPatternGeneratorControlFunctions Pin Name Function

12 D0 TPG Code InputLSB

13 D1 TPG Code Input

14 D2 TPG Code Input

15 D3 TPG Code InputMSB

29 TPG_EN TPG Enable,ActiveHighTrue

3 Test_Out BIST Pass/FailOutput.Pass=High (See textforTiming Requirements) Table2.Component Video TestPatternSelection(1) Standard Frame TestPattern D3 D2 D1 D0 NTSC 4x3 Flat-FieldBlack 0 0 0 0 NTSC 4x3 PLL Pathological 0 0 0 1 NTSC 4x3 EQ Pathological 0 0 1 0 NTSC 4x3 ColourBars,75%, 8-Bars(modified,see text),BIST 0 0 1 1 PAL 4x3 Flat-FieldBlack 0 1 0 0 PAL 4x3 PLL Pathological,BIST 0 1 0 1 PAL 4x3 EQ Pathological 0 1 1 0 PAL 4x3 ColourBars,75%, 8-Bars(modified,see text) 0 1 1 1 NTSC 16x9 Flat-FieldBlack 1 0 0 0 NTSC 16x9 PLL Pathological 1 0 0 1 NTSC 16x9 EQ Pathological 1 0 1 0 NTSC 16x9 ColourBars,75%, 8-bars(modified,see text) 1 0 1 1 PAL 16x9 Flat-FieldBlack 1 1 0 0 PAL 16x9 PLL Pathological 1 1 0 1 PAL 16x9 EQ Pathological 1 1 1 0 PAL 16x9 ColourBars,75%, 8-Bars(modified,see text) 1 1 1 1 (1) D9 throughD4 = 0 (binary) Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:CLC021

SNLS068H –MAY 2000–REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (1) Pin Name Description

1 Reset Manual ResetInput(HighTrue)

2 NRZ- NRZI NRZ-to-NRZIConversionControl(NRZ=High,NRZI=Low)

3 TestOut TestOut (BISTPass/FailIndicator)

4 VSS NegativePower SupplyInput(DigitalLogic)

5 VSS NegativePower SupplyInput(DigitalLogic)

6 VDD PositivePower SupplyInput(DigitalLogic)

7 VDD PositivePower SupplyInput(DigitalLogic)

8 EDH Force ForceInsertionofNew EDH and FlagsinSerialOutputData (HighTrue)

9 EDH Enable EDH EnableInput(Low True)

10 SMPTE Mode SMPTE/non-SMPTE Mode SelectInput(SMPTE Mode=Low)

11 N/C No Connect

12 D0 ParallelData Input(InternalPull-DowntoVSS )

13 D1 ParallelData Input(InternalPull-DowntoVSS )

14 D2 ParallelData Input(InternalPull-DowntoVSS )

15 D3 ParallelData Input(InternalPull-DowntoVSS )

16 D4 ParallelData Input(InternalPull-DowntoVSS )

17 D5 ParallelData Input(InternalPull-DowntoVSS )

18 D6 ParallelData Input(InternalPull-DowntoVSS )

19 D7 ParallelData Input(InternalPull-DowntoVSS )

20 D8 ParallelData Input(InternalPull-DowntoVSS )

21 D9 ParallelData Input(InternalPull-DowntoVSS )

22 PCLK ParallelClockInput(InternalPull-DowntoVSS )

23 H/Line-Fieldb0 (LSB) H-BitOutput(Component);Line-FieldID (Composite)

24 V/Line-Fieldb1 V-BitOutput(Component);Line-FieldID (Composite)

25 F/Line-Fieldb2 (MSB) F-BitOutput(Component);Line-FieldID (Composite)

26 Lock Detect Lock DetectorOutput(HighTrue)

27 VSSO NegativePower SupplyInput(PLL Supply)

28 VDDO PositivePower SupplyInput(PLL Supply)

29 TPG Enable TPG Enable(HighTrue)

30 VSSOD NegativePower SupplyInput(PLL DigitalSupply)

31 VSSOD NegativePower SupplyInput(PLL DigitalSupply)

32 VDDOD PositivePower SupplyInput(PLL DigitalSupply)

33 VDDOD PositivePower SupplyInput(PLL DigitalSupply)

34 N/C No Connect

35 R REF OutputLevelReferenceResistor(1.69kΩ,1% NominalValue)

36 VDDOD PositivePower SupplyInput(PLL DigitalSupply)

37 VSSSD NegativePower SupplyInput(OutputDriver)

38 SDO SerialData TrueOutput

39 SDO SerialData Complement Output

40 VDDSD PositivePower SupplyInput(OutputDriver)

41 Sync DetectEnable ParallelData Sync DetectionEnableInput(Low True)

42 NSP New Sync PositionOutput

43 ANC AncilliaryData Header FlagOutput

44 NTSC/PAL NTSC/PAL Mode IndicatorOutput(PAL=High,NTSC=Low)

(1) AllCMOS/TTL inputshave internalpull-downdevices.

14 SubmitDocumentationFeedback Copyright© 2000–2013,Texas InstrumentsIncorporated

ProductFolderLinks:CLC021

www.ti.com SNLS068H –MAY 2000–REVISED APRIL 2013

APPLICATION INFORMATION

A typicalapplicationcircuitfortheCLC021 isshown inFigure9.Thiscircuitdemonstratesthecapabilitiesofthe CLC021 and allowsitsevaluationina varietyof configurations.Assembled demonstrationboards withmore comprehensiveevaluationoptionsare available,partnumber SD021-5EVK (5V device)or SD021-3EVK (3.3V device).The boards may be orderedthroughany of Texas Instruments'salesoffices.Complete circuitboard layoutsand schematicsincludingGerber photoplotfiles,forthe demonstrationboards are availableon Texas Instruments'websiteintheapplicationinformationforthisdevice. APPLICATION CIRCUIT Figure9. TypicalApplicationCircuit The SD021EVK applicationcircuitboards,Figure10, can accommodate differentinputand outputdriveand loadingoptions.Pin headersare providedforinputand controlI/Osignalaccess.Installtheappropriatevalue resistorpacks,220Ω at RP1 and RP3 and 330Ω at RP2 and RP4, forTTL cabledinterfacesbeforeapplying inputsignals.Install51Ω resistorpacks atRP2 and RP4 forsignalsourcesrequiringsuch loading.Remove any resistorpacksatRP1 and RP3 when using50Ω sourceloading. The board'soutputsmay be DC interfacedto PECL inputsby firstinstalling124Ω resistorsat R1B and R2B, changingR1A and R2A to187Ω and replacingC1 and C2 withshortcircuits.The PECL inputsshouldbe directly connectedtoJ1 and J2 withoutcabling.If75Ω cablingisused toconnecttheCLC021 tothePECL inputs,the voltagedividersused on theCLC021 outputsmust be removed and re-installedon thecircuitboard where the PECL deviceismounted.Thiswillprovidecorrectterminationforthecableand biasingforboththeCLC021's outputsand thePECL inputs.Itismost importanttonotethata 75Ω or equivalentDC loading(measured with respectto the negativesupplyrail)must always be installedat both of the CLC021's SDO outputsto obtain propersignallevelsfromdevice.When using75Ω Thevenin-equivalentloadcircuits,theDC biasappliedtothe SDO outputsshouldnotexceed +3V (+1.3VforCLC021AVGZ-3.3) withrespecttothenegativesupplyrail.Serial outputlevelsshouldbe reducedto400 mV p-p by changingR REF to3.4kΩ.Thismay be done by removingthe OutputLevelshortingjumperon thepostheader. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:CLC021

SNLS068H –MAY 2000–REVISED APRIL 2013 www.ti.com The TestOut outputisintendedformonitoringby equipmenthavinghighimpedance testloading(>500Ω).Ifthe Lock Detectoutputistobe externallymonitored,theattachedmonitoringcircuitshouldpresenta DC resistance greaterthan5 kΩ so as nottoaffectLock Detectindicatoroperation. ConnectLOCK DETECT toTPG ENABLE fortestpatterngeneratorfunction. Remove RP1 & RP3 and replaceRP2 & RP4 with50Ω resistorpacksforcoax interfacing. InstallRP1-4 when usingribboncableforinputinterfacing. Thisboardisdesignedforuse withTTL power suppliesonly. Figure10. SD021EVK Schematic Diagram

16 SubmitDocumentationFeedback Copyright© 2000–2013,Texas InstrumentsIncorporated

ProductFolderLinks:CLC021

www.ti.com SNLS068H –MAY 2000–REVISED APRIL 2013 MEASURING JITTER The testmethod used toobtainthetimingjittervaluegivenintheAC ElectricalSpecificationtableisbased on proceduresand equipmentdescribedinSMPTE RP 192-1996.The recommended practicediscussesseveral methods and indicatordevices.An FFT method performedby standardvideotestequipmentwas used toobtain thedatagiveninthisdatasheet.As such,thejittercharacteristics(orjitterfloor)ofthemeasurement equipment, particularlythemeasurement analyzer,become integraltotheresultingjittervalue.The method and equipment were chosen so thatthetestcan be easilyduplicatedby thedesignengineerusingmost standarddigitalvideo testequipment.Inso doing,similarresultsshouldbe achieved.The intrinsicjitterflooroftheCLC021's PLL is approximately25% of the typicaljittergiven in the electricalspecifications.In production,device jitteris measured on automaticIC testequipment(ATE) usinga differentmethod compatiblewiththatequipment.Jitter measured usingthisATE yieldsvaluesapproximately50% ofthoseobtainedusingthevideotestequipment. The jittertestsetupused toobtainvaluesquotedinthedatasheetconsistsof:

  • Texas InstrumentsSD021-5EVK (SD021-3EVK),CLC021 evaluationkit
  • TektronixTG2000 signalgenerationplatformwithDVG1 option
  • TektronixVM700T Option1S VideoMeasurement Set
  • TektronixTDS 794D, OptionC2 oscilloscope
  • TektronixP6339A passiveprobe
  • 75Ω coaxialcable,3 ft.,Belden8281 orRG59 (2required)
  • ECL-to-TTL/CMOS levelconverter/amplifiersee Figure12. Applytheblack-burstreferenceclockfrom theTG2000 signalgenerator'sBG1 module 27 MHz clockoutputto thelevelconverterinput.The clockamplitudeconverterschematicisshown inFigure12.Adjusttheinputbias controlto givea 50% duty cycleoutputas measured on the oscilloscope/probesystem.Connect the level translatortotheSD021EVK board,connectorP1, PCLK pins(theouter-mostrow ofpinsisground).Configurethe SD021EVK to operatein the NTSC colourbars,BIST mode. Configurethe VM700T to make the jitter measurement inthejitterFFT mode attheframeratewith1 kHz filterbandwidthand Hanningwindow.Configure the setupas shown inFigure11. Switchthe testequipmenton (fromstandbymode) and allowallequipment temperaturesstabilizeper manufacturer'srecommendation. Measure the jittervalue afterallowingthe instrument'sreadingtostabilize(about1 minute).ConsulttheVM700T VideoMeasurement Set Option1S Serial DigitalMeasurements User Manual (documentnumber 071-0074-00)fordetailsofequipmentoperation. The VM700T measurement system'sjitterfloorspecificationat270 Mbps isgivenas 200 ps ±20% (100ps ±5% typical)ofactualcomponents from50 Hz to1 MHz and 200 ps +60%, -30% ofactualcomponents from1 MHz to 10 MHz. To obtainthe actualresidualjitterof the CLC021, a root-sum-squareadjustmentof the jitterreading must be made to compensate forthe measurement system'sjitterfloorspecification.For example,ifthe jitter readingis250 ps,theCLC021 residualjitteristhesquarerootof(2502 − 2002)= 150 ps.The accuracylimitsof thereadingas givenabove apply. Figure11. JitterTestCircuit Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:CLC021

SNLS068H –MAY 2000–REVISED APRIL 2013 www.ti.com Figure12. ECL-to-TTL/CMOS LevelConverter/Amplifer

18 SubmitDocumentationFeedback Copyright© 2000–2013,Texas InstrumentsIncorporated

ProductFolderLinks:CLC021

www.ti.com SNLS068H –MAY 2000–REVISED APRIL 2013 Figure13. JitterPlots PCB LAYOUT AND POWER SYSTEM BYPASS RECOMMENDATIONS Circuitboardlayoutand stack-upfortheCLC021 shouldbe designedtoprovidenoise-freepower tothedevice. Good layoutpracticealsowillseparatehighfrequencyor highlevelinputsand outputsto minimizeunwanted straynoisepickup,feedbackand interference.Power systemperformancemay be greatlyimprovedby usingthin dielectrics(4to10 mils)forpower/groundsandwiches.ThisincreasestheintrinsiccapacitanceofthePCB power system which improves power supply filtering,especiallyat high frequencies,and makes the value and placementofexternalbypass capacitorslesscritical.Externalbypass capacitorsshouldincludebothRF ceramic and tantalumelectrolytictypes.RF capacitorsmay use valuesin the range 0.01 µF to 0.1 µF. Tantalum capacitorsmay be intherange2.2µF to10 µF.Voltageratingfortantalumcapacitorsshouldbe atleast5X the power supplyvoltagebeingused.Itisrecommended practicetouse two viasateach power pinoftheCLC021 as wellas allRF bypass capacitorterminals.Dual viasreducetheinterconnectinductanceby up tohalf,thereby reducinginterconnectinductanceand extendingtheeffectivefrequencyrangeofthebypasscomponents. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:CLC021

SNLS068H –MAY 2000–REVISED APRIL 2013 www.ti.com The outerlayersof the PCB may be floodedwithadditionalVSS (ground)plane.These planeswillimprove shieldingand isolationas wellas increasetheintrinsiccapacitanceofthepower supplyplanesystem.Naturally, tobe effective,theseplanesmust be tiedtotheVSS power supplyplaneatfrequentintervalswithvias.Frequent viaplacementalsoimprovessignalintegrityon signaltransmissionlinesby providingshortpaths forimage currentswhich reduces signaldistortion.The planesshouldbe pulledback from alltransmissionlinesand component mountingpads a distanceequaltothewidthofthewidesttransmissionlineor thethicknessofthe dielectricseparatingthetransmissionlinefromtheinternalpower orgroundplane(s)whicheverisgreater.Doing so minimizeseffectson transmissionlineimpedances and reduces unwanted parasiticcapacitancesat component mountingpads. Inespeciallynoisypower supplyenvironments,such as isoftenthecase when usingswitchingpower supplies, separatefilteringmay be used attheCLC021's VCO and outputdriverpower pins.The CLC021 was designed forthissituation.The digitalsection,VCO and outputdriverpower supplyfeeds are independent(see and CONNECTION DIAGRAM fordetails).Supplyfilteringmay taketheformofL-sectionorpi-section,L-C filtersin serieswiththeseVDD inputs.Such filtersareavailableina singlepackage fromseveralmanufacturers.Despite beingindependentfeeds,alldevicepower suppliesshouldbe appliedsimultaneouslyas froma common source. The CLC021 isfreefrom power supplylatch-upcaused by circuit-induceddelaysbetween the device'sthree separatepower feedsystems.

20 SubmitDocumentationFeedback Copyright© 2000–2013,Texas InstrumentsIncorporated

ProductFolderLinks:CLC021

www.ti.com SNLS068H –MAY 2000–REVISED APRIL 2013

REVISION HISTORY

Changes from RevisionG (April2013)toRevisionH Page Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:CLC021

www.ti.com 1-Nov-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CLC021AVGZ-3.3 NRND QFP PGB 44 96 TBD Call TI Call TI 0 to 70 CLC021A VGZ-3.3 CLC021AVGZ-3.3/NOPB ACTIVE QFP PGB 44 96 Green (RoHS & no Sb/Br) SN Level-3-260C-168 HR 0 to 70 CLC021A VGZ-3.3 CLC021AVGZ-5.0/NOPB ACTIVE QFP PGB 44 96 Green (RoHS & no Sb/Br) SN Level-3-260C-168 HR 0 to 70 CLC021A VGZ-5.0 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

www.ti.com 1-Nov-2013 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Texas InstrumentsIncorporatedand itssubsidiaries(TI)reservetherighttomake corrections,enhancements,improvementsand other changes toitssemiconductorproductsand servicesperJESD46, latestissue,and todiscontinueany productorserviceperJESD48, latest issue.Buyersshouldobtainthelatestrelevantinformationbeforeplacingordersand shouldverifythatsuch informationiscurrentand complete.Allsemiconductorproducts(alsoreferredtohereinas “components”)aresoldsubjecttoTI’s termsand conditionsofsale suppliedatthetimeoforderacknowledgment. TIwarrantsperformanceofitscomponents tothespecificationsapplicableatthetimeofsale,inaccordancewiththewarrantyinTI’s terms and conditionsofsaleofsemiconductorproducts.Testingand otherqualitycontroltechniquesareused totheextentTIdeems necessary tosupportthiswarranty.Exceptwhere mandated by applicablelaw,testingofallparametersofeach component isnotnecessarily performed. TIassumes no liabilityforapplicationsassistanceorthedesignofBuyers’products.Buyersareresponsiblefortheirproductsand applicationsusingTIcomponents.To minimizetherisksassociatedwithBuyers’productsand applications,Buyersshouldprovide adequatedesignand operatingsafeguards. TIdoes notwarrantorrepresentthatany license,eitherexpressorimplied,isgrantedunderany patentright,copyright,mask work right,or otherintellectualpropertyrightrelatingtoany combination,machine,orprocessinwhichTIcomponents orservicesareused.Information publishedby TIregardingthird-partyproductsorservicesdoes notconstitutea licensetouse such productsorservicesora warrantyor endorsementthereof.Use ofsuch informationmay requirea licensefroma thirdpartyunderthepatentsorotherintellectualpropertyofthe thirdparty,ora licensefromTIunderthepatentsorotherintellectualpropertyofTI. ReproductionofsignificantportionsofTIinformationinTIdatabooks ordatasheetsispermissibleonlyifreproductioniswithoutalteration and isaccompaniedby allassociatedwarranties,conditions,limitations,and notices.TIisnotresponsibleorliableforsuch altered documentation.Informationofthirdpartiesmay be subjecttoadditionalrestrictions. ResaleofTIcomponents orserviceswithstatementsdifferentfromorbeyond theparametersstatedby TIforthatcomponent orservice voidsallexpressand any impliedwarrantiesfortheassociatedTIcomponent orserviceand isan unfairand deceptivebusinesspractice. TIisnotresponsibleorliableforany such statements. Buyeracknowledgesand agreesthatitissolelyresponsibleforcompliancewithalllegal,regulatoryand safety-relatedrequirements concerningitsproducts,and any use ofTIcomponents initsapplications,notwithstandingany applications-relatedinformationorsupport thatmay be providedby TI.Buyerrepresentsand agreesthatithas allthenecessaryexpertisetocreateand implementsafeguardswhich anticipatedangerousconsequencesoffailures,monitorfailuresand theirconsequences,lessenthelikelihoodoffailuresthatmightcause harm and takeappropriateremedialactions.BuyerwillfullyindemnifyTIand itsrepresentativesagainstany damages arisingoutoftheuse ofany TIcomponents insafety-criticalapplications. Insome cases,TIcomponents may be promotedspecificallytofacilitatesafety-relatedapplications.Withsuch components,TI’s goalisto helpenablecustomerstodesignand createtheirown end-productsolutionsthatmeet applicablefunctionalsafetystandardsand requirements.Nonetheless,such components aresubjecttotheseterms. No TIcomponents areauthorizedforuse inFDA ClassIII(orsimilarlife-criticalmedicalequipment)unlessauthorizedofficersoftheparties have executeda specialagreementspecificallygoverningsuch use. OnlythoseTIcomponents whichTIhas specificallydesignatedas militarygradeor“enhanced plastic”aredesignedand intendedforuse in military/aerospaceapplicationsorenvironments.Buyeracknowledgesand agreesthatany militaryoraerospaceuse ofTIcomponents whichhave not been so designatedissolelyattheBuyer's risk,and thatBuyerissolelyresponsibleforcompliancewithalllegaland regulatoryrequirementsinconnectionwithsuch use. TIhas specificallydesignatedcertaincomponents as meetingISO/TS16949 requirements,mainlyforautomotiveuse.Inany case ofuse of non-designatedproducts,TIwillnotbe responsibleforany failuretomeet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotiveand Transportationwww.ti.com/automotive Amplifiers amplifier.ti.com Communicationsand Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP ® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energyand Lighting www.ti.com/energy Clocksand Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space,Avionicsand Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Videoand Imaging www.ti.com/video RFID www.ti-rfid.com OMAP ApplicationsProcessors www.ti.com/omap TIE2E Community e2e.ti.com WirelessConnectivity www.ti.com/wirelessconnectivity MailingAddress:Texas Instruments,PostOfficeBox 655303,Dallas,Texas 75265 Copyright© 2013,Texas InstrumentsIncorporated

Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: SD021-3EVK SD021-5EVK