CLC021 NSC | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 18
Technical content
Features
n SMPTE 259M serial digital video standard compliant n Supports all NTSC and PAL standard component and composite serial video data rates n No external serial data rate setting or VCO filtering components required* n Fast VCO lock time:<75 µs at 270 Mbps n Built-in self-test (BIST) and video test pattern generator (TPG) with 16 internal patterns* n Automatic EDH character and flag generation and insertion per SMPTE RP 165 n Non-SMPTE mode operation as parallel-to-serial converter n NRZ-to-NRZI conversion control n HCMOS/LSTTL-compatible data and control inputs and outputs for CLC021AVGZ-5.0, LVCMOS for CLC021AVGZ-3.3 n 75Ω ECL-compatible, differential, serial cable-driver outputs n Single power supply operation: 5V (CLC021AVGZ-5.0) or 3.3V (CLC021AVGZ-3.3) in TTL or ECL systems n Low power: typically 235 mW n JEDEC 44-lead metric PQFP package n Commercial temperature range 0˚C to +70˚C * Patents applications made or pending.
Applications
n SMPTE 259M parallel-to-serial digital video interfaces for: — Video cameras — VTRs — Telecines — Video test pattern generators and digital video test equipment — Video signal generators n Non-SMPTE video applications n Other high data rate parallel/serial video and data CLC021 SMPTE 259M Digital Video Serializer with EDH Generation and Insertion © 2003 National Semiconductor Corporation DS101368 www.national.com
www.national.com 2
Order Number CLC021AVGZ-5.0 or CLC021AVGZ-3.3 See NS Package Number VGZ44A CLC021 www.national.com3
Absolute Maximum Ratings(Note 1) It is anticipated that this device will not be offered in a military qualified version. If Military/Aerospace speci- fied devices are required, please contact the National Semiconductor Sales Office / Distributors for availabil- ity and specifications. Supply Voltage (V DD−VSS): CLC021AVGZ-5.0V 6.0V CLC021AVGZ-3.3V 4.0V CMOS/TTL Input Voltage (V I): CLC021AVGZ-5.0V −0.5V to V DD+0.5V CLC021AVGZ-3.3V -0.3V to V DD+0.3V CMOS/TTL Output Voltage (VO): CLC021AVGZ-5.0V −0.5V to V DD+0.5V CLC021AVGZ-3.3V -0.3V to V DD+0.3V CMOS/TTL Input Current (single input): VI =V SS −0.5V: −5 mA VI =V DD +0.5V: +5 mA Input Current, Other Inputs: ±1m A CMOS/TTL Output Source/Sink Current: ±16 mA SDO Output Source Current: 22 mA Package Thermal Resistance θ JA 44-lead Metric PQFP: (@ 0 LFM airflow) 60˚C/W (@ 500 LFM airflow) 43˚C/W θJC 44-lead Metric PQFP: 17˚C/W Storage Temp. Range: −65˚C to +150˚C Junction Temperature: +150˚C Lead Temperature (Soldering 4 Sec): +260˚C ESD Rating (HBM): 2 kV ESD Rating (MM): 150V Transistor Count: 33,400 Recommended Operating Conditions Supply Voltage (VDD−VSS): CLC021AVGZ-5.0 5.0V ±10% CLC021AVGZ-3.3 3.3V ±10% CMOS/TTL Input Voltage: V SS to VDD Maximum DC Bias on SDO pins: CLC021AVGZ-5.0 3.0V ±10% CLC021AVGZ-3.3 1.3V ±10% PCLK Frequency Range 10 to 40MHz PCLK Duty Cycle 45 to 55% DN and PCLK Rise/Fall Time 1.0 to 3.0 ns Operating Free Air Temperature (TA): 0˚C to +70˚C Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3). Symbol Parameter Conditions Reference Min Typ Max Units VIH Input Voltage High Level All CMOS Inputs
2.0 V DD V
VIL Input Voltage Low Level V SS 0.8 V IIH Input Current High Level V IH =V DD +40 +60 µA IIL Input Current Low Level V IL =V SS -1 -20 µA VOH CMOS Output Voltage High Level IOH = −10 mA All CMOS Outputs 2.4 4.7 V DD V VOL CMOS Output Voltage Low Level IOL = +10 mA 0.0 0.3 V SS + 0.5V V VSDO Serial Driver Output Voltage RL =7 5Ω 1%, RREF = 1.69 kΩ 1%, Figure 2 SDO, SDO 700 800 900 mV P-P IDD Power Supply Current, Total RL =7 5Ω 1%, RREF = 1.69 kΩ 1%, PCLK = 27 MHz, NTSC Colour Bar Pattern, Figure 2 47 60 mA Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3). Symbol Parameter Conditions Reference Min Typ Max Units VIH Input Voltage High Level All CMOS Inputs VIL Input Voltage Low Level V SS 0.6 V IIH Input Current High Level V IH =V DD +22 +60 µA IIL Input Current Low Level V IL =V SS -1 -20 µA CLC021 www.national.com 4
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3). specifies acceptable device operating conditions. Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated referenced to VSS =0 V . Note 4: Specification is guaranteed by design. Note 5: RL =7 5Ω, AC-coupled@ 270 Mbps,R REF = 1.69 kΩ 1%, See Test Loadsand Figure 2. reference. Timing jitter measured with Tektronix VM700T using jitter measurement FFT mode, frame rate, 1 kHz filter bandwidth, Hanning window. Note 7: Measured from rising-edge of first PCLK cycle until Lock Detect output goes high (true). FIGURE 1. Test Loads
FIGURE 2. Test Circuit
CLC021 can serialize other 8- and 10-bit data. with a value between 3FCh and 3FFh to be forced to 3FFh.
- H, V, and F or Line/Field ID— For component video,
tered for the duration of the applicable field.
- NSP — New Sync Position: A function and output indi-
activated by a subsequent new or out-of-place TRS.
- ANC — Ancilliary data location output: Indicates that the
LOW. Non-SMPTE mode is enabled when this pin is HIGH. NSP outputs and TRS clipping are enabled. FIGURE 3. Setup and Hold Timing
Device Operation (Continued) NRZ-TO-NRZI CONVERTER The NRZ-to-NRZI converter accepts NRZ serial data from the SMPTE and EDH polynomial genertors and converts it to NRZI using the polynomial (X + 1) per SMPTE 259M, para- graph 5.2 and Annex C. The converter’s output goes to the output buffer amplifier. The NRZ/NRZI input enables this conversion function. Conversion from NRZ to NRZI is en- abled when the input is a logic LOW. Conversion to NRZI is disabled when this input is a logic-HIGH. This function is not affected by the SMPTE mode control input. The input pin is pulled internally to V SS (NRZI enabled) when unconnected. EDH SYSTEM OPERATION The CLC021 has EDH character and flag generation and insertion circuitry which operates as proposed in SMPTE RP-165. Inputs and circuitry are provided to control genera- tion and automatic insertion of the EDH check words at proper locations in the serial data output. The EDH polynomial generatorsaccept parallel data from the input register and generate 16-bit serial check words using the polynomial X 16 +X 12 +X 6 + 1. Separate calcula- tions are made for each video field prior to serialization. Separate CRCs for the full-field and active picture along with status flags are inserted and serially transmitted with the other data. Upon being reset, the initial state of all EDH check characters is 00h. The EDH controlsystem accepts input from the sync detec- tor and controls the EDH polynomial generator and SMPTE/ EDH polynomial insertion multiplexer.EDH Enable,a ne x - ternal TTL-compatible, low-true input, enables this circuitry. The controller inserts the EDH check words in the serial data stream at the correct positions in the ancilliary data space SMPTE RP-165. Ancilliary data space is formatted per SMPTE 291M. The EDH Force control input causes the insertion of new EDH checkwords and flags into the serial output regardless of the previous condition of EDH checkwords and flags in the input parallel data. This function may be used in situations where video content has been editted thus making the pre- vious EDH information invalid. The NTSC/PAL output indicates the type of component or composite data standard being input to the CLC021. This output is useful for troubleshooting or may be used to drive a panel indicator. The output is high when 625-line PAL data is being input and low when 525-line NTSC data is being input. PHASE-LOCKED LOOP AND VCO The phase-locked loop(PLL) system generates the output serial data clock at 10x the parallel data clock frequency. This system consists of a VCO, divider chain, phase- frequency detector and internal loop filter. The VCO free- running frequency is internally set. The PLL automatically generates the appropriate frequency for the serial clock rate using the parallel data clock (P CLK) frequency as its refer- ence. Loop filtering is internal to the CLC021. The VCO halts when no P CLK signal is present or is inactive. PCLK should be applied after power to the device. The VCO has separate VSSO and VDDO power supply feeds, pins 27 and 28, which may be supplied power via an external low-pass filter, if desired. The PLL acquisition (lock) time is less than 75 µs @ 270 Mbps. LOCK DETECT The lock detect output (pin 26) of the phase-frequency de- tector is a logic HIGH when the loop is locked. The output is CMOS/TTL-compatible and is suitable for driving other CMOS devices or an LED indicator. The Lock Detect pin reports the status of the PLL. When P CLK is lost, it will switch low at the event. SERIAL DATA OUTPUT BUFFER The current-mode serial data outputs provide low-skew complimentary or differential signals. The output buffer de- sign can drive 75Ω coaxial cables (AC-coupled) or 10K/100K ECL/PECL-compatible devices (DC-coupled). Output levels are 800 mV P-P ±10% into 75Ω AC-coupled, back-matched loads. The output level is 400 mV P-P ±10% when DC- coupled into 75Ω. (See Application Information for details.) The 75Ω resistors connected to the SDO outputs are back- matching resistors. No series back-matching resistors should be used. Output level is controlled by the value of R REF connected to pin 35. The value of RREF is normally 1.69 kΩ, ±1%. The output buffer is static when the device is in an out-of-lock condition. Separate V SSSD and VDDSD power feeds, pins, 37 and 40 are provided for the serial output driver. POWER-ON RESET AND RESET INPUT The CLC021 has an internally controlled, automatic,power- on-reset circuit. Reset clears TRS detection circuitry, all latches, registers, counters and polynomial generators, sets the EDH characters to 00h and disables the serial output. The SDO outputs are tri-stated during power-on reset. The part will remain in the reset condition until the parallel input clock is applied. An active-HIGH-true, manual reset input is available at pin 1. It resets both the digital and PLL blocks. The reset input has an internal pull-down device and is inactive when unconnected. It is recommended that P CLK not be asserted until at least 30 µs after power has reached VDDmin. See Figure 4.I f manual reset is used during power-on, then PCLK may be asserted at any time as long as manual reset is not de- asserted until V DDmin is reached. SeeFigure 5. CLC021 www.national.com9
TABLE 1. BIST and Test Pattern Generator Control Functions
12 D0 TPG Code Input LSB
13 D1 TPG Code Input
14 D2 TPG Code Input
15 D3 TPG Code Input MSB
29 TPG_EN TPG Enable, Active High True
TABLE 2. Component Video Test Pattern Selection
1 Reset Manual Reset Input (High True)
2 NRZ-NRZI
NRZ-to-NRZI Conversion Control (NRZ=High, NRZI=Low)
3 Test Out Test Out (BIST Pass/Fail Indicator)
SS Negative Power Supply Input (Digital Logic) 5V SS Negative Power Supply Input (Digital Logic) 6V DD Positive Power Supply Input (Digital Logic) 7V DD Positive Power Supply Input (Digital Logic)
8 EDH Force Force Insertion of New EDH and Flags in Serial Output Data (High True)
9 EDH Enable
EDH Enable Input (Low True)
10 SMPTE Mode SMPTE/non-SMPTE Mode Select Input (SMPTE Mode=Low)
11 N/C No Connect
12 D0 Parallel Data Input (Internal Pull-Down to V
SS)
13 D1 Parallel Data Input (Internal Pull-Down to V SS)
14 D2 Parallel Data Input (Internal Pull-Down to V SS)
15 D3 Parallel Data Input (Internal Pull-Down to V SS)
16 D4 Parallel Data Input (Internal Pull-Down to V SS)
17 D5 Parallel Data Input (Internal Pull-Down to V SS)
18 D6 Parallel Data Input (Internal Pull-Down to V SS)
19 D7 Parallel Data Input (Internal Pull-Down to V SS)
20 D8 Parallel Data Input (Internal Pull-Down to V SS)
21 D9 Parallel Data Input (Internal Pull-Down to V SS)
22 P CLK Parallel Clock Input (Internal Pull-Down to VSS)
23 H/Line-Field b0 (LSB) H-Bit Output (Component); Line-Field ID (Composite)
24 V/Line-Field b1 V-Bit Output (Component); Line-Field ID (Composite)
25 F/Line-Field b2 (MSB) F-Bit Output (Component); Line-Field ID (Composite)
26 Lock Detect Lock Detector Output (High True)
SSO Negative Power Supply Input (PLL Supply)
28 V DDO Positive Power Supply Input (PLL Supply)
29 TPG Enable TPG Enable (High True)
SSOD Negative Power Supply Input (PLL Digital Supply)
31 V SSOD Negative Power Supply Input (PLL Digital Supply)
32 V DDOD Positive Power Supply Input (PLL Digital Supply)
33 V DDOD Positive Power Supply Input (PLL Digital Supply)
34 N/C No Connect
REF Output Level Reference Resistor (1.69 kΩ, 1% Nominal Value)
36 V DDOD Positive Power Supply Input (PLL Digital Supply)
37 V SSSD Negative Power Supply Input (Output Driver)
38 SDO Serial Data True Output
39 SDO
Serial Data Complement Output
40 V DDSD Positive Power Supply Input (Output Driver)
41 Sync Detect Enable Parallel Data Sync Detection Enable Input (Low True)
42 NSP New Sync Position Output
43 ANC Ancilliary Data Header Flag Output
44 NTSC/PAL
NTSC/PAL Mode Indicator Output (PAL=High, NTSC=Low) Note: All CMOS/TTL inputs have internal pull-down devices. CLC021 www.national.com13
than 5 kΩ so as not to affect Lock Detect indicator operation. obtained using the video test equipment. Connect LOCK DETECT to TPG ENABLE for test pattern generator function. Remove RP1 & RP3 and replace RP2 & RP4 with 50Ω resistor packs for coax interfacing. Install RP1-4 when using ribbon cable for input interfacing. This board is designed for use with TTL power supplies only. FIGURE 9. SD021EVK Schematic Diagram
the device’s three separate power feed systems. FIGURE 12. Jitter Plots
Physical Dimensions inches (millimeters) unless otherwise noted 44-Pin Metric PQFP Order Number CLC021AVGZ-5.0 or CLC21AVGZ-3.3 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com CLC021 SMPTE 259M Digital Video Serializer with EDH Generation and Insertion National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.