CLC020 TI1 | Alldatasheet

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www.ti.com SNLS046E –FEBRUARY 2000–REVISED APRIL 2013 CLC020SMPTE259MDigitalVideoSerializerwithIntegratedCableDriver Check forSamples: CLC020 1FEATURES DESCRIPTION The CLC020 SMPTE 259M DigitalVideo Serializer 2• SMPTE 259M SerialDigitalVideo Standard withIntegratedCable Driverisa monolithicintegratedCompliant circuitthat encodes, serializesand transmitsbit-• No ExternalSerialData Rate Settingor VCO paralleldigitaldataconformingtoSMPTE 125M and FilteringComponents Required(1) SMPTE 267M component videoand SMPTE 244M composite video standards.The CLC020 can also• Built-InSelf-Test(BIST)and Video TestPattern serializeother8 or 10-bitparalleldata.The CLC020Generator(TPG) with16 InternalPatterns(1) operatesatdataratesfrom below 100 Mbps toover• Supports AllNTSC and PAL Standard 400 Mbps. The serialdata clock frequency isComponent and Composite SerialVideo Data internallygenerated and requires no externalRates frequencysettingcomponents,trimmingor filtering*.

  • HCMOS/TTL-Compatible Data and Control Functionsperformedby theCLC020 include:parallel- to-serialdata conversion,data encoding using theInputsand Outputs polynomial(X9+X4+1),data formatconversionfrom• 75Ω ECL-Compatible,Differential,SerialCable- NRZ to NRZI, paralleldata clock frequencyDriverOutputs multiplicationand encodingwiththe serialdata,and
  • FastVCO Lock Time: <75 µs coaxialcabledriving.Inputforsync (TRS) detection disablingand a PLL lockdetectoutputare provided.• Single+5V TTL or −5V ECL Supply Operation The CLC020 has an exclusivebuilt-inself-test(BIST)• Low Power: 235 mW Typical and video test patterngenerator(TPG) with 4• 28-Lead PLCC Package component videotestpatterns,referenceblack,PLL
  • Commercial Temperature Range 0°C to+70°C and EQ pathologicalsand modifiedcolourbars,in4:3 and 16:9 rasterand both NTSC and PAL formats*. Separatepower pinsforthe outputdriver,VCO andAPPLICATIONS the digitallogicimprove power supply rejection,• SMPTE 259M Parallel-to-SerialDigitalVideo outputjitterand noiseperformance.Interfacesfor: The CLC020 is the ideal complement to the– Video Cameras CLC011B SMPTE 259M Serial DigitalVideo – VTRs Decoder, CLC014 ActiveCable Equalizer,CLC016 Data RetimingPLL (clock-dataseparator),CLC018– Telecines 8X8 DigitalCrosspointSwitch and CLC006 or– Video TestPatternGeneratorsand Digital CLC007 Cable Drivers,fora completeparallel-serial-Video TestEquipment parallel, high-speed data processing and
  • Non-SMPTE Video Applications transmissionsystem.
  • Other High Data Rate Parallel/SerialVideo and The CLC020 is powered from a single5V supply.Data Systems Power dissipationistypically235 mW includingtwo 75Ω back-matched output loads. The device is packaged ina JEDEC 28-leadPLCC. (1) PatentsApplicationsMade orPending. TYPICAL APPLICATION Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2000–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNLS046E –FEBRUARY 2000–REVISED APRIL 2013 www.ti.com BLOCK DIAGRAM CONNECTION DIAGRAM Figure1. 28-PinPLCC See Package Number FN0028A

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www.ti.com SNLS046E –FEBRUARY 2000–REVISED APRIL 2013 These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. ABSOLUTE MAXIMUM RATINGS (1)(2) SupplyVoltage(VDD −VSS ) 6.0V CMOS/TTL InputVoltage(VI) −0.5Vto(VDD + 0.5V) CMOS/TTL OutputVoltage(VO ) −0.5Vto(VDD + 0.5V) CMOS/TTL InputCurrent(singleinput) VI= VSS −0.5V −5 mA VI= VDD +0.5V +5 mA InputCurrent,OtherInputs ±1 mA CMOS/TTL OutputSource/SinkCurrent ±10 mA SDO OutputSourceCurrent 20 mA Package ThermalResistance θJA 28-leadPLCC 85°C/W θJC 28-leadPLCC 35°C/W StorageTemp. Range −65°C to+150°C JunctionTemperature +150°C Lead Temperature(Soldering4 Sec) +260°C ESD Rating(HBM) >2.5kV ESD Rating(MM) >200 V TransistorCount 33,400 (1) AbsoluteMaximum Ratingsarethoseparametervaluesbeyond whichthelifeand operationofthedevicecannotbe ensured.The statinghereinofthesemaximums shallnotbe construedtoimplythatthedevicecan orshouldbe operatedatorbeyond thesevalues. The tableofElectricalCharacteristicsspecifiesacceptabledeviceoperatingconditions. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. RECOMMENDED OPERATING CONDITIONS SupplyVoltage(VDD −VSS ) 5.0V±10% CMOS/TTL InputVoltage VSS toVDD PCLK FrequencyRange 10 to40MHz PCLK DutyCycle 45 to55% D N and PCLK Rise/FallTime 1.0to3.0ns Maximum DC Biason SDO pins 3.0V±10% OperatingFreeAirTemperature(TA) 0°C to+70°C Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:CLC020

SNLS046E –FEBRUARY 2000–REVISED APRIL 2013 www.ti.com DC ELECTRICAL CHARACTERISTICS Over SupplyVoltageand OperatingTemperatureranges,unlessotherwisespecified.(1)(2) Symbol Parameter Conditions Reference Min Typ Max Units VIH InputVoltageHighLevel D0 throughD9, 2.0 VDD V PCLK ,TPG_ENVIL InputVoltageLow Level VSS 0.8 Vand Sync. IIH InputCurrentHighLevel VIH = VDD +40 +60 µADetectEnable IIL InputCurrentLow Level VIL= VSS -1 -20 µA VOH CMOS OutputVoltage IOH = −10 mA Lock Detect, 2.4 4.7 VDD V HighLevel TestOut VOL CMOS OutputVoltageLow IOL = +10 mA 0.0 0.3 VSS + 0.5V V Level VSDO SerialDriverOutput R L = 75Ω 1%, SDO, SDO 700 800 900 mV P-P Voltage R REF = 1.69kΩ 1%, See Figure3 IDD Power SupplyCurrent, R L = 75Ω 1%, 47 60 mA Total R REF = 1.69kΩ 1%, PCLK = 27 MHz, See Figure3, NTSC ColourBar Pattern (1) Currentflowintodevicepinsisdefinedas positive.Currentflowoutofdevicepinsisdefinedas negative.Allvoltagesarestated referencedtoVSS = 0V. (2) TypicalvaluesarestatedforVDD = +5.0V and TA = +25°C. AC ELECTRICAL CHARACTERISTICS Over SupplyVoltageand OperatingTemperatureranges,unlessotherwisespecified.(1) Symbol Parameter Conditions Reference Min Typ Max Units BR SDO Serialdatarate R L = 75Ω,AC coupled(2) SDO, SDO 100 400 Mbps FPCLK ReferenceClock PCLK 10 40 MHzInputFrequency ReferenceClockDuty PCLK 45 50 55 %Cycle tr,tf Risetime,Falltime 10% –90% D N ,PCLK 1.0 1.5 3.0 ns tj Serialoutputjitter 270 Mbps (3),See Figure3 220 psP-P tjit Serialoutputjitter See (4)(2) 100 200 psP-P SDO, SDO tr,tf Risetime,Falltime 20% –80% (2)(4) 500 800 1500 ps Outputovershoot 1 % tLOCK Lock time 270 Mbps (2)(5) 75 µs tSU Setuptime See Figure4 D N toPCLK 3 2 ns tHLD Holdtime See Figure4 D N fromPCLK 1.5 1 ns LGEN Outputinductance See (4) 6 nH SDO, SDO R GEN Outputresistance See (4) 25k Ω (1) TypicalvaluesarestatedforVDD = +5.0V and TA = +25°C. (2) R L = 75Ω,AC-coupled@ 270 M bps,R REF = 1.69kΩ 1%, See TEST LOADS and Figure3. (3) CLC020 mounted intheSD020EVK board,configuredinBIST mode (NTSC colorbars)withPCLK = 27MHz derivedfromTektronix TG2000 black-burstreference.Timingjittermeasured withTektronixVM700T usingjittermeasurement FFT mode, framerate,1kHz filterbandwidth,Hanningwindow. (4) Specificationisensuredby design. (5) Measured fromrising-edgeoffirstPCLK cycleuntilLock Detectoutputgoes high(true).

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www.ti.com SNLS046E –FEBRUARY 2000–REVISED APRIL 2013 TEST LOADS AllresistorsinOhms, 1% tolerance. Figure2. TestLoads Figure3. TestCircuit Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:CLC020

SNLS046E –FEBRUARY 2000–REVISED APRIL 2013 www.ti.com TIMING DIAGRAM Figure4. Setup and Hold Timing DEVICE OPERATION The CLC020 SMPTE 259M DigitalVideo Serializerisused indigitalvideosignaloriginationand processing equipment:cameras, video tape recorders,telecines,video testequipment and others.Itconvertsparallel component or compositedigitalvideosignalsintoserialformat.Logiclevelswithinthisequipmentare normally TTL-compatibleas produced by CMOS or bipolarlogicdevices.The encoder outputsECL-compatibleserial digitalvideo(SDV) signalsconformingtoSMPTE 259M-1997.The CLC020 operatesatallstandardSMPTE and ITU-R paralleldatarates. VIDEO DATA PROCESSING CIRCUITS The inputdata registeraccepts8 or10-bitparalleldataand clocksignalshavingCMOS/TTL-compatiblesignal levels.Paralleldatamay conformtoany ofseveralstandards:SMPTE 125M, SMPTE 267M, SMPTE 244M or ITU-R BT.601.Ifdatais8-bit,itisconvertedtoa 10-bitrepresentationaccordingtothetypeofdatabeinginput: component 4:2:2per SMPTE 259M paragraph7.1.1,compositeNTSC per paragraph8.1.1or compositePAL per paragraph9.1.1.Output from thisregisterfeeds the SMPTE polynomialgenerator/serializerand sync detector.AllCMOS inputsincludingthePCLK inputhave internalpull-downdevices. The sync detectoror TRS characterdetectoracceptsdata from the inputregister.The detectionfunctionis controlledby Sync DetectEnable,a low-true,TTL-compatible,externalsignal.Synchronizationwords,thetiming referencesignals(TRS),start-of-active-video(SAV) and end-of-active-video(EAV) aredefinedinSMPTE 125M- 1995 and 244M. The sync detectorsuppliescontrolsignalstotheSMPTE polynomialgeneratorthatidentifythe presenceofvalidvideodata.The sync detectorperformsinputTRS characterLSB-clippingas prescribedinITU- R-BT.601.LSB-clippingcauses allTRS characterswitha valuebetween 000h and 003h tobe forcedto000h and allTRS characterswitha valuebetween 3FCh and 3FFh to be forcedto 3FFh. Clippingisdone priorto encoding. The SMPTE polynomialgeneratoracceptstheparallelvideodataand encodes itusingthepolynomialX9+X4+1 as specifiedinSMPTE 259M –1997,paragraph5 and Annex C. The scrambleddataisthenserializedforoutput. The NRZ-to-NRZI converteracceptsserialNRZ datafrom theSMPTE polynomialgenertorand convertsitto NRZI usingthe polynomialX + 1 per SMPTE 259M –1997, paragraph5.2 and Annex C. The transmissionbit orderisLSB first,perparagraph6.The converter'soutputfeedstheoutputdriveramplifier. PHASE-LOCKED LOOP AND VCO The phase-locked loop (PLL) system generatesthe outputserialdata clockat 10× the paralleldata clock frequency.Thissystem consistsofa VCO, dividerchain,phase-frequencydetectorand internalloopfilter.The VCO free-runningfrequencyisinternallyset.The PLL automaticallygeneratestheappropriatefrequencyforthe serialclockrateusingtheparalleldataclock(PCLK ) frequencyas itsreference.Loop filteringisinternaltothe CLC020. The VCO has separateVSSO and VDDO power supplyfeeds,pins15 and 16,which may be supplied power independentlyviaan externallow-passfilter,ifdesired.The PLL acquisition(lock)timeislessthan75 µs @ 270 Mbps.

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10% PCLK VDD 30Ps min CLC020 www.ti.com SNLS046E –FEBRUARY 2000–REVISED APRIL 2013 LOCK DETECT The Lock Detect outputof the phase-frequencydetectorindicatesthe PLL lockcondition.Itisa logicHIGH when theloopislocked.The outputisCMOS/TTL-compatibleand issuitablefordrivingotherCMOS devicesor a LED indicator. SERIAL DATA OUTPUT BUFFER The current-modeserialdata outputsprovidelow-skewcomplimentaryordifferentialsignals.The outputbuffer designcan drive75Ω coaxialcables(AC-coupled)or 10k/100kECL/PECL-compatibledevices(DC-coupled). Outputlevelsare 800 mV P-P ±10% into75Ω AC-coupled,back-matchedloads.The outputlevelis400 mV P-P ±10% when DC-coupledinto75Ω (See APPLICATION INFORMATION fordetails).The 75Ω resistorsconnected totheSDO outputsareback-matchingresistors.No seriesback-matchingresistorsshouldbe used.SDO output levelsarecontrolledby thevalueofR REF connectedtopin19.The valueofR REF isnormally1.69kΩ,±1%. The outputbufferisstaticwhen thedeviceisinan out-of-lockcondition.SeparateVSSSD and VDDSD power feeds,pins 21 and 24,areprovidedfortheserialoutputdriver. POWER-ON RESET The CLC020 has an internallycontrolled,automatic,power-on resetcircuit.ThiscircuitclearsTRS detection circuitry,alllatches,registers,countersand polynomialgeneratorsand disablesthe serialoutput.The SDO outputsare tri-statedduringpower-on reset.The partwillremain inthe resetconditionuntilthe parallelinput clockisapplied. Itisrecommended thatPCLK notbe asserteduntilatleast30 µs afterpower has reachedVDD min.See Figure5. Figure5. Power-On Reset Sequence BUILT-INSELF-TEST (BIST) The CLC020 has a built-inself-test(BIST)function.The BIST performsa comprehensivego-no-gotestofthe device.The testuses eithera full-fieldcolorbarforNTSC ora PLL pathologicalforPAL as thetestdatapattern. Data isinputinternallyto the inputdata register,processedthroughthe deviceand testedforerrors.Table 1 givesdevicepinfunctionsand Table 2 givesthe testpatterncodes used forthisfunction.The signallevelat Test_Output,pin26,indicatesa pass orfailcondition. The BIST isinitiatedby applyingthecode forthedesiredBIST toD0 throughtD3 (D9 throughD4 are00h)and a 27 MHz clockatthePCLK input.Sinceallparalleldatainputsareequippedwithan internalpull-downdevice,only thoseinputsD0 throughD3 whichrequirea logic-1need be pulledhigh.AftertheLock_Detectoutputgoes high (true)indicatingtheVCO islockedon frequency,TPG_Enable, pin17,isthentakentoa logichigh.TPG_Enable may be temporarilyconnectedto the Lock_Detectoutputto automate BIST operation.Test_Output,pin26, is monitoredfora pass/failindication.Ifno errorshave been detected,thisoutputwillgo to a logichighlevel approximately2 fieldintervalsafterTPG_Enable istaken high.Iferrorshave been detectedin the internal circuitryoftheCLC020, Test_Outputwillremainlow untilthetestisterminated.The BIST isterminatedby taking TPG_Enable toa logiclow.Continuousserialdataoutputisavailableduringthetest. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:CLC020

SNLS046E –FEBRUARY 2000–REVISED APRIL 2013 www.ti.com TEST PATTERN GENERATOR The CLC020 featuresan on-boardtestpatterngenerator(TPG).Four full-fieldcomponent videotestpatterns forbothNTSC and PAL standards,and 4x3 and 16x9 rastersizesareproduced.The testpatternsare:flat-field black,PLL pathological,equalizer(EQ) pathologicaland a modified75%, 8-colorverticalbar pattern.The pathologicalsfollowrecommendationscontainedin SMPTE RP 178–1996 regardingthe testdata used. The colorbarpatterndoes notincorporatebandwidthlimitingcodinginthechroma and luma datawhen transitioning between thebars.Forthisreason,itmay notbe suitableforuse as a visualtestpatternorforinputtovideoD-to- A conversiondevicesunlessmeasures aretakentorestricttheproductionofout-of-bandfrequencycomponents. The TPG isoperatedby applyingthe code forthe desiredtestpatternto D0 throughD3 (D4 throughD9 are 00h).Sinceallparalleldatainputsareequippedwithan internalpull-downdevice,onlythoseinputsD0 through D3 whichrequirea logic-1need be pulledhigh.Next,applya 27 or36 MHz signal,appropriatetotherastersize desired,at the PCLK inputand waituntilthe Lock_Detectoutputgoes trueindicatingthe VCO islockedon- frequency.Then, takeTPG_Enable, pin17, to a logichigh.The serialtestpatterndata appears on the SDO outputs.TPG_Enable may be temporarilyconnectedtotheLock_DetectoutputtoautomateTPG operation.The TPG mode isexitedby takingTPG_Enable to a logiclow.Table 1 givesdevicepinfunctionsforthismode. Table2 givestheavailabletestpatternsand selectioncodes. Figure6. Built-InSelf-TestControlSequence Figure7. TestPatternGeneratorControlSequence

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www.ti.com SNLS046E –FEBRUARY 2000–REVISED APRIL 2013 Table1.BIST and TestPatternGeneratorControl Functions Pin Name Function

3 D0 TPG code inputLSB

4 D1 TPG code input

5 D2 TPG code input

6 D3 TPG code inputMSB

17 TPG_EN TPG Enable,activehightrue

26 Test_Out BIST Pass/Failoutput.Pass=High (See text fortimingrequirements) Table2.Component Video TestPatternSelection(1) Standard Frame TestPattern D3 D2 D1 D0 NTSC 4x3 Flat-fieldblack 0 0 0 0 NTSC 4x3 PLL pathological 0 0 0 1 NTSC 4x3 EQ pathological 0 0 1 0 NTSC 4x3 Colorbars,75%, 8-bars(modified,see text),BIST 0 0 1 1 PAL 4x3 Flat-fieldblack 0 1 0 0 PAL 4x3 PLL pathological,BIST 0 1 0 1 PAL 4x3 EQ pathological 0 1 1 0 PAL 4x3 Colorbars,75%, 8-bars(modified,see text) 0 1 1 1 NTSC 16x9 Flat-fieldblack 1 0 0 0 NTSC 16x9 PLL pathological 1 0 0 1 NTSC 16x9 EQ pathological 1 0 1 0 NTSC 16x9 Colorbars,75%, 8-bars(modified,see text) 1 0 1 1 PAL 16x9 Flat-fieldblack 1 1 0 0 PAL 16x9 PLL pathological 1 1 0 1 PAL 16x9 EQ pathological 1 1 1 0 PAL 16x9 Colorbars,75%, 8-bars(modified,see text) 1 1 1 1 (1) D9 throughD4 = 0 (binary) Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:CLC020

SNLS046E –FEBRUARY 2000–REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (1) Pin # Name Description

1 VDD Positivepower supplyinput(digitallogic)

2 VDD Positivepower supplyinput(digitallogic)

3 D0 Paralleldatainput/Testpatternselect(LSB)

4 D1 Paralleldatainput/Testpatternselect

5 D2 Paralleldatainput/Testpatternselect

6 D3 Paralleldatainput/Testpatternselect(MSB)

7 D4 Paralleldatainput

8 D5 Paralleldatainput

9 D6 Paralleldatainput

10 D7 Paralleldatainput

11 D8 Paralleldatainput

12 D9 Paralleldatainput

13 PCLK Parallelclockinput

14 Lock Detect VCO Lock Detectoutput(high-true)

15 VSSO Negativepower supplyinput(PLL supply)

16 VDDO Positivepower supplyinput(PLL supply)

17 TPG_EN TestPatternGenerator(TPG) Enableinput(high-true)

18 VSSOD Negativepower supplyinput(PLL digitalsupply)

19 R REF Outputdriverlevelcontrol

20 VDDOD Positivepower supplyinput(PLL digitalsupply)

21 VSSSD Negativepower supplyinput(Outputdriver)

22 SDO Serialdatatrueoutput

23 SDO Serialdatacomplement output

24 VDDSD Positivepower supplyinput(Outputdriver)

25 Sync DetectEnable Paralleldatasyncdetectionenableinput(lowtrue)

26 Test_Out BIST Pass/Failoutput

27 VSS Negativepower supplyinput(digitallogic)

28 VSS Negativepower supplyinput(digitallogic)

(1) AllCMOS/TTL inputshave internalpull-downdevices.

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APPLICATION INFORMATION

A typicalapplicationcircuitfortheCLC020 isshown inFigure8.Thiscircuitdemonstratesthecapabilitiesofthe CLC020 and allowsitsevaluationina varietyofconfigurations.An assembled demonstrationboard withmore comprehensiveevaluationoptionsisavailable,partnumber SD020EVK. The boardmay be orderedthroughany of Texas Instruments'ssalesoffices.Complete circuitboard layoutsand schematics,forthe SD020EVK are availableon Texas Instruments'WEB siteintheapplicationinformationforthisdevice. APPLICATION CIRCUIT Figure8. TypicalApplicationCircuit Severaldifferentinputand outputdriveand loadingoptionscan be constructedon theSD020EVK application circuitboard,Figure9. Pin headers are providedforinputcablingand controlsignalaccess.The appropriate valueresistorpacks,220 and 330Ω forTTL or50Ω forsignalsourcesrequiringsuch loading,shouldbe installed atRP1-4 beforeapplyinginputsignals. The board'soutputsmay be DC interfacedto PECL inputsby firstinstalling124Ω resistorsat R1B and R2B, changingR1A and R2A to187Ω and replacingC1 and C2 withshortcircuits.The PECL inputsshouldbe directly connectedtoJ1 and J2 withoutcabling.If75Ω cablingisused toconnecttheCLC020 tothePECL inputs,the voltagedividersused on theCLC020 outputsmust be removed and re-installedon thecircuitboard where the PECL deviceismounted.Thiswillprovidecorrectterminationforthecableand biasingforboththeCLC020's outputsand thePECL inputs.Itismost importanttonotethata 75Ω or equivalentDC loading(measured with respectto the negativesupplyrail)must always be installedat both of the CLC020's SDO outputsto obtain propersignallevelsfromdevice.When using75Ω Thevenin-equivalentloadcircuits,theDC biasappliedtothe SDO outputsshouldnot exceed +3V withrespectto the negativesupplyrail.Serialoutputlevelsshouldbe reducedto400 mV p-p by changingR REF to3.4kΩ. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:CLC020

SNLS046E –FEBRUARY 2000–REVISED APRIL 2013 www.ti.com The TestOut outputisintendedformonitoringby equipmentpresentinghighimpedance loading(>500Ω).When monitoringtheLock Detectoutput,theattachedmonitoringcircuitshouldpresenta DC resistancegreaterthan5 kΩ so thatLock Detectindicatoroperationisnotaffected. ConnectLOCK DETECT toTPG ENABLE fortestpatterngeneratorfunction. Remove RP1 & RP3 and replaceRP2 & RP4 with50Ω resistorpacksforcoax interfacing. InstallRP1-4 when usingribboncableforinputinterfacing. Thisboardisdesignedforuse withTTL power suppliesonly. ForoptionalECL compatibleload:R1A = R2A = 187;R1B = R2B = 124. Allresistances& impedancesinOhms. Valueswith3 significantdigitsare1%; with2 digits5%. Figure9. SD020EVK Schematic Diagram MEASURING JITTER The testmethod used toobtainthetimingjittervaluegivenintheAC ElectricalSpecificationtableisbased on proceduresand equipmentdescribedinSMPTE RP 192-1996.The recommended practicediscussesseveral methods and indicatordevices.An FFT method performedby standardvideotestequipmentwas used toobtain thedatagiveninthisdatasheet.As such,thejittercharacteristics(orjitterfloor)ofthemeasurement equipment, particularlythemeasurement analyzer,become integraltotheresultingjittervalue.The method and equipment were chosen so thatthetestcan be easilyduplicatedby thedesignengineerusingmost standarddigitalvideo testequipment.Inso doing,similarresultsshouldbe achieved.The intrinsicjitterflooroftheCLC020's PLL is approximately25% of the typicaljittergiven in the electricalspecifications.In production,device jitteris measured on automaticIC testequipment(ATE) usinga differentmethod compatiblewiththatequipment.Jitter measured usingthisATE yieldsvaluesapproximately50% ofthoseobtainedusingthevideotestequipment.

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www.ti.com SNLS046E –FEBRUARY 2000–REVISED APRIL 2013 The jittertestsetupused toobtainvaluesquotedinthedatasheetconsistsof:

  • Texas InstrumentsSD020EVK, CLC020 evaluationkit
  • TektronixTG2000 signalgenerationplatformwithDVG1 option
  • TektronixVM700T Option1S VideoMeasurement Set
  • TektronixTDS 794D, OptionC2 oscilloscope
  • TektronixP6339A passiveprobe
  • 75 Ohm coaxialcable,3ft.,Belden8281 orRG59 (2required)
  • ECL-to-TTL/CMOS levelconverter/amplifier,Figure11 Applytheblack-burstreferenceclockfromtheTG2000 signalgenerator'sBG1 module 27MHz clockoutputtothe levelconverterinput.The clockamplitudeconverterschematicisshown in Figure10. Adjustthe inputbias controlto givea 50% duty cycleoutputas measured on the oscilloscope/probesystem.Connect the level translatortotheSD020EVK board,connectorP1, PCLK pins(theouter-mostrow ofpinsisground).Configurethe SD020EVK to operatein the NTSC colourbars,BIST mode. Configurethe VM700T to make the jitter measurement inthejitterFFT mode attheframeratewith1kHz filterbandwidthand Hanning window.Configure the setupas shown inFigure10. Switchthe testequipmenton (fromstandbymode) and allowallequipment temperaturesstabilizeper manufacturer'srecommendation. Measure the jittervalue afterallowingthe instrument'sreadingtostabilize(about1 minute).ConsulttheVM700T VideoMeasurement Set Option1S Serial DigitalMeasurements User Manual (documentnumber 071-0074-00)fordetailsofequipmentoperation. The VM700T measurement system'sjitterfloorspecificationat270Mbps isgivenas 200ps ±20% (100ps±5% typical)ofactualcomponents from 50Hz to1MHz and 200ps +60%, -30% ofactualcomponents from 1MHz to 10MHz. To obtainthe actualresidualjitterof the CLC020, a root-sum-squareadjustmentof the jitterreading must be made to compensate forthe measurement system'sjitterfloorspecification.For example,ifthe jitter readingis250ps,theCLC020 residualjitteristhesquarerootof(2502 − 2002)= 150ps.The accuracylimitsof thereadingas givenabove apply. Figure10. JitterTestCircuit Figure11. ECL-to-TTL/CMOS levelconverter/amplifer Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:CLC020

SNLS046E –FEBRUARY 2000–REVISED APRIL 2013 www.ti.com Figure12. JitterPlots PCB LAYOUT AND POWER SYSTEM BYPASS RECOMMENDATIONS Circuitboardlayoutand stack-upfortheCLC020 shouldbe designedtoprovidenoise-freepower tothedevice. Good layoutpracticealsowillseparatehighfrequencyor highlevelinputsand outputsto minimizeunwanted straynoisepickup,feedbackand interference.Power systemperformancemay be greatlyimprovedby usingthin dielectrics(4to10 mils)forpower/groundsandwiches.ThisincreasestheintrinsiccapacitanceofthePCB power system which improves power supply filtering,especiallyat high frequencies,and makes the value and placementofexternalbypass capacitorslesscritical.Externalbypass capacitorsshouldincludebothRF ceramic and tantalumelectrolytictypes.RF capacitorsmay use valuesin the range 0.01 µF to 0.1 µF. Tantalum capacitorsmay be intherange2.2µF to10 µF.Voltageratingfortantalumcapacitorsshouldbe atleast5× the power supplyvoltagebeingused.Itisrecommended practicetouse two viasateach power pinoftheCLC020 as wellas allRF bypass capacitorterminals.Dual viasreducetheinterconnectinductanceby up tohalf,thereby reducinginterconnectinductanceand extendingtheeffectivefrequencyrangeofthebypasscomponents.

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www.ti.com SNLS046E –FEBRUARY 2000–REVISED APRIL 2013 The outerlayersof the PCB may be floodedwithadditionalVSS (ground)plane.These planeswillimprove shieldingand isolationas wellas increasetheintrinsiccapacitanceofthepower supplyplanesystem.Naturally, tobe effective,theseplanesmust be tiedtotheVSS power supplyplaneatfrequentintervalswithvias.Frequent viaplacementalsoimprovessignalintegrityon signaltransmissionlinesby providingshortpaths forimage currentswhich reduces signaldistortion.The planesshouldbe pulledback from alltransmissionlinesand component mountingpads a distanceequaltothewidthofthewidesttransmissionlineor thethicknessofthe dielectricseparatingthetransmissionlinefromtheinternalpower orgroundplane(s)whicheverisgreater.Doing so minimizeseffectson transmissionlineimpedances and reduces unwanted parasiticcapacitancesat component mountingpads. Inespeciallynoisypower supplyenvironments,such as isoftenthecase when usingswitchingpower supplies, separatefilteringmay be used attheCLC020's VCO and outputdriverpower pins.The CLC020 was designed forthissituation.The digitalsection,VCO and outputdriverpower supplyfeeds are independent(see PIN DESCRIPTIONS tableand PinoutDrawing fordetails).Supply filteringmay takethe form of L-sectionor pi- section,L-C filtersinserieswiththeseVDD inputs.Such filtersare availableina singlepackage from several manufacturers.Despitebeingindependentfeeds,alldevicepower suppliesshouldbe appliedsimultaneouslyas from a common source.The CLC020 is freefrom power supplylatch-upcaused by circuit-induceddelays between thedevice'sthreeseparatepower feedsystems. REPLACING THE GENNUM GS9022 The CLC020 is form-fit-functioncompatiblewith the Gennum GS9022. The CLC020 can improve the performanceofGS9022 applicationsusingtheexistingPCB layoutwiththeremovalofcertaincomponents or changes to component values.New layoutsusingthe CLC020 willbenefitfrom the greatlyreduced ancilliary component countand more compact layout. The CLC020 does notrequireexternalVCO filteringcomponents.The externalVCO filteringcomponents atpin 17 of the GS9022 may remain connectedto the CLC020 withoutcomplications.Itissuggestedthatthesebe removed fromthecircuitboard.The CLC020 uses pin17 foritstestpatterngeneratorenablefunction.You will findtheTPG functionveryusefulwhen you make thischange. Remove the C OSC capacitorused by the GS9022 at pin26. The CLC020 uses pin26 as the BIST pass/fail indicatoroutput.You may attacha LED as an indicatortothispin,ifdesired.LED currentshouldbe limitedto10 mA maximum. The same LED typeand currentlimitingresistorshown inFigure9 attheLock Detectoutputmay be used forthisindicatorfunction. Remove any capacitorattachedtopin19.A capacitorattachedtopin19 willcause distortionoftheoutputVOH level.The formerdata ratesettingresistor,R VCO , at pin19 now functionsas the outputlevelsettingresistor, R REF .Itmust be changed toa 1.69kΩ,1% valueforcorrectoutputlevelsetting. The inputseriesresistorsand the PCLK risetimefiltercapacitorused withthe GS9022 are not needed forthe CLC020. These components shouldbe removed from the circuitboard and the resistorsreplacedby short circuits(0Ω resistors).These seriesresistorswillincreaseinputsignalriseand falltimesiflefton theboard. The CLC020 has current-modeserialcabledriveroutputs.These outputshave very high internalgenerator resistanceas one would expect of a currentsource.Though these current-modeoutputscan produce the equivalentdrivevoltagesintotheload,itisnecessarytochange and simplifythetypicalGS9022 outputcircuit normallyrecommended forthatdevice.The outputloadresistorsatpins22 and 23 must be changed to75Ω,1% values.These resistorsbecome the back-matchingloadsacrosswhich the CLC020's outputsdevelopdrive voltage.The seriesback-matchingresistorsused on the GS9022 shouldbe removed and replacedwithshort circuits.The risetimecompensatingcapacitorsacrosstheseresistorsshouldbe removed. Pin28 on theCLC020 isVSS and must be connectedtothenegativesupplyorground.On layoutsdesignedto mount the GS9022, the seriesR-C networkconnectedto thispin shouldbe replacedby shortcircuits(0Ω resistors).The pull-upresistorconnectedto the Lock Detectoutput,pin 14, shouldbe removed. Itmay be replacedby a LED and currentlimitingresistorconnectedtoVSS ifa visuallockindicatorisdesired. The CLC020 has an internalpull-downattheSync DetectEnableinputand may be leftunconnectedinSMPTE video-onlyapplications. The CLC020 has independentpower supplypinsfortheVCO, VSSO ,pin15 and VDDO ,pin16.The CLC020 has an outputdrivernegativesupply,VSSSD ,atpin21.The outputdriverpositivesupply,VDDSD ,ispin24 (ason the GS9022).On new layouts,additionalpower supplyfilteringmay be added atthesepins,ifdesired. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:CLC020

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www.ti.com 12-Jul-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CLC020BCQ/NOPB ACTIVE PLCC FN 28 35 Green (RoHS & no Sb/Br) CU SN Level-2A-245C-4 WEEK 0 to 70 CLC020BCQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 12-Jul-2014 Addendum-Page 2

MPLC004A – OCTOBER 1994 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 4040005/B 03/95

20 PIN SHOWN

0.026 (0,66) 0.032 (0,81) D2/E2 0.020 (0,51) MIN 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D2/E2 0.013 (0,33) 0.021 (0,53) Seating Plane MAX D2/E2 0.219 (5,56) 0.169 (4,29) 0.319 (8,10) 0.469 (11,91) 0.569 (14,45) 0.369 (9,37) MAX 0.356 (9,04) 0.456 (11,58) 0.656 (16,66) 0.008 (0,20) NOM 1.158 (29,41) 0.958 (24,33) 0.756 (19,20) 0.191 (4,85) 0.141 (3,58) MIN 0.441 (11,20) 0.541 (13,74) 0.291 (7,39) 0.341 (8,66) D E1E MINMAXMIN PINS 0.385 (9,78) 0.485 (12,32) 0.685 (17,40) 84 1.185 (30,10) 0.985 (25,02) 0.785 (19,94) D/E 0.395 (10,03) 0.495 (12,57) 1.195 (30,35) 0.995 (25,27) 0.695 (17,65) 0.795 (20,19) NO. OF D1/E1 0.350 (8,89) 0.450 (11,43) 1.150 (29,21) 0.950 (24,13) 0.650 (16,51) 0.750 (19,05) 0.004 (0,10) M0.007 (0,18) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018

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