CLC020BCQ

CLC020 NSC | Alldatasheet

Document overview

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Technical content

Features

n SMPTE 259M serial digital video standard compliant n No external serial data rate setting or VCO filtering components required* n Built-in self-test (BIST) and video test pattern generator (TPG) with 16 internal patterns * n Supports all NTSC and PAL standard component and composite serial video data rates n HCMOS/TTL-compatible data and control inputs and outputs n 75Ω ECL-compatible, differential, serial cable-driver outputs n Fast VCO lock time: <75 µs n Single +5V TTL or −5V ECL supply operation n Low power: 235 mW typical n 28-lead PLCC package n Commercial temperature range 0˚C to +70˚C

Applications

n SMPTE 259M parallel-to-serial digital video interfaces for: — Video cameras — VTRs — Telecines — Video test pattern generators and digital video test equipment n Non-SMPTE video applications n Other high data rate parallel/serial video and data systems * Patents applications made or pending. Typical Application 10091712 July 2003 CLC020 SMPTE 259M Digital Video Serializer with Integrated Cable Driver © 2003 National Semiconductor Corporation DS100917 www.national.com

See NS Package Number V28A CLC020 www.national.com 2

Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V DD−VSS) 6.0V CMOS/TTL Input Voltage (VI) −0.5V to (V DD + 0.5V) CMOS/TTL Output Voltage (VO) −0.5V to (V DD + 0.5V) CMOS/TTL Input Current (single input) VI =V SS −0.5V −5 mA VI =V DD +0.5V +5 mA Input Current, Other Inputs ±1m A CMOS/TTL Output Source/Sink Current ±10 mA SDO Output Source Current 20 mA Package Thermal Resistance θ JA 28-lead PLCC 85˚C/W θJC 28-lead PLCC 35˚C/W Storage Temp. Range −65˚C to +150˚C Junction Temperature +150˚C Lead Temperature (Soldering 4 Sec) +260˚C ESD Rating (HBM) >2.5 kV ESD Rating (MM) >200 V Transistor Count 33,400 Recommended Operating Conditions Supply Voltage (VDD−VSS) 5.0V ±10% CMOS/TTL Input Voltage V SS to VDD PCLK Frequency Range 10 to 40MHz PCLK Duty Cycle 45 to 55% DN and PCLK Rise/Fall Time 1.0 to 3.0 ns Maximum DC Bias on SDO pins 3.0V ±10% Operating Free Air Temperature (T A) 0˚C to +70˚C Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3). Symbol Parameter Conditions Reference Min Typ Max Units VIH Input Voltage High Level D0 through D9, PCLK, TPG_EN and Sync. Detect Enable

2.0 V DD V

VIL Input Voltage Low Level V SS 0.8 V IIH Input Current High Level V IH =V DD +40 +60 µA IIL Input Current Low Level V IL =V SS -1 -20 µA VOH CMOS Output Voltage High Level IOH = −10 mA Lock Detect, Test Out 2.4 4.7 V DD V VOL CMOS Output Voltage Low Level IOL = +10 mA 0.0 0.3 V SS + 0.5V V VSDO Serial Driver Output Voltage RL =7 5Ω 1%, RREF = 1.69 k Ω 1%, Figure 2 SDO, SDO 700 800 900 mV P-P IDD Power Supply Current, Total RL =7 5Ω 1%, RREF = 1.69 k Ω 1%, PCLK = 27 MHz, Figure 2, NTSC Colour Bar Pattern 47 60 mA Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3). Symbol Parameter Conditions Reference Min Typ Max Units BRSDO Serial data rate R L =7 5Ω, AC coupled, (Note 5) SDO, SDO 100 400 Mbps FPCLK Reference Clock Input Frequency PCLK 10 40 MHz Reference Clock Duty Cycle PCLK 45 50 55 % tr,t f Rise time, Fall time 10%–90% D N,P CLK 1.0 1.5 3.0 ns tj Serial output jitter 270 Mbps, Figure 2, (Note 6) SDO, SDO 220 ps P-P tjit Serial output jitter (Notes 4, 5) 100 200 ps P-P tr,t f Rise time, Fall time 20%–80%, (Notes 4, 5) 500 800 1500 ps Output overshoot 1% tLOCK Lock time 270 Mbps, (Notes 5, 7) 75 µs tSU Setup time Figure 3 DN to PCLK 32 n s CLC020 www.national.com3

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3). specifies acceptable device operating conditions. Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated referenced to V SS =0 V . Note 3: Typical values are stated for V DD = +5.0V and T A = +25˚C. Note 4: Specification is guaranteed by design. Note 5: RL =7 5Ω, AC-coupled @ 270 Mbps,R REF = 1.69 k Ω 1%, See Test Loadsand Figure 2. reference. Timing jitter measured with Tektronix VM700T using jitter measurement FFT mode, frame rate, 1kHz filter bandwidth, Hanning window. Note 7: Measured from rising-edge of first P CLK cycle until Lock Detect output goes high (true). All resistors in Ohms, 1% tolerance. FIGURE 1. Test Loads

SMPTE and ITU-R parallel data rates. clock signals having CMOS/TTL-compatible signal levels. CLK input have internal pull-down devices. mial generator that identify the presence of valid video data. specified in SMPTE 259M–1997, paragraph 5 and Annex C. The scrambled data is then serialized for output. serial data clock at 10x the parallel data clock frequency. suitable for driving other CMOS devices or a LED indicator. coupled into 75 Ω (See Application Information for details). reset condition until the parallel input clock is applied. 30 µs after power has reached V DDmin. See Figure 4. FIGURE 4. Power-On Reset Sequence

BIST performs a comprehensive go-no-go test of the device.

27 MHz clock at the P

output is available during the test. FIGURE 5. Built-In Self-Test Control Sequence

TABLE 1. BIST and Test Pattern Generator Control Functions

3 D0 TPG code input LSB

4 D1 TPG code input

5 D2 TPG code input

6 D3 TPG code input MSB

17 TPG_EN TPG Enable, active high true

TABLE 2. Component Video Test Pattern Selection FIGURE 6. Test Pattern Generator Control Sequence

Pin # Name Description 1V DD Positive power supply input (digital logic) 2V DD Positive power supply input (digital logic)

3 D0 Parallel data input/Test pattern select (LSB)

4 D1 Parallel data input/Test pattern select

5 D2 Parallel data input/Test pattern select

6 D3 Parallel data input/Test pattern select (MSB)

7 D4 Parallel data input

8 D5 Parallel data input

9 D6 Parallel data input

10 D7 Parallel data input

11 D8 Parallel data input

12 D9 Parallel data input

13 PCLK Parallel clock input

14 Lock Detect VCO Lock Detect output (high-true)

SSO Negative power supply input (PLL supply)

16 V DDO Positive power supply input (PLL supply)

17 TPG_EN Test Pattern Generator (TPG) Enable input (high-true)

SSOD Negative power supply input (PLL digital supply)

19 R REF Output driver level control

20 V DDOD Positive power supply input (PLL digital supply)

21 V SSSD Negative power supply input (Output driver)

22 SDO Serial data true output

23 SDO

Serial data complement output

24 V DDSD Positive power supply input (Output driver)

25 Sync Detect Enable Parallel data sync detection enable input (low true)

26 Test_Out BIST Pass/Fail output

SS Negative power supply input (digital logic)

28 V SS Negative power supply input (digital logic)

Note: All CMOS/TTL inputs have internal pull-down devices. CLC020 www.national.com9

obtained using the video test equipment. Connect LOCK DETECT to TPG ENABLE for test pattern generator function. Remove RP1 & RP3 and replace RP2 & RP4 with 50 Ω resistor packs for coax interfacing. Install RP1-4 when using ribbon cable for input interfacing. This board is designed for use with TTL power supplies only. For optional ECL compatible load: R1A = R2A = 187; R1B = R2B = 124. All resistances & impedances in Ohms. Values with 3 significant digits are 1%; with 2 digits 5%. FIGURE 8. SD020EVK Schematic Diagram

the device’s three separate power feed systems. FIGURE 11. Jitter Plots

Application Information (Continued) values. New layouts using the CLC020 will benefit from the greatly reduced ancilliary component count and more com- pact layout. The CLC020 does not require external VCO filtering compo- nents. The external VCO filtering components at pin 17 of the GS9022 may remain connected to the CLC020 without complications. It is suggested that these be removed from the circuit board. The CLC020 uses pin 17 for its test pattern generator enable function. You will find the TPG function very useful when you make this change. Remove the C OSC capacitor used by the GS9022 at pin 26. The CLC020 uses pin 26 as the BIST pass/fail indicator output. You may attach a LED as an indicator to this pin, if desired. LED current should be limited to 10 mA maximum. The same LED type and current limiting resistor shown in Figure 8 at the Lock Detect output may be used for this indicator function. Remove any capacitor attached to pin 19. A capacitor at- tached to pin 19 will cause distortion of the output V OH level. The former data rate setting resistor, R VCO, at pin 19 now functions as the output level setting resistor, RREF. It must be changed to a 1.69 k Ω, 1% value for correct output level setting. The input series resistors and the PCLK risetime filter capaci- tor used with the GS9022 are not needed for the CLC020. These components should be removed from the circuit board and the resistors replaced by short circuits (0 Ω resis- tors). These series resistors will increase input signal rise and fall times if left on the board. The CLC020 has current-mode serial cable driver outputs. These outputs have very high internal generator resistance as one would expect of a current source. Though these current-mode outputs can produce the equivalent drive volt- ages into the load, it is necessary to change and simplify the typical GS9022 output circuit normally recommended for that device. The output load resistors at pins 22 and 23 must be changed to 75 Ω, 1% values. These resistors become the back-matching loads across which the CLC020’s outputs develop drive voltage. The series back-matching resistors used on the GS9022 should be removed and replaced with short circuits. The risetime compensating capacitors across these resistors should be removed. Pin 28 on the CLC020 is V SS and must be connected to the negative supply or ground. On layouts designed to mount the GS9022, the series R-C network connected to this pin should be replaced by short circuits (0 Ω resistors). The pull-up resistor connected to the Lock Detect output, pin 14, should be removed. It may be replaced by a LED and current limiting resistor connected to V SS if a visual lock indicator is desired. The CLC020 has an internal pull-down at the Sync Detect Enable input and may be left unconnected in SMPTE video- only applications. The CLC020 has independent power supply pins for the VCO, V SSO, pin 15 and V DDO, pin 16. The CLC020 has an output driver negative supply, V SSSD, at pin 21. The output driver positive supply, VDDSD, is pin 24 (as on the GS9022). On new layouts, additional power supply filtering may be added at these pins, if desired. CLC020 www.national.com 14

Physical Dimensions inches (millimeters) unless otherwise noted 28-Pin PLCC Order Number CLC020BCQ LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com CLC020 SMPTE 259M Digital Video Serializer with Integrated Cable Driver National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the righ t at any time without notice to change said circuitry and specifications.