CLC018 NSC | Alldatasheet
Document overview
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Technical content
Features
n Fully differential signal path n Non-Blocking n Flexible expansion to larger array sizes with very low power n Single +5/−5V or dual±5V operation n TRI-STATE outputs n Double row latch architecture n 64-lead PQFP package
Applications
n Serial digital video routing (SMPTE 259M) n Telecom/datacom switching n ATM SONET Key Specifications n High speed:>1.4 Gbps n Low jitter: <50 psPP for rates<500 Mbps <100 psPP for rates<1.4 Gbps n Low power; 850 mW with all outputs active n Fast output edge speeds: 250 ps CLC018 Block Diagram DS100088-2 DS100088-1 October 1998 CLC0188x8Digital Crosspoint Switch, 1.4 Gbps © 1998 National Semiconductor Corporation DS100088 www.national.com
Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V CC –V EE) −0.3V to +6.0V VLL Maximum V CC +6V VLL Minimum V CC −0.5V Storage Temperature Range −65˚C to +150˚C Lead Temp. (Soldering 4 sec.) +260˚C ESD Rating TBD Package Thermal Resistance θ JA 64-Pin PQFP 75˚C/W θJC 64-Pin PQFP 15˚C/W Reliability Information Transistor Count 3000 MTTF (based on limited life test data) TBD Recommended Operating Conditions Supply Voltage (VCC –V EE ) 4.5V to 5.5V Operating Temperature −40˚C to +85˚C V LL VCC or VCC +5V
Electrical Characteristics
(VCC = 0V, VEE = −5V, VLL = 0V; unless otherwise specified) (Note 4). Parameter Conditions Typ +25˚C Min/Max +25˚C Min/Max −40˚C to +85˚C Units DYNAMIC PERFORMANCE Max. Data Rate/Channel (NRZ) (Note 5) 1.4 Gbps Channel Jitter Data Rate <500 Mbps (Note 6) 50 ps PP Data Rate<1.4 Gbps (Note 6) 100 ps PP Propagation Delay (input to output) 0.75 ns Propagation Delay Match (Note 7) ±200 ps Output Rise/Fall Time (Note 8) 250 ps Duty Cycle Distortion (Note 9) 10 ps CONTROL TIMING: CONFIGURATION OA Bus to LOAD ↑ Setup Time (T1)1 5 n s LOAD ↓ to OA Bus Hold Time (T2)0 n s IA Bus, TRI to LOAD↓ Setup Time (T3)5 n s LOAD ↓ to IA Bus, TRI Hold Time (T4)5 n s Min Pulse Width: (T5) LOAD 10 ns CNFG 10 ns LOAD ↑ to CNFG ↑ Delay (T6)0 n s CNFG ↑ to Valid Delay (T7)2 0 n s CNFG ↑ to Output TRI-STATE Delay (T8)2 0 n s CNFG ↑ to Output Active Delay (T9)7 0 n s CONTROL TIMING: RESET (Note 11) TRI to RES↑ Setup Time (T10)5 n s RES ↓ to TRI Hold Time (T11)5 n s Min Pulse Width: RES (T12)1 0 n s RES ↑ to TRI-STATE Mode Delay (T13)2 0 n s RES ↑ to Broadcast Mode Delay (T14)7 0 n s STATIC PERFORMANCE Signal I/O: Min Input Swing, Differential (Note 3) 150 200 200 mV PP Input Voltage Range Lower Limit −2 V Input Voltage Range Upper Limit 0.4 V www.national.com 2
Electrical Characteristics(Continued) (VCC = 0V, VEE = −5V, VLL = 0V; unless otherwise specified) (Note 4). Parameter Conditions Typ +25˚C Min/Max +25˚C Min/Max −40˚C to +85˚C Units Signal I/O: Output Voltage Swing R LOAD =7 5Ω 800 640/960 540/1060 mV Output Voltage Range Lower Limit −2.5 V Output Voltage Range Upper Limit 0 V Control Inputs: Input Voltage - HIGH V IH min (Note 3) −1 −0.5 −0.5 V Input Voltage - LOW VIL max (Note 3) −4 −4.5 −4.5 V Input Voltage - HIGH VIH min VLL = +5V (Note 3) 4 4.5 4.5 V Input Voltage - LOW VIL max VLL = +5V (Note 3) 1 0.5 0.5 V Input Current - HIGH V IH =V LL (Note 3) 1 0.2/2.0 0.1/2.5 µA Input Current - LOW V IL =V LL −5V (Note 3) −100 −200/10 −250/15 µA MISCELLANEOUS PERFORMANCE V CC Supply Current All Outputs Active (Notes 3, 13, 14) 157 127/202 119/217 mA VCC Supply Current All Outputs TRI-STATE (Note 3) 7 3/11 2/12 mA VLL Supply Current V LL = +5V (Note 3) 7 mA Input Capacitance 1.5 pF Output Capacitance 2 pF Note 1:“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2:Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3:J-level spec. is 100% tested at +25˚C. Note 4:VLL and all VEE supply pins are bypassed with 0.01 µF ceramic capacitor. Note 5:Bit error rate less than 10−9 over 50% of the bit cell interval. Note 6:Measured using a pseudo-random (223−1 pattern) binary sequence with all other channels active with an uncorrelated signal. Note 7:Spread in propagation delays for all input/output combinations. Note 8:Measured between the 20% and 80% levels of the waveform. Note 9:Difference in propagation delay for output low-to-high vs. output high-to-low transition. Note 10:Refer to theConfiguration Timing Diagram. Note 11:Refer to theReset Timing Diagram. Note 12:The bias current for high speed data input depends on the number of data outputs that are selecting that input. Note 13:The VCC supply current is a function of the number of active data outputs. IVCC 1 8 * N+7m Awhere N is an integer from 0 to 8. Note 14:IVEE =IVCC +IVLL. www.national.com3
Typical Performance Characteristics DS100088-3 DS100088-4 DS100088-5 DS100088-6 DS100088-7 DS100088-8 www.national.com 4
VCC is the most positive rail for the data path. When the data levels are ECL compatible, then VCC should be connected to GND. For PECL data (+5V referenced ECL), VCC is con- nected to the +5V supply. Please refer to the device opera- tion section in this datasheet for recommendations on the bypassing and ground/power plane requirements of this de- vice. V EE is the most negative rail for the data path. When the data levels are ECL compatible, then VEE is connected to a −5.2V power supply. For PECL data (+5V referenced ECL), VEE is connected to GND. VLL is the logic-level power supply. If the control signals are referenced to +5V, VLL is connected to a +5V supply. If con- trol signals are ECL compatible, VLL is connected to GND. DATA INPUT PINS DI0 and DI0 through DI7 and D17 are the data input pins to the CLC018. Depending upon how the Power pins are con- nected (please refer to the Power Pin section above) the data may be either differential ECL, or differential PECL. To drive the CLC018 inputs with a single-ended signal, please refer to the section “Using Single-Ended Data” in the OP- ERATION section of this datasheet. DATA OUTPUT PINS DO0 and DO0 through DO7 and DO7 are the data output pins of the CLC018. The CLC018 outputs are differential cur- rent outputs which can be converted to ECL or PECL com- patible outputs through the use of load resistors. Please re- fer to the “Output Interfacing” paragraph in the OPERATION section of this datasheet for more details. CONTROL PINS IA2, IA1 and IA0 are the three bit input selection address bus. The input port to be addressed is placed on this bus. IA2 is the Most Significant Bit (MSB). If input port 6 is to be addressed, IA2, IA1, IA0 should have 1, 1, 0 asserted on them. The IA bus should be driven with CMOS levels, if V LL is +5V. These levels are thus +5V referenced (standard CMOS). If V LL is connected to GND, the input levels are ref- erenced to the −5V and GND supplies. OA2, OA1 and OA0 are the output selection address bus. The output port selected by the OA bus is connected to the input port selected on the IA bus when the data is loaded into the configuration registers. OA2 is the MSB. If OA2, OA1, OA0 are set to 0, 0, 1; then output port 1 will be selected. CS is an active-high chip select input. When CS is high, the RES, LOAD, and CNFG pins will be enabled. LOAD is the latch control for the LOAD register. When LOAD is high, the load register is transparent. Outputs follow the state of the IA bus, and are presented to the inputs of the Configuration register selected by the OA bus. When LOAD is low, the outputs of the Load register are latched. RES is the reset control of the configuration and load regis- ters. A high-going pulse on the RES pin programs the switch matrix to one of two possible states: with TRI low, all outputs are connected to input #0; with TRI high, all outputs are put in TRI-STATE condition. TRI will program the selected output to be in a high imped- ance or TRI-STATE condition. To place an output in TRI-STATE, assert a logic-high level on the TRI input when the desired input and output addresses are asserted on the respective address inputs and strobe the LOAD input as de- picted in the ”Configuration Truth Table”. To enable an out- put, assert a logic-low level on the TRI input together with the appropriate addresses and strobe the LOAD input as previ- ously described. CNFG is the configuration register latch control. When CNFG is high the Configuration register is made transparent, and the switch matrix is set to the state loaded into the Load registers. When CNFG is low, the state of the switch matrix is latched. DS100088-9 Order Number CLC018AJVJQ See NS Package Number VJE64A www.national.com5
Operation(Continued) put address (OA) bus. Data to be written into the load regis- ter, consisting of the 3-bit address of the input to be con- nected to that output and the output-enable control bit, are placed on the input address (IA) bus. Input data is stored in the load registers at the low-to-high transition of the LOAD input pin with chip-select (CS) high-true. The contents of the load registers are transferred to the second rank of CON- FIGURATION REGISTERS at the low-to-high transition of the CNFG input signal (with CS high). This causes the state of the entire switch matrix to be set to the selected configu- ration. The entire crosspoint may be placed in an initializing state, with all outputs connected to input-0 and with all outputs ei- ther enabled or TRI-STATE. To do so, hold TRI low to make outputs active, or high to place outputs in TRI-STATE, and apply a high-going pulse to the RES input pin (with CS high). In summary, outputs are configured by: a) first placing the 3-bit address of that output on the OA bus together with b) the 3-bit address of the input to be connected to that output on the IA bus, c) the output-enable (TRI-STATE) control bit for that output on the IA bus, d) making chip-select (CS) true, and then e) providing a high-going pulse to the LOAD input pin. f) Repeat these four steps for each output to be config- ured. The entire crosspoint matrix may now be configured with the data held in the load registers. To implement the configura- tion, apply a high-going pulse to the CNFG input pin. The contents of the load registers are transferred to the configu- ration registers and the new configuration of all crosspoints is effected. The CLC018 Configuration Truth Table is shown at the end of the datasheet. EXPANDING THE SWITCH SIZE The CLC018 was designed for easy expansion to larger ar- ray sizes without paying a significant penalty in either speed or power. The power dissipation of the expanded array will be dominated by the number of active outputs, therefore power will increase linearly with the array size even though the number of components required increases as the square of the array size. As an example, a single CLC018 can be used for an 8x8 array, and it will dissipate about 0.85W. A 32 x 32 array will require 16 CLC018s and will consume only about 4W. www.national.com9
FIGURE 11. Expanded Input Ports
FIGURE 12. 24 x 32 Output Switch Array
Operation(Continued) CALCULATING THE POWER DISSIPATION IN AN EXPANDED ARRAY The CLC016 dissipates about 100 mW per active output plus about 50 mW quiescent power. With all outputs active, this is about 850 mW. In an expanded array, all devices will dissi- pate quiescent power, but only those devices with active out- puts will dissipate the 100 mW/output. So, an N-by-M device array (an 8xN-input-by-8xM-output switch) with all outputs active will dissipateNxMx5 0m W+8xMx1 0 0m W .A3 2 - input x 32-output (4 x 4 device) switch array dissipates4x4 x5 0m W+8x4x1 0 0m W=4 W . CONTROLLED IMPEDANCE TRANSMISSION LINES AND OTHER LAYOUT TECHNIQUES All transmission lines whose length is greater than 1⁄4 wave- length of the highest frequencies present in the transmitted signal require proper attention to impedance control to avoid distortion of the signal. Digital signals are especially suscep- tible to distortion due to poorly controlled line characteristics and reflections. With its 250 ps output transitions, which im- ply a bandwidth of 4 GHz or more, transmission lines driven by the CLC018 must be carefully designed and correctly ter- minated. Either microstrip line, which resides on the outer surfaces of a printed circuit board and paired with an image ground plane, or stripline, which is sandwiched in an inner layer between image ground planes, may be used in CLC018 designs. With either line type, it is important to maintain a uniform characteristic impedance over the entire extent of the transmission line system. Likewise, the receiv- ing end of these lines must be terminated in a resistance equal to the characteristic impedance to preserve signal fi- delity. Figure 13shows representative methods of interfacing to and from the CLC018. Often, when voltage-mode drivers, such as ECL, with low output impedance (also called equivalent generator resis- tance) are used to drive bus networks, a series resistor con- nects the output of the amplifier to the transmission line. This resistor serves both as a termination for any signals travel- ling toward the source- end of the line and as the series leg of a voltage divider (with the transmission line as the shunt leg) to reduce the transmitted signal level. This resistor’s cor- rect value is Z O −R OUT . However, a value equal to ZO may be used successfully in most situations. The receiving end of the line is terminated in a resistance equal to the value of Z O of the receiving end of the line. A resistance equal to the line’s Z O works in most situations. In cases where the bus is heavily loaded, the receiving end termination’s value may need to be reduced to the loaded- Z O of the line. (Please see the material on distributed loading effects on line character- istics in the Fairchild F100K ECL 300 Series Databook and Design Guide). Current-mode drivers, with their high equivalent generator resistance, when used as bus drivers require a resistance equal to Z O at each end of the bus to either power or ground as appropriate for the design. A detailed discussion of digital transmission line design tech- niques is beyond the scope of this data sheet, but many good references are available from National Semiconductor and others. Extensive material is available in the National In- terface Databook, theFairchild F100K ECL 300 Series Da- tabook and Design Guideand theMotorola MECL System Design Handbook. Especially useful is the National SemiconductorTransmis- sion Line RAPIDESIGNERrSliderule and user manualAN- 905. The RAPIDESIGNER is available by calling the Na- tional Semiconductor Customer Response Center in your area and asking for either Literature Number 633200-001 (ISO Metric units) or 633201-001 (English units). The User Manual for both versions is Literature Number 100905-002 and is available on our WEB Site at http://www.national.com as AN-905. www.national.com 14
FIGURE 13. Input/Output Bussing
Operation(Continued) Configuration Truth Table IA2 IA1 IA0 OA2 OA1 OA0 TRI RES LOAD CNFG CS Condition of Device XXXXXXXX X X 0 N O CHANGE XXXXXX0 I X X 1 Load I/P 0 to All O/Ps XXXXXX1 I X X 1 TRI-STATE All O/P 0 XXX000 10 I 0 1 TRI-STATE O/P 0 XXX001 10 I 0 1 TRI-STATE O/P 1 XXX010 10 I 0 1 TRI-STATE O/P 2 XXXCBA 10 I 0 1 TRI-STATE O/P CBA RQPCBA 00 I 0 1 Load I/P PQR to O/P CBA and Enable O/P CBA
00000000 I 0 1 Load I/P 0 to O/P 0
00000100 I 0 1 Load I/P 0 to O/P 1
00001000 I 0 1 Load I/P 0 to O/P 2
00001100 I 0 1 Load I/P 0 to O/P 3
00010000 I 0 1 Load I/P 0 to O/P 4
00010100 I 0 1 Load I/P 0 to O/P 5
00011000 I 0 1 Load I/P 0 to O/P 6
00011100 I 0 1 Load I/P 0 to O/P 7
00100000 I 0 1 Load I/P 1 to O/P 0
00100100 I 0 1 Load I/P 1 to O/P 1
00101000 I 0 1 Load I/P 1 to O/P 2
00101100 I 0 1 Load I/P 1 to O/P 3
00111100 I 0 1 Load I/P 1 to O/P 7
11111000 I 0 1 Load I/P 7 to O/P 6
11111100 I 0 1 Load I/P 7 to O/P 7
XXXXXXX0 0 I 1 Activate New Configuration www.national.com 16
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