CLC011 NSC | Alldatasheet

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Technical content

Features

n Data decoding and deserializing n CLC011B operates to 360Mbps n CLC011A operates to 300Mbps n Low noise injection to power supplies n Single +5V or −5.2V supply operation n Output levels programmable for interface to 5V or 3.3V logic n Low power n Low cost Block Diagram DS100086-1 January 1999 CLC011 Serial Digital Video Decoder © 1999 National Semiconductor Corporation DS100086 www.national.com

Name Pin No. Description EAV 1 End of active video flag. For component video, a logic low is output for one cycle of the parallel clock every time an EAV timing reference is detected. The pulse is aligned with the fourth word of the timing reference (the XYZ word). For composite video, this line is always asserted high. V EE 2, 4, 26 Negative supply pins. NC 3 Unused pin. SDI+, SDI− 5, 6 Differential serial data inputs. SCI+, SCI− 7, 8 Differential serial clock inputs. NRZI 9 A logic high at this pin enables NRZI-to-NRZ conversion. DESC 10 A logic high at this pin enables descrambling. FE 11 Frame enable. Enables resynchronization of the parallel word at the next TRS. V CC 12 Positive supply pin. VCP 13 Parallel clock high level programming pin. The voltage at this supply pin defines the logic high level for the parallel clock output. NSP 14 New sync position. Indicates that the most recent TRS is in a new position relative to the previous TRS. Remains high until the parallel rate clock is aligned properly with the TRS. TRS 15 Timing reference flag. A logic low is output for the duration of the TRS. PCLK 16 Parallel clock output. The rising edge of this clock is located at the center of the parallel data window. PD0–9 17, 19–25, 27, 28 Parallel data outputs. VDP 18 Parallel data high level programming pin. The voltage at this supply pin defines the logic high level for the data outputs. DS100086-2 28-Pin PLCC Order Number CLC011ACQ, or CLC011BCQ See NS Package Number V28A www.national.com 2

Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V CC –V EE ) +6V Storage Temperature Range −65˚C to +150˚C Junction Temperature +150˚C ESD Rating (HBM) PDx 500V other 2kV Package Thermal Resistance θ JA 28-Pin PLCC 85˚C/W θJC 28-Pin PLCC 35˚C/W Reliability Information Transistor Count 3076 Recommended Operating Conditions Supply Voltage (VCC –V EE ) 4.5V to 5.5V Logic High Voltage (VCP –V EE and VDP –V EE ) 3.0V to 5.5V Operating Temperature 0˚C to +70˚C

Electrical Characteristics

(VCC = +5V, VEE = 0V, CL = 10 pF; unless specified). Parameter Conditions Typ +25˚C Min/Max +25˚C Min/Max 0˚C to +70˚C Units DYNAMIC PERFORMANCE Minimum Serial Data Rate 0 Mbps Maximum Serial Data Rate CLC011B 400 360 360 Mbps CLC011A 300 300 Mbps PDn and PCLK Rise/Fall Time C L = 2 pF,(Note 9) 2.0 ns PDn and PCLK Rise/Fall Time C L = 20 pF,(Note 9) 4.0 ns PCLK Rising Edge Residual Jitter (Note 9) 50 ps pp TIMING PERFORMANCE SD to SC Setup Time 0.2 0.2 ns SC to SD Hold Time 00 n s PDn to PCLK Skew (Note 9) ±0.8 ns PDn Valid to PCLK↑ PCLK = 27 MHz, (Note 9) 18 ns PCLK ↑ to PDn Invalid PCLK = 27 MHz, (Note 9) 18 ns Digital Latency (Notes 6, 7, 9) 42 sclk cycles Output Buffer Latency (Notes 7, 9) 10 ns STATIC PERFORMANCE I CC Supply Current (Note 9) V CC Pin 44 mA VDP and VCP Supply Current PCL K = 0 MHz, (Note 9) 2 mA VDP and VCP Supply Current PCLK = 27 MHz, (Note 9) 12 mA SD and SC Inputs Input Range Upper Limit V CC VCC V Input Range Lower Limit V EE +2.5 V EE +2.5 V Minimum Differential Input 200 200 mV I IH 10 15 µA FE, NRZI, and DESC Inputs VIL VEE +0.8 V EE +0.8 V VIH VEE +2.0 V EE +2.0 V Outputs VOL IOL =1 0m A V EE +0.5 V EE +0.5 V VOH IOH =1 0m A V CC −0.5 V CC −0.5 V MISCELLANEOUS PERFORMANCE SD and SC Input Capacitance (Note 9) 2.0 pF SD and SC Input Resistance (Note 9) 20 k Ω Note 1:“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. www.national.com3

Electrical Characteristics(Continued) Note 2:Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3:Nominal position of rising edge of serial clock is at the center of the serial data eye. Note 4:Nominal position of the rising edge of PCLK is at the center of the PDn eye. Note 5:See Timing Diagrams. Note 6:Data latency due to digital registers, measured from MSB of serial data to parallel clock out. Note 7:Total latency is the digital latency plus the output buffer latency. Note 8:100% tested at 25˚C, sample tested over temperature. Note 9:Typicals only specified. Timing Diagrams DS100086-3 FIGURE 1. www.national.com 4

Output Interface— Control Outputs PCLK (Parallel Clock):The parallel output or word clock, PCLK, is synchronous with the parallel data outputs, PD0–9. The rising edge of PCLK is located at the center of the par- allel data window. TRS (Timing Reference Signal):The active-low TRS out- put pulse is four parallel clock periods long. TRS is active during decoding of both composite and component video signals. EAV (End of Active Video):The EAV output is pulsed low for one cycle of the parallel clock every time an EAV timing reference is detected during decoding of component video. The pulse is coincident with the fourth word of the timing ref- erence (the XYZ word). During reception of composite video, this output is always asserted high. NSP (New Sync Position):The active-low NSP output indi- cates that the most recently received TRS is in a different po- sition relative to the previous TRS. NSP remains high until the parallel rate clock is properly aligned with the TRS, then goes low. PCB Layout Guidelines The CLC011 is not as sensitive to PCB layout as some Serial Digital Video decoders. The following suggestions will help achieve and maintain optimum system performance. 1. Locate the CLC011 decoder away from equalizers and other sensitive circuitry to avoid unwanted crosstalk from clock and data outputs which may degrade system per- formance. 2. The trace from the signal input connector to the CLC011 must be kept short and should not run parallel to the data output traces. 3. Bypass each power pin with a 0.01 µF to 0.1 µF mono- lithic ceramic capacitor. 4. Power the CLC011 and other clock recovery circuitry from a separate power supply network from that of other digital circuitry on the board. Other PCB layout tips may be found in: “Keeping Analog Sig- nals Pure in a Hostile Digital World”, Electronic Design, Spe- cial Analog Issue, June 24, 1996, available from National Semiconductor. Request Literature number 665502-001. www.national.com7

Physical Dimensionsinches (millimeters) unless otherwise noted LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or sys- tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose fail- ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 Order Number CLC011ACQ, or CLC011BCQ CLC011 Serial Digital Video Decoder National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.