CL0204KRX5R5BB121 YAGEO | Alldatasheet
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Product Specification – November 21, 2016 V.1 DATA SHEET SURFACE-MOUNT CERAMIC MULTILAYER CAPACITORS Low-Inductance X5R / X7R
6.3 V TO 50 V
RoHS compliant & Halogen Free
www.yageo.com Nov. 21, 2016 V.1 Surface-Mount Ceramic Multilayer Capacitors Product specification Low Inductance X5R, X7R 6.3V to 50V ORDERING INFORMATION - GLOBAL PART NUMBER, PHYCOMP CTC All part numbers are identified by the series, size, tolerance, TC material, packing style, voltage, process code, termination and capacitance value. YYAAGGEEOO BBRRAANNDD oorrddeerriinngg ccooddee GLOBAL PART NUMBER (PREFERRED ) CL XXXX X X XXX X BB XXX (1) SIZE – INCH BASED (METRIC) 0204(0510) 0306(0816) 0508(1220) 0612(1632) (2) TOLERANCE K = ± 10% M = ± 20% (3) PACKING STYLE R = Paper/PE taping reel; Reel 7 inch K = Blister taping reel; Reel 7 inch P = Paper/PE taping reel; Reel 13 inch F = Blister taping reel; Reel 13 inch (4) TC MATERIAL X5R / X7R (5) RATED VOLTAGE 5 = 6.3 V 6 = 10 V 7 = 16 V 8 = 25 V 9 = 50 V (6) CAPACITANCE VALUE 2 significant digits+number of zeros The 3rd digit signifies the multiplying factor, and letter R is decimal point Example: 121 = 12 x 101 = 120 pF SCOPE This specification describes Mid- voltage X7R series chip capacitors with lead -free terminations
APPLICATIONS
Processor package decoupling AC noise reduction in multi -chip modules.
FEATURES
Nickel -barrier end termination RoHS compliant Halogen Free compliant
www.yageo.com Nov. 21, 2016 V.1 Surface-Mount Ceramic Multilayer Capacitors Product specification Low Inductance X5R, X7R 6.3V to 50V CONSTRUCTION The capacitor consists of a rectangular block of ceramic dielectric in which a number of interleaved metal electrodes are contained. This structure gives rise to a high capacitance per unit volume. The inner electrodes are connected to the two end terminations and finally covered with a layer of plated tin (NiSn). The terminations are lead -free. A cross section of the structure is shown in Fig.1. Fig. 1 Surface mounted multilayer ceramic capacitor construction TYPE L1 (mm) W (mm) T (mm) L2 / L3 (mm) L4 (mm) min. max. min. 0612*: 1uF/16V, 470nF~1uF/25V, 120nF~470nF/50V Table 1 For outlines see fig. 2 DIMENSION OOUUTTLLIINNEESS For dimension see Table 1 Fig. 2 Surface mounted multilayer ceramic capacitor dimension
www.yageo.com Nov. 21, 2016 V.1 Surface-Mount Ceramic Multilayer Capacitors Product specification Low Inductance X5R, X7R 6.3V to 50V CAPACITANCE RANGE & THICKNESS FOR X5R Table 2 Sizes from 0204 CAP. 0204
6.3 V / 10V
10 nF 0.3 ± 0.1 15 nF 0.3 ± 0.1 22 nF 0.3 ± 0.1 33 nF 0.3 ± 0.1 47 nF 0.3 ± 0.1 68 nF 0.3 ± 0.1 100 nF 0.3 ± 0.1 150 nF 220 nF 330 nF 470 nF 680 nF 1 uF NOTE 1. Values in shaded cells indicate thickness class in mm 2. Capacitance value of non E-6 series is on request 3. For special ordering code, please contact local sales force before order.
www.yageo.com Nov. 21, 2016 V.1 Surface-Mount Ceramic Multilayer Capacitors Product specification Low Inductance X5R, X7R 6.3V to 50V CAPACITANCE RANGE & THICKNESS FOR X7R Table 3 Sizes from 0306 to 0508 CAP. 0306 0508
6.3 V / 10V 10 V 16 V 25 V
150 nF 0.85 ± 0.1 0.85 ± 0.1 330 nF 470 nF 0.85 ± 0.1 680 nF 1 uF 0.85 ± 0.1 NOTE 1. Values in shaded cells indicate thickness class in mm 2. Capacitance value of non E-6 series is on request 3. For special ordering code, please contact local sales force before order.
www.yageo.com Nov. 21, 2016 V.1 Surface-Mount Ceramic Multilayer Capacitors Product specification Low Inductance X5R, X7R 6.3V to 50V Table 5 THICKNESS CLASSES AND PACKING QUANTITY SIZE CODE THICKNESS CLASSIFICATION TAPE WIDTH QUANTITY PER REEL Ø 180 MM / 7 INCH Ø 330 MM / 13 INCH QUANTITY PER BULK CASE Paper Blister Paper Blister CAPACITANCE RANGE & THICKNESS FOR X7R Table4 Sizes from 0612 CAP. 0612
6.3 V 10 V 16 V 25 V 50 V
- Values in shaded cells indicate thickness class in mm 2. Capacitance value of non E-6 series is on request 3. For special ordering code, please contact local sales force before order
www.yageo.com Nov. 21, 2016 V.1 Surface-Mount Ceramic Multilayer Capacitors Product specification Low Inductance X5R, X7R 6.3V to 50V Table 6 DESCRIPTION VALUE Capacitance range 10 nF to 1 uF Capacitance tolerance Dissipation factor (D.F.) X5R / X7R ≤ 5 % Insulation resistance after 1 minute at Ur (DC) Rins ≥ 10 GΩ or Rins × C ≥ 500 seconds whichever is less Maximum capacitance change as a function of temperature (temperature characteristic/coefficient): X5R / X7R ± 15% Operating temperature range: X5R –55 °C to +85 °C X7R –55 °C to +125 °C
ELECTRICAL CHARACTERISTICS
XX77RR DDIIEELLEECCTTRRIICC CCAAPPAACCIITTOORRSS;; Unless otherwise specified, all test and measurements shall be made under standard atmospheric conditions for testing as given in 5.3 of IEC 60068 -1: - Temperature: 15 °C to 35 °C - Relative humidity: 25% to 75% - Air pressure: 86 kPa to 106 kPa Before the measurements are made, the capacitor shall be stored at the measuring temperature for a time sufficient to allow the entire capacitor to reach this temperature. The period as prescribed for recovery at the end of a test is normally sufficient for this purpose.
www.yageo.com Nov. 21, 2016 V.1 Surface-Mount Ceramic Multilayer Capacitors Product specification Low Inductance X5R, X7R 6.3V to 50V SOLDERING RECOMMENDATION Table 7 SOLDERING METHOD SIZE 0204 0306 0508 0612 Reflow Reflow/Wave O O O O TEST TEST METHOD PROCEDURE REQUIREMENTS Mounting IEC 60384-
4.3 The capacitors may be mounted on printed-circuit boards or
4.4 Any applicable method using × 10 magnification In accordance with specification
Capacitance 4.5.1 Class 2: f = 1 KHz, measuring at voltage 1 Vrms at 20 °C Within specified tolerance Dissipation Factor (D.F.)
4.5.2 Class 2:
f = 1 KHz, measuring at voltage 1 Vrms at 20 °C In accordance with specification Insulation Resistance
4.5.3 At Ur (DC) for 1 minute In accordance with specification
Table 8 Test procedures and requirements
www.yageo.com Nov. 21, 2016 V.1 Surface-Mount Ceramic Multilayer Capacitors Product specification Low Inductance X5R, X7R 6.3V to 50V TEST TEST METHOD PROCEDURE REQUIREMENTS Temperature coefficient
4.6 Capacitance shall be measured by the steps shown
in the following table. The capacitance change should be measured after 5 min at each specified temperature stage. Step Temperature(℃) a 25± 2 b Lower temperature± 3℃ c 25± 2 d Upper Temperature± 2℃ e 25± 2 Class II Capacitance Change shall be calculated from the formula as below ∆C = C1-C2 x 100% C1: Capacitance at step c C2: Capacitance at step b or d Class2: X7R/X5R : ∆ C/C : ± 15% In case of applying voltage, the capacitance change should be measured after 1 more min. with applying voltage in equilibration of each temp. stage. Adhesion IEC 60384- 4.7 A force applied for 10 seconds to the line joining the terminations and in a plane parallel to the substrate Force size ≥ 0306: 5N size = 0204: 2.5N Bending Strength 4.8 Mounting in accordance with IEC 60384-22 paragraph 4.3 No visible damage Conditions: bending 1 mm at a rate of 1 mm/s, radius jig 5 mm ∆C/C Class2: X7R/X5R : ± 10%
www.yageo.com Nov. 21, 2016 V.1 Surface-Mount Ceramic Multilayer Capacitors Product specification Low Inductance X5R, X7R 6.3V to 50V TEST TEST METHOD PROCEDURE REQUIREMENTS Resistance to Soldering Heat 4.9 Precondition: 150 +0/–10 °C for 1 hour, then keep for 24 ± 1 hours at room temperature Preheating: 120 °C to 150 °C for 1 minute and 170 °C to 200 °C for 1 minute. Solder bath temperature: 260 ± 5 °C Dipping time: 10 ± 0.5 seconds Recovery time: 24 ±2 hours Dissolution of the end face plating shall not exceed 25% of the length of the edge concerned ∆C/C Class2: X7R/X5R : ± 10% D.F. within initial specified value Rins within initial specified value Solderability 4.10 Preheated the temperature of 80 °C to 140 °C and maintained for 30 seconds to 60 seconds. Test conditions for leadfree containing solder alloy Temperature: 245 ± 5 °C Dipping time: 3 ± 0.3 seconds Depth of immersion: 10 mm The solder should cover over 95% of the critical area of each termination Rapid Change of Temperature IEC 60384-
4.11 Preconditioning;
150 +0/–10 °C for 1 hour, then keep for 24 ± 1 hours at room temperature 5 cycles with following detail: 30 minutes at lower category temperature 30 minutes at upper category temperature Recovery time 24 ± 2 hours No visual damage ∆C/C Class2: X7R/X5R : ± 15% D.F. meet initial specified value Rins meet initial specified value
www.yageo.com Nov. 21, 2016 V.1 Surface-Mount Ceramic Multilayer Capacitors Product specification Low Inductance X5R, X7R 6.3V to 50V TEST TEST METHOD PROCEDURE REQUIREMENTS Damp Heat with Ur load 4.13 1. Preconditioning, class 2 only: 150 +0/-10 °C /1 hour, then keep for 24 ± 1 hour at room temp 2. Initial measure: Spec: refer initial spec C, D, IR 3. Damp heat test: 500 ± 12 hours at 40 ±2 °C; 90 to 95% R.H; 1.0 Ur applied. 4. Recovery: Class 1: 6 to 24 hours Class 2: 24 ± 2 hours 5. Final measure: C, D, IR P.S. If the capacitance value is less than the minimum value permitted, then after the other measurements have been made the capacitor shall be precondition according to “IEC 60384 4.1” and then the requirement shall be met. No visual damage after recovery ∆C/C Class2: X7R/X5R : ± 20% D.F. Class2: X7R/X5R : ≤ 2 x specified value Rins Class2: X7R/X5R : ≥ 500 MΩ or Rins x Cr ≥ 25s whichever is less Δ C/C Class2: X7R/X5R : ± 25% D.F. Class2: X7R/X5R : ≤ 2 x specified value Rins Rins x Cr ≥ 25Ω· F
www.yageo.com Nov. 21, 2016 V.1 Surface-Mount Ceramic Multilayer Capacitors Product specification Low Inductance X5R, X7R 6.3V to 50V TEST TEST METHOD PROCEDURE REQUIREMENTS Endurance IEC 60384- 4.14 1. Preconditioning, class 2 only: 150 +0/-10 °C /1 hour, then keep for 24 ± 1 hour at room temp 2. Initial measure: Spec: refer initial spec C, D, IR 3. Endurance test: Temperature: NP0: 125 °C Specified stress voltage applied for 1,000 hours: Applied 2.0 x Ur for general product Temperature: X7R: 125°C Specified stress voltage applied for 1,000 hours: Recovery time: 24 ± 2 hours 4. Final measure: C, D, IR P.S. If the capacitance value is less than the minimum value permitted, then after the other measurements have been made the capacitor shall be precondition according to “IEC 60384 4.1” and then the requirement shall be met. No visual damage ∆C/C Class2: X7R/X5R : ± 20% D.F. Class2: X7R/X5R : ≤ 2x initial value max Rins Class2: X7R/X5R : ≥ 1,000 MΩ or Rins x Cr ≥ 50s whichever is less Δ C/C Class2: X7R/X5R : ± 25% D.F. Class2: X7R/X5R : ≤ 2x initial value max Rins Class2: Rins x Cr ≥ 50 Ω· F Voltage Proof IEC 60384-1 4.5.4 Specified stress voltage applied for 1 to 5 seconds Ur ≤ 100 V: series applied 2.5 Ur Charge/Discharge current less than 50mA No breakdown or flashover
www.yageo.com Nov. 21, 2016 V.1 Surface-Mount Ceramic Multilayer Capacitors Product specification Low Inductance X5R, X7R 6.3V to 50V
REVISION HISTORY
REVISION DATE CHANGE NOTIFICATION DESCRIPTION Version 1 Nov. 7, 2016 - - Add 13" packing Version 0 Jun. 26, 2015 - - New