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High‐Efficiency 5V MOSFET Gate Driver CHL8505 December 6, 2011 | FINAL | V1.052

ORDERING INFORMATION

CHL8505   Package Tape & Reel Qty Part Number DFN 3000 CHL8505CRT Top View GND Pin 11 3x3 DFN NC BOOT LO_GATE HI_GATE NCPWM VCC NC SWITCH VDRV Figure 3: CHL8505 Pin Diagram Enlarged T – Tape and Reel R – Package Type (DFN) C – Operating Temperature (Commercial Standard)

High‐Efficiency 5V MOSFET Gate Driver CHL8505 December 6, 2011 | FINAL | V1.053 FUNCTIONAL BLOCK DIAGRAM Figure 4: CHL8505 Simplified Functional Block Diagram

High‐Efficiency 5V MOSFET Gate Driver CHL8505 December 6, 2011 | FINAL | V1.054 TYPICAL APPLICATION DIAGRAM +3.3V V_CPU_L1 CHL8325A8 VINSEN PWM4 PWM5 PWM3 PWM 2 PWM1 ISEN5 VR_RDY_L11/PWRGD2 VSEN VCC RRES EN V18A VRTN IRTN3 ISEN4 IRTN1 RCSP IRTN2 RCSM ISEN3 ISEN2 ISEN1 IRTN4 +12V EN L O A D RCS CCS Rseries Rseries RTh RVIN_1 RVIN_2 IRTN5

10 VR_RDY_L21/PWROK2

20VAR_GATE_ PM_ADDR V_CPU_L2 L O A D

15 VR_HOT#1/

VRHOT_ICRIT#2 +3.3V

19 SMB_CLK

SMB_DIO SMB_ALERT#

30 RCSP_L2

RCSM_L2 RCS CCS Rseries Rseries RTh VSEN_L2 VRTN_L2

19 SV_CLK1/SVC2

SV_DIO1/SVD2 SV_ALERT#1/VFIXEN2 Notes

1 Pin definition in Intel & MPoL modes

2 Pin definition in AMD mode

V 12V VDRV LoGate HiGate Vcc GND PWM Boot Switch CHL8505 V 12V VDRV LoGate HiGate Vcc GND PWM Boot Switch CHL8505 V 12V VDRV LoGate HiGate Vcc GND PWM Boot Switch CHL8505 V 12V VDRV LoGate HiGate Vcc GND PWM Boot Switch CHL8505 V 12V Figure 5: 4+1 CPU VR solution using CHL8505 MOSFET Drivers & CHL8325A Controller

High‐Efficiency 5V MOSFET Gate Driver CHL8505 December 6, 2011 | FINAL | V1.055 PIN DESCRIPTIONS PIN# PIN NAME PIN DESCRIPTION 1 PWM The PWM signal is the control input for the driver from a 1.8V IR ATL‐based PWM signal. Connect this pin to the PWM output of the controller. 2 VCC Connect this pin to a +5V bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND. 3 VDRV Connect this pin to a separate supply voltage between 4.0V and 13.2V to vary the drive voltage on the low‐side MOSFETs. Place a high quality low ESR ceramic capacitor from this pin to GND. 4 NC Leave this pin floating.

5 BOOT

Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the SWITCH pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value. 6 HI_GATE Upper gate drive output. Connect to gate of high‐side power N‐Channel MOSFET. 7 SWITCH Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides a return path for the upper gate drive 8 LO_GATE Lower gate drive output. Connect to gate of the low‐side power N‐Channel MOSFET. 9 NC Leave this pin floating. 10 NC Leave this pin floating. PAD (11) GND Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.

High‐Efficiency 5V MOSFET Gate Driver CHL8505 December 6, 2011 | FINAL | V1.056 ABSOLUTE MAXIMUM RATINGS VCC, VDRV ‐0.3V to +7.0V PWM, OTSET, OT# ‐ 0.3V to +7.0V BOOT‐GND, BOOT‐SWITCH ‐0.3V to +35.0V, ‐0.3V TO +7V LO_GATE ‐ 0.3V to VDRV + 0.3V, <200ns: ‐5V to VDRV + 0.3V HI_GATE SWITCH – 0.3V to VBOOT + 0.3V, <20ns: SWITCH –5V to VBOOT + 0.3V SWITCH ‐ 0.3V to +35.0V, <200ns, ‐8V ESD HBM 250V JEDEC Standard Thermal Information Thermal Resistance (θJC) 3°C/W Thermal Resistance (θJA)1 45°C/W Maximum Operating Junction Temperature 150°C Maximum Storage Temperature Range ‐ 65°C to 150°C Maximum Lead Temperature (Soldering 10s) 300°C Note: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied.

High‐Efficiency 5V MOSFET Gate Driver CHL8505 December 6, 2011 | FINAL | V1.057 ELECTRICAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN Recommended Operating Ambient Temperature Range ‐ 40°C to 85°C Recommended Maximum Operating Junction Temperature 125°C Supply Voltage Range +5V ± 10% The electrical characteristics table lists the spread of values guaranteed within the recommended operating conditions. Typical values represent the median values, which are related to 25°C, unless otherwise specified. VCC = 5.0V, HVCC = 7.0V, LVCC = 5.0V.

ELECTRICAL CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Supply Idle Supply Bias Current IVCC + IVDRV PWM input tri‐stated ‐ 2.3 ‐ mA Active Supply Bias Current IVCC VCC = 5V 2.7 3.1 3.5 mA VCC Rising Threshold for POR 3.5 3.7 3.9 V VCC Falling Threshold for POR 3.2 3.4 3.6 V PWM Input IR ATL Mode PWM Input High Threshold VIH(C_PWM) ‐ 1.0 ‐ V PWM Input Low Threshold VIL(C_PWM) ‐ 0.8 ‐ V PWM Input Tri‐level High Threshold VTL(C_PWM) ‐ 2.5 ‐‐ V PWM Input Tri‐level Low Threshold VTH(C_PWM) ‐ 2.3 ‐ V PWM Input Current Low IC_PWM VPWM = 0V ‐ 1.0 ‐ mA PWM Input Current High VPWM = 1.8V ‐ 1.0 ‐ mA High‐side Gate Driver Transition Time – Rise tR(HS) 3nF Load, 10% – 90% ‐ 10 ‐ ns Transition Time – Fall tF(HS) 3nF Load, 10% – 90% ‐ 8 ‐ ns Propagation Delay – Turn‐on tPDH(HS) 3nF Load, Adaptive ‐ 19 ‐ ns Propagation Delay – Turn‐off tPDL(HS) 3nF Load ‐ 20 ‐ ns Propagation Delay – Exit Tri‐state tPDTS(HS_en) 3nF Load ‐ 35 ‐ ns Propagation Delay – Enter Tri‐state tPDTS(HS_dis) 3nF Load ‐ 20 ‐ ns Source Current IHS_SOURCE 3nF Load ‐ 2 ‐ A Output Impedance Sourcing RHS_SOURCE Sink Current at 100mA ‐ 1.4 ‐ Ω Sink Current IHS_SINK 3nF Load ‐ 2 ‐ A Output Impedance – Sinking RHS_SINK Sink Current at 100mA ‐ 0.7 ‐ Ω Low‐side Gate Driver Transition Time – Rise tF(LS) 3nF Load, 10% – 90% ‐ 10 ‐ ns Transition Time – Fall tR(LS) 3nF Load, 10% – 90% ‐ 7 ‐ ns

High‐Efficiency 5V MOSFET Gate Driver CHL8505 December 6, 2011 | FINAL | V1.058 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Propagation Delay – Turn‐on tPDH(LS) 3nF Load, Adaptive ‐ 9 ‐ ns Propagation Delay – Turn‐off tPDL(LS) 3nF Load ‐ 25 ‐ ns Propagation Delay – Exit Tri‐state tPDTS(LS_en) 3nF Load ‐ 36 ‐ ns Propagation Delay – Enter Tri‐state tPDTS(LS_dis) 3nF Load ‐ 22 ‐ ns Source Current ILS_SOURCE 3nF Load ‐ 2 ‐ A Output Impedance Sourcing RLS_SOURCE Sink Current at 100mA ‐ 1.5 ‐ Ω Sink Current ILS_SINK 3nF Load ‐ 4 ‐ A Output Impedance – Sinking RLS_SINK Sink Current at 100mA ‐ 0.4 ‐ Ω Note: 1 Guaranteed by design

High‐Efficiency 5V MOSFET Gate Driver CHL8505 December 6, 2011 | FINAL | V1.059 TIMING DIAGRAM Figure 6: IR Active Tri‐Level (ATL) mode PWM, HI_GATE and LO_GATE signals Normal PWM operation Active Tri-level (ATL) PWM operation HI_GATE LO_GATE PWM R(HS) PDTS(HS_en) tPDL(HS) t tF(HS) tF( LS ) tR(LS)tPDL(LS) tPDH(LS) tPDTS(LS_dis) t tPDL(HS) tPDTS(HS_dis) tPDTS(LS_en)

High‐Efficiency 5V MOSFET Gate Driver CHL8505 December 6, 2011 | FINAL | V1.0510 GENERAL DESCRIPTION The CHL8505 is a high efficiency, fast MOSFET driver with large source and sink current capability. It can reliably drive the external high‐ and low‐side N‐channel MOSFETs with large input capacitance at switching frequencies up to 1MHz. The patented IR Active Tri‐Level (ATL) feature allows complete control over enable and disable of both MOSFETs using the PWM input signal from the controller. The timing and voltage levels of ATL are shown in Figure 6. During normal operation the PWM transitions between low and high voltage levels to drive the low‐ and high‐side MOSFETs. The PWM signal falling edge transition to a low voltage threshold initiates the high‐side driver turn off after a short propagation delay, tPDL(HS). The dead time control circuit monitors the HI_GATE and switch voltages to ensure the high‐side MOSFET is turned off before the LO_GATE voltage is allowed to rise to turn on the low‐side MOSFET. The PWM rising edge transition through the high‐side turn on threshold, initiates the turn off of the low‐side MOSFET after a small propagation delay, tPDL(LS). The adaptive dead time circuit provides the appropriate dead time by determining if the falling LO_GATE voltage threshold has been crossed before allowing the HI_GATE voltage to rise and turn on the high‐side MOSFET, tPDH(HS).

High‐Efficiency 5V MOSFET Gate Driver CHL8505 December 6, 2011 | FINAL | V1.0512 This startup also ensures that any undetermined PWM signal levels from a controller in pre‐POR state will not result in high‐ or low‐side MOSFET turn on until the controller is out of its POR. HIGH‐SIDE DRIVER The high‐side driver drives an external floating N‐channel MOSFET which can be switched at 1MHz. An external bootstrap circuit referenced to the SWITCH node, consisting of a boot diode and capacitor is used to bias the external MOSFET gate. When the SWITCH node is at ground, the boot capacitor is charged to near the supply voltage using the boot diode and this stored charge is used to turn on the external MOSFET when the PWM signal goes high. Once the high‐side MOSFET is turned on, the SWITCH voltage raises to the supply voltage and the boot voltage to twice the supply voltage. When the PWM signal goes low, the MOSFET is turned off by pulling the MOSFET gate to the SWITCH voltage. LOW‐SIDE DRIVER The CHL8505 low‐side driver is designed to drive an external N‐channel MOSFET referenced to ground at 1MHz. The low‐side driver is connected internally to the supply voltage to turn the MOSFET on. When the low‐side MOSFET is turned on the SWITCH node is pulled to ground. This allows charging of the boot capacitor to the supply voltage ready to drive the high‐side MOSFET based on the PWM signal level. ADAPTIVE DEAD TIME ADJUSTMENT In a synchronous buck configuration dead time between the turn off of one gate and turn on of the other is necessary to prevent simultaneous conduction of the external MOSFETS. It prevents a shoot‐through condition which would result in a short of the supply voltage to ground. A fixed dead time does not provide optimal performance over a variety of MOSFETs, converter duty cycles and board layouts. The CHL8505 provides an ‘adaptive’ dead time adjustment. This feature minimizes dead time to an optimum duration which allows for maximum efficiency. The ‘break before make’ adaptive design is achieved by monitoring gate and SWITCH voltages to determine OFF status of a MOSFET. It also provides zero‐voltage switching (ZVS) of the low‐ side MOSFET with minimum current conduction through its body‐diode. When the PWM is switching between 1.8V and 0V, its falling edge transition from high to low will turn off the high‐side gate driver. The adaptive dead time circuit monitors the HI_GATE and the SWITCH node voltages during the high‐side MOSFET turn off. When the HI_GATE falls below 1.7V above the SWITCH node potential or the SWITCH node voltage drops below 0.8V the high‐side MOSFET is determined to be turned off and the LO_GATE turn on is initiated. This turns on the external low‐side MOSFET. The rising edge transition of the PWM signal from low to high voltage causes the low‐side gate driver to turn off. The adaptive circuit monitors the voltage at LO_GATE and when it falls below 1.7V, the low‐side MOSFET is determined to be turned off and the high‐side MOSFET turn on is initiated.

High‐Efficiency 5V MOSFET Gate Driver CHL8505 December 6, 2011 | FINAL | V1.0513

APPLICATION INFORMATION

Once the high‐side MOSFET selection is made, the bootstrap circuit can be defined. The integrated boot diode of the CHL8505 reduces the external component count for use in cost and space sensitive designs. For ultra high efficiency designs, an external boot strap diode is recommended. The bootstrap capacitor CBoot stores the charge and provides the voltage required to drive the external high‐ side MOSFET gate. The minimum capacitor value can be defined by: CBoot = QHS MOSFET_gate / ∆VBoot where,  QHS MOSFET_gate is the total gate charge of the high‐side external MOSFET(s)  ∆VBoot is the droop allowed on the boot capacitor voltage (at the high‐side MOSFET gate) A series resistor, 1Ω to 4Ω, may be added to customize the rise time of the high‐side output. Slowing down this output allows setting the phase node rising slew rate and limits the surge current into the boot capacitor on start‐up. SUPPLY DECOUPLING CAPACITOR VCC decoupling to the IR3598 is provided by a 0.1uF bypass capacitor CVcc located close to the supply input pin. A series resistor Rvcc, typically 10Ω, is added in series with the supply voltage to filter high frequency ringing and noise. A 1.0uF or higher capacitor is recommended for the VDRV decoupling capacitor, CDRV. PCB LAYOUT CONSIDERATIONS PCB layout and design is important to driver performance in voltage regulator circuits due to the high current slew rate (di/dt) during MOSFET switching.  Locate all power components in each phase as close to each other as practically possible in order to minimize parasitics and losses, allowing for reasonable airflow.  Input supply decoupling and bootstrap capacitors should be physically located close to their respective IC pins.  High current paths like the gate driver traces should be as wide and short as practically possible.  Trace inductances to the high‐ and low‐side MOSFETs should be minimized.  The ground connection of the IC should be as close as possible to the low‐side MOSFET source.  Use of a copper plane under and around the IC and thermal vias to connect to buried copper layers improves the thermal performance. MOSFET stages should be well bypassed with capacitors placed between the drain of the HIGH‐side MOSFET and the source of the LOW‐side MOSFET.

High‐Efficiency 5V MOSFET Gate Driver CHL8505 December 6, 2011 | FINAL | V1.0515 Data and specifications subject to change without notice. This product will be designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. www.irf.com