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Digital Multi-Phase Buck Controller CHL8225G/8G June 21, 2013 | FINAL | V1.12 1
FEATURES
5-phase & 8-phase dual output PWM Controller with phases flexibly assigned between Loops 1 & 2 Dynamic voltage control by 2-bit parallel interface with Gamer Mode override and Vmax setting Input Voltage Management for up to 3 Input Voltages ICRITICAL Monitor and Phase Current Capture Mode Phase Switching frequency from 200kHz to 1.2MHz IR Efficiency Shaping Features including Variable Gate Drive, Dynamic Phase Control Programmable 1-phase or 2-phase for Light Loads and Active Diode Emulation for Very Light Loads IR Adaptive Transient Algorithm (ATA) minimizes output bulk capacitors and system cost Per-Loop Fault Protection: OVP, UVP, OCP, OTP I2C/SMBus/PMBus system interface for telemetry of Temperature, Voltage, Current & Power for both loops Non-Volatile Memory (NVM) for custom configuration Compatible with IR ATL and 3.3V tri-state Drivers +3.3V supply voltage; 0ºC to 85ºC ambient operation Pb-Free, RoHS, 6x6 40-pin & 8x8 56-pin QFN, MSL2 package
APPLICATIONS
Multiphase GPU systems PIN DIAGRAM SMB_DIO PWM5 VRHOT_ICRIT# VRTN RCSM ISEN5 ISEN4 ISEN3 VSEN SMB_CLK PWM4 VR_READY_L1 IRTN3 IRTN4 IRTN5 RCSP TSEN VIDSEL0 PWM3 ENABLE V18A RRES VCC ISEN2 ISEN1 IRTN1 IRTN2 PWM2 PWM1 RCSM_L2 RCSP_L2 VAR_GATE VIDSEL1 VIDSEL_L2 VINSEN_AUX1 VR_READY_L2 VCC VINSEN VRTN_L2 VSEN_L2
41 GND
40 Pin 6x6 QFN
Figure 1: CHL8225G Package Top View
DESCRIPTION
The CHL8225G/8G are dual-loop, digital multi-phase buck controllers. The CHL8225G drives up to 5 phases and the CHL8228G drives up to 8 phases. They feature Input Voltage Management allowing up to 3 input voltages to be monitored to ensure adequate power is delivered to the load. Dynamic voltage control is provided by 4 registers which are programmed through I2C/SMBus/PMBus and then selected using a 2-bit parallel bus for fast access. The CHL8225G/8G includes the IR Efficiency Shaping Technology to deliver exceptional efficiency at minimum cost across the entire load range. IR Variable Gate Drive optimizes the MOSFET gate drive voltage as a function of real-time load current. IR Dynamic Phase Control adds and drops phases based upon load current. The CHL8225G/8G can be configured to enter 1-phase operation and active diode emulation based upon load current or by command. IR’s unique Adaptive Transient Algorithm (ATA), based on proprietary non-linear digital PWM algorithms, minimizes output bulk capacitors. The I2C/PMBus interface can communicate with up to 16 CHL8225G/8G-based VR loops. Device configuration and fault parameters are defined using the IR Digital Power Design Center (DPDC) GUI and stored in on-chip NVM. The CHL8225G/8G provides extensive OVP, UVP, OCP and OTP fault protection and includes thermistor based temperature sensing with VRHOT signal. The CHL8225G/8G includes numerous features like register diagnostics for fast design cycles and platform differentiation, simplifying VRD design and enabling fastest time-to-market with its “set-and-forget” methodology. SMB_DIO PWM5 ISEN6 ENABLE VRTN RCSM ISEN5 ISEN4 ISEN3 PWM6 VSEN SMB_CLK PWM4VR_READY_L1 IRTN3 IRTN4 IRTN6 IRTN5 RCSP TSEN VRHOT_ICRIT# PWM3 VINSEN VIDSEL1_L2 V18A RRES VCC ISEN2 ISEN1 IRTN1 IRTN2 PWM2 PWM1 VINSEN_AUX1 RCSM_L2 RCSP_L2 VBOOT VRHOT2 VMAX VIDSEL0 VIDSEL1 VIDSEL0_L2 VR_READY_L2 VCC VINSEN_AUX2 PWM7 VRTN_L2 VSEN_L2
57 GND
56 Pin 8x8 QFN
55 5153 4854 5052 474956 46 45 4344 16 2018 2317 2119 242215 25 26 2827 ISEN8 EN_L2 TSEN2 VAR_GATE PWM8 ISEN7 IRTN7 IRTN8 Figure 2: CHL8228G Package Top View
Digital Multi-Phase Buck Controller CHL8225G/8G June 21, 2013 | FINAL | V1.12 2
ORDERING INFORMATION
SMB_DIO PWM5 VRHOT_ICRIT# VRTN RCSM ISEN5 ISEN4 ISEN3 VSEN SMB_CLK PWM4 VR_READY_L1 IRTN3 IRTN4 IRTN5 RCSP TSEN VIDSEL0 PWM3 ENABLE V18A RRES VCC ISEN2 ISEN1 IRTN1 IRTN2 PWM2 PWM1 RCSM_L2 RCSP_L2 VAR_GATE VIDSEL1 VIDSEL_L2 VINSEN_AUX1 VR_READY_L2 VCC VINSEN VRTN_L2 VSEN_L2 Figure 3: CHL8225G Top View Enlarged Package Packing Qty Part Number QFN T=3000 TY=4900 CHL8225G-00CRT CHL8225G-00CRTY QFN T=3000 CHL8225G-xxCRT1 QFN T=3000 TY=2600 CHL8228G-00CRT CHL8228G-00CRTY QFN T=3000 CHL8228G-xxCRT1 Notes: 1. “xx” indicates customer specific configuration file. SMB_DIO PWM5 ISEN6 ENABLE VRTN RCSM ISEN5 ISEN4 ISEN3 PWM6 VSEN SMB_CLK PWM4VR_READY_L1 IRTN3 IRTN4 IRTN6 IRTN5 RCSP TSEN VRHOT_ICRIT# PWM3 VINSEN VIDSEL1_L2 V18A RRES VCC ISEN2 ISEN1 IRTN1 IRTN2 PWM2 PWM1 VINSEN_AUX1 RCSM_L2 RCSP_L2 VBOOT VRHOT2 VMAX VIDSEL0 VIDSEL1 VIDSEL0_L2 VR_READY_L2 VCC VINSEN_AUX2 PWM7 VRTN_L2 VSEN_L2 55 5153 4854 5052 474956 46 45 4344 16 2018 2317 2119 242215 25 26 2827 ISEN8 EN_L2 TSEN2 VAR_GATE PWM8 ISEN7 IRTN7 IRTN8 Figure 4: CHL8228G Top View Enlarged T – Tape & Reel / TY - Tray R – Package Type (QFN) C – Operating Temperature (Commercial Standard) xx – Configuration File Part Number 5: CHL8225G 8: CHL8228G
Digital Multi-Phase Buck Controller CHL8225G/8G June 21, 2013 | FINAL | V1.12 3 FUNCTIONAL BLOCK DIAGRAM TSEN VINSEN Voltage ADC VSEN VRTN Control and Monitoring Vout1_Error Vout2_Error PWM1 PWM2 PWM3 PWM4 PWM5 Reference, Oscillator, State Control, Interfaces, Registers and NVM VIDSEL1 ADC Clocks MUX Clocks Phase_Period_1 Phase_Period_2 V3_3 Iout Vin Temp Fault Bus System Clock Iout Vin Temp Vout Fault Bus System Clock VID_1 VID_2 Current ADC Mode Control VAR_GATE LDO VCC 1.8V V18A VIDSEL0 VIDSEL0_L2 VRHOT_ICRIT# VR_READY_L1 VR_READY_L2 Phase_ Period_1 Phase_ Period_2 RRES RCSP RSCM AFE_1 VID_1 SMB_DIO SMB_CLK VINSEN_AUX1 VINSEN_AUX2 (CHL8228G only) VMAXVBOOT Only for CHL8228G Only for CHL8228G VRHOT2 EN PWM6 PWM7 PWM8 Only for CHL8228G PWM Generator ISEN1 IRTN1 ISENx IRTNx ISENy IRTNy ISENz IRTNz Σ ITOT_1 ITOT_2 IP1 IPx IPy Σ IPz ... ... ... ... ... ... CHL8225G CHL8228G x 3 4 y 4 5 z 5 8 EN_L2 VIDSEL1_L2 VSEN_L2 VRTN_L2 RCSP_L2 RSCM_L2 AFE_2 VID_2 ITOT_2 IP5 IP6 IP8 ... ... Only for CHL8228G TSEN2 (CHL8228G only) Monitor ADC IP1 Figure 5: CHL8225G & CHL8228G Functional Block Diagram