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CH8398A

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TRUE-COLOR CHRONDAC WITH 16-BIT INTERFACE

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e CH8398A CHRONTEL True-Color ChronDAC™ with 16-bit Interface Te UU RSRERInemne ee Features Description * 16-bit pixel bus interface The CH8398A ChronDAC™ integrates two * On-chip clock doubler programmable PLLs, a triple 256 x 6-bit palette RAM, . hi d 8-bit 110/135 MHz DAC. and a triple 8-bit 110/135 MHz video DAC. The video ae igh Spee : A S clock PLL provides 16 programmable frequencies, and . e high speed 256 x 6-bit color palette RAMs th . hb . . ie memory clock PLL provides 8 programmable * Compatible with ATT20C498 display modes frequencies. * MIX-COLOR®: true on-the-fly mode switching The CH8398A pixel bus is 16 bits, twice the bandwidth * 16.7M, 64K, 32K, and 256 color modes of an 8-bit LUTDAC. The on-chip clock doubler + Supports 128/256 pseudo color, HICOLOR™2, allows CH8398A to support more colors with higher 64K bypass, 16.7M bypass, XGA™ mode 2, and resolution while maintaining a lower pixel transfer rate. MIX-COLOR® Upon power up, the video clock is preset to * Intemal/external voltage reference or extemal current 3 39> MHz. and memory clock is preset to 40 MHz. re erence . After power up, video BIOS or driver software can * Drives singly or doubly terminated 75 © loads initialize the PLL RAM entries to the desired values. * [register for software identification oo. MIX-COLOR® mode provides the simultaneous + Power down features for “Green PC” applications display of maximum spatial resolution and color depth + Anti-sparkle circuitry within a single bitmapped frame, efficiently utilizing + Dual-programmable 135 MHz PLL clocks memory. True on-the-fly mode switching occurs on a * On-chip loop filters for PLL clocks pixel by pixel basis, allowing 178726 pseudo-color . Pi c ‘S-Th 170: mode to be mixed wit color 5-6-5 or color 5- : eee eee ae Snes Pee 5-5 bypass. Mixed mode switching can be controlled ‘Ow power technology in 68-pin by hardware or software, easing design * SV supply implementation. CH8398A is fully compatible with VGA, VESA, Super-VGA, XGA™, TARGA™, 8514, and other non- standard frequencies, while providing many other enhanced features. FS[3:0] STROBE VOD Xt XO/FIN AVDD y oN — ‘ RS[3:0] PI a VCLK oe wr RAM VREF P[15:0] ! 256x6 — IREF msw | ik RAM MUX >g— [DAC > 10R BLANK ° | 9 RAM MUX DAC 10G PCLK x t COMP | SENSE* GND AGND Figure 1: Block Diagram @™@ 9004133 oooc405 44? a

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—_—- OSM FTOVIOA MPU Access SR 7 Access to the Palette RAM Ne eee eee eee cece n nett eee e tet e tee eee ees 34 Palette RAM Data Organization Se: Ff Electrical Specifications CN” | Absolute Maximum Ratings Fennec eect e eee e eee e teen ett eeececesee ee Al Analog Outputs Se”) Strobe Timing Seen cece eee ete t eee teen nse en eee 45 PC Board Layout Considerations EC Supply Decoupling SN” 1 Typical Connection Using External Current Reference Sn + MIX-COLOR is a registered trademark of Chrontel ChronDAC is a trademark of Chrontel * HICOLOR is a trademark of Sierra Semiconductor; TARGA is a trademark of TRUEVISION; XGA and PS/2 are trademarks of IBM Corporation; and PixMix is a trademark of SGS-Thomson + Windows is a registered trademark of Microsoft Corporation @™ 9004133 co0o407 2l1T

Sok ,ae82a8e5 7% 0% PEEEC I 200s tao es Siglielisleigiaioiaiaisioioioisiols GND (J 10 60 [J] GND BLANK* [1] 14 O 59 Pq) Do (Jj 12 58) P(6) D1 (413 57 [7 P(S) o2 (14 56 [) Pi) ps (15 551] P(3) p4 (J 16 5417) P(2) ps (17 CHRONTEL 53 P(t) De C] 18 5210) P(o) 07 (j19 CH8398A 51) VREF wr (J 20 50 [) RS2 Rso (j 21 49 [) IREF RS1 (J 22 48 [] RSET P(14) C4 23 47 [) FS3 msw [| 24 46 1] Fs2 P(15) (J 25 45 {J Fs1 NC (J 26 441) Fso RRRSSSSSSSRERSSSEVEY agezgeeeego2ssegesa > Z£GO-==Os0 qitig Figure 2: CH8398A M@@ 9004133 o000408 15b mm

——, AA OOOO Table 1 * Pin Description [Pint [Symbol | Type ] Name Description 1, 4, 23, 25, | P12, P13, P14, Pixel. TTL compatible. Pixel data is latched on the rising edge of PCLK. 52-59, | P15, PO-P7, Pseudo-color mode: pixel data is used as an address map to color palette RAM. 64-67 P8-P11 Bypass color mode: pixel data represents actual color and directly drives DACs. | 241 | AGND [P| Analog Ground. AGND pins must be connected to system ground. | 3,42 | AVDD_ | P| Analog Power. AVDD pins must be connected to +5V. Read (Active Low). TTL compatible. RS[3:0] data is latched and transferred from selected register to data bus on falling edge of RD*. xl Crystal Oscillator. 14.318 MHz crystal or connect to GND if XO/FINIs connected to an external reference clock. 7 XO/ FIN 1/0 | Crystal Oscillator / External Frequency. 14.318 MHz crystal or external reference clock input. 827,62 | VDD [| P___| Digital Power. VDD pins must be connected to +5V. py 9 =| vciK [0 | Video Clock. TTL compatible. 28.322 MHz upon power up. 10, 36, 37, ; oP Digital Ground. GND pins must be connected to system ground. 1 BLANK* Blank (Active Low). TTL compatible. BLANK‘ is latched on the rising edge of PCLK. When asserted, the analog outputs are tumed off and the pixel inputs are ignored. 12-19 Data Bus. TTL compatible. Bi-directional data bus. Write (Active Low). TTL compatible. RS[3:0] data is latched on falling edge of WR’. [7:0] data is latched on rising edge of WR*. RSO, RS1, Register Select. TTL compatible. RS[3:0] data is latched on falling edge of RD* RS3, RS2 or WR*. RS[3:0] inputs determine which internal register to access. RS3 pin is internally pulled up to Voo. MSW Mode Switch. TTL compatible with intemal pull-down resistor. MSWis latched on the rising edge of PCLK. MSW input enables on-the-fly mode switching between primary and secondary modes. 26,28-34] =NC — [ — | NoConnect. Unconnected pins. 38, 39,40 | IOR, 1OG, 108 Color Signals Output. Red, green, and blue DAC outputs, high impedance current sources capable of driving singly or doubly terminated 75 Q load directly. 43 STROBE Strobe. TTL compatible with internal pull-up resistor. FS[3:0] inputs are latched on the falling edge of STROBE. The STROBE control pin should be held at Vop or left open for direct pass-through of FS[3:0]. For further details, please refer to Figure 22 on page 45. 44-47 External Video Clock Select. TTL compatible with internal pull-down resistor. FS[3:0] inputs are bit-wise “OR"ed with internal register CSR [3:0]. A Reference Resistor. This pin should be connected through an extemal 147 Q 1% resistor to GND. DAC output current levels are controlled by this resistor. See Note 2 below. ; 49 | IREF Current Reference. External current reference input. 51 VREF A Voltage Reference. If using an external voltage source, supply this input with a 1.23V reference. ; 63 [| PCLK | 1 __| Pixel Clock. TTL compatible, Pixel data is latched on the rising edge of PCLK. | 61 | MCLK | 0 [Memory Clock. TTL compatible. 40 MHz upon power up. Sense (Active Low). TTL compatible. Monitor detect signal. SENSE* is logical 0 if one or more of the IOR, IOG, and IOB outputs has exceeded the intemal voltage reference level of 340 mV. Note 1: Note 2: I Input signal where O Output signal + Irs is full-scale output current 1/0 Bi-directional signal VrEF + VREF is the voltage reference with value 1.23V P Power pins Is =— x21 + RSETis the resistor connected between the RSET pin and A Analog signal Rser ground, typical value is 147 W + 1% eee mm 9004133 oooo4o9 Oce a

a oSSSSSSSSSSSSSsSssssFssssSseSeSSSSSSSSSSSSSSSSSSSSSSSSSSe Comparison of CH8398 and CH8398A The following changes have been made in the CH8398A: | Bee FEATURES 3 2, See CHe398 mal CHESSaAR |g _ | RS2 Bealted fo access PLU RAM (eace'33) atl Seeyeemes |e ae _ REL Daal N Values este roe 9): a aes eee a ||| NPLL-RAM Locations 0 and-1.(page 96); == S| fFlard'Wired =| “Initialized l= _|[Iohanges in AUXR definitions (page $2) 32s Sis) eS Note: Changes have been highlighted on pages indicated . Display Modes Chrontel CH8398A offers two basic color modes: pseudo and bypass. Pseudo-color mode: _ Pixel address (8-bit), after being logically “AND”ed with the pixel Read Mask Register (RMR), is used to address all red, green, and blue palette RAM. Bypass color mode: Pixel data is used to drive inputs of the DACs directly, bypassing the palette RAM and the RMR. CH8398A provides 14 different display modes, each consisting of a primary and secondary mode. The pixel- by-pixel mode switching between primary and secondary modes is accomplished on-the-fly, and can be achieved through either hardware or software control. [> 9004133 c000410 604

eS NNO, Table 2 * Summary of Display Modes [Modelcrer4][__MSW=0,PRIMARYMODE [Primary Mode Description [Colors] [or | 0000 | “sBiPIC [SB bpp, 1 pixcladcress, TPCIK ace | Ebtpseudo_——S—~Sd 2h [i= [0001 |“ 7581P1C | 15 bpp, 1 piel data, 1PCLK cycle | 15-it 655 bypass | ak] [zt | 0010 | aB2P1C — [bpp 2 pixel adcresses, 1 PCLK cycle |e-bt pseudo] 56] [3° [0011 | 16B1P1C [76 bpp, t pict data, 1PCLK cycle | 16-bit 6-5 bypass | ea] [4] 0100 ]as1P2C (4 +4] 8 bpp, {pixel adcress, 2 PCLK cycles | 8-bit pseudo (4+ 4 piel data wanwfe) | 256] [s_| 0101 | 24BtP20 | 24bpp, t piel deta, 2PCLK cycles [2408-88 bypass +d Te7i] [er _[ 0110 | 168126 | 16 bpp, 1 pal data, 2PCLK eycies | Te-bRSG5 bypass | 6a | [e*| 1000 [SB1P2C (4+ 4)] 8 bpp, 7 pixel address, 2 PCLK cycios_|8-bit pseudo (4+ 4 pixel data Fanster) | 256 | [a*_| 1001 [@B1P2c (6+ 0)|& bpp 1 pixel address, 2 PCLK cycies_| S-bt pseudo (@ + 0 pixel data transfer) | 256 | [At_[ toro | s82Pic__[@ bpp, 2 pixel addresses, TPCLK cycle | MIX-COLOR®, @-bitpseudo | 256 | [Br _| 1011 | 24B2P3C__|24 bpp, 2pixel data, SPCLK cycles [24biteES bypass SC ‘16.7 [e_| 1100 | 18B1P2C_[15bpp, i pixeldata, 2PCLK cycles | 15-bitSSSbypass «| RK | por [riot | se2Pic | @ bpp, 2 pixel addresses, TPCLK cycle | MIX-COLOR®, S-bitpseudo =| «256 | PET IMode[oniral| ____ MSW=1, SECONDARYMODE | __ Secondary Mode Description [Gators [ = | 0000 | TEBIP1C [Tebpp, 1 pixel data, 1 POLK cycle | T6565 bypass | bak | [| 0001 | e8tP1C [8 bpp, Tpixel aderess, TPOLK cycle | @bitpseudo | 56 | [2 [0010 | eB2P1C | 8 bpp, 2 piel addresses, 1 POLK cycle B-bitpseudo | 286] | 3 [0011 | eB1F1C[@ bpp, 1 piel address, 1 PCLK cycle | e-bit pseudo | 256 ] | 4 [0100 | 24BtP2c [24 bpp, 1 pixel data, 2 POLK cycles | 24-bit 6-8-8 bypass | 16.7 [S| oro | 1e81P26 | 16 bpp, piel data, 2 POLK cycies | 16-65-65 bypass | eax | [-e* | 0110 | 24BiP2c [26 bpp, 1 pil data, 2PCLK cycles | 24-bit 88 bypass | 76.7] | * | 1000 | 1681P2C | 16 bpp, Tinel data, 2PCLK cycles | 16-6565 bypass | 64K | | a | toot | “2481626 | 24 bpp, 1 piel data, 2PCLK cycies | 24-08-68 bypass | 16.7 [ar [1010 [158116 | 15 bpp. pixel data, 1 POLK cycle | MIX-COLOR@, 1&R5-S-S bypass | 22K | [-c| 1100 [a81P2C (4 + 4)| 8 bpp, t pixel address, ZPCLK cycles | Sbit pseudo (4 + 4 pixel data vansfer) | 256 | [or [rior [168110 [16 bpp, 1 piel data, 1 POLK cycle | MIX-COLOR®, T6-bit-6-Sbypass __| 64K | Note: bpp = bits per pixel + = on-chip clock doubler enabled * = ATT20C498 compatible mode wm 9004133 0000411 740

Display Modes (continued) See Table 2 on page 7 for detailed pixel data organization. Mode 0 Primary Mode: 8BIPIC: 8 bpp, 1 pixel address, 1 PCLK cycle, 256 colors Pixel address for the red, green, and blue color palette is latched on the rising edge of PCLK. Palette RAM contains 256 colors of 256K possible colors (6 bits each for the IOR, IOG, and IOB outputs). Pseudo color pixel address (P[7:0]) is then bit-wise “AND”ed with the pixel RMR. Following is the 8B1P1C pixel address transfer format: [Prsi [ Pt4) | Prisi [Pray] Pra] Prior] Pret | Pre) [Pet | Pre | PIs | Pel | Pe | Pe] Pn] Pi | [xx xxx xx x [p76 Ps Pa P32 PT PO | Note: _ bpp=bits per pixel X= unused bit P{i] = pixel input pin P[7:0] = pseudo color pixel address Secondary Mode: 16B1P1C: 16 bpp (5-6-5), 1 pixel data, 1 PCLK cycle, 64K colors Pixel data is latched on the rising edge of PCLK. Pixel data is organized as 5 bits of color information for red and blue, and 6 bits of color information for the green color palette. For further information, please refer to Figure 6 on page 20. Following is the 16B1P1C (5-6-5) pixel data transfer format: Pers) | Pca) [ Pes) [ Peta} [Pray | Prva} | Prey | Pred [Pi T Pre! | Pel | Plat [P| Pre] Pr | PIO) Note: Lowest two or three bits of the DAC inputs are padded with zeros bpp = bits per pixel P[i] = pixel input pin B[7:3] = blue pixel data R[7:3] = red pixel data G[7:2] = green pixel data @™® 9004133 oo00412e ba?

Display Modes (continued) Mode 1 Primary Mode: 15BIP1C: 15 bpp (5-5-5), 1 pixel data, 1 PCLK cycle, 32K colors Pixel data is latched on the rising edge of PCLK. Pixel data is organized as 5 bits of color information each for the red, green, and blue color palette. For further information, please refer to Figure 5 on page 20. Following is the 15B1P1C (5-5-5) pixel data transfer format: [ Pris) | Pea} | Pts) ] Prs2) | Peay | Peto] Pre) | Piel | Pr | Pret | Pist [ Pra) | Pel [Pri | Pra | Pol | Note: Lowest three bits of the DAC inputs are padded with zeros bpp = bits per pixel X = unused bit P{i] = pixel input pin R[7:3] = red pixel data G[7:3] = green pixel data B[7:3] = blue pixel data Secondary Mode: 8BiP1C: 8 bpp, | pixel address, 1 PCLK cycle, 256 colors Pixel address for the red, green, and blue color palette is latched on the rising edge of PCLK. Palette RAM contains 256 colors of 256K possible colors (6 bits each for the IOR, IOG, and IOB outputs). Pseudo color pixel address (P[7:0]) is then bit-wise “AND” ed with the pixel RMR. Following is the 8BIP1C pixel address transfer format: [ Pt18) | Pea) | Peasy | Prt2) | Petty [ Peon] Piel | Pre) [Pra | Pre | Pest | Pra) | Pest [Pre [Pr | Pro] Note: bpp = bits per pixel X = unused bit P[i] = pixel input pin P[7:0] = pseudo color pixel address mm 9004133 0000413 513 a

Display Modes (continued) Mode 2 Primary / : Secondary Modes: 8B2P1C: 8 bpp, 2 pixel addresses, 1 PCLK cycle, 256 colors Pixel addresses for the red, green, and blue color palette are latched on the rising edge of PCLK. Palette RAM contains 256 colors of 256K. Possible colors (6 bits each for the IOR, IOG, and IOB outputs). Pseudo color pixel addresses (P[7:0]) are then bit-wise “AND”ed with the RMR. Following is the 8B2P1C pixel address transfer format: prey | Ptval | irs} [Peta] [PLATT Prvor | PIL | Pre! | PO | Piel] PL] Pl] P| Pe PT] PIT] Note: Internal clock doubler enabled to produce twice the pixel resolution per PCLK period bpp = bits per pixel P{i] = pixel input pin P{7:0] = pseudo color pixei address Mode 3 Primary Mode: 16B1P1C: 16 bpp (5-6-5), 1 pixel data, 1 PCLK cycle, 64K colors Pixel data is latched on the rising edge of PCLK. Pixel data is organized as 5 bits of color information for red and blue, and 6 bits of color information for the green color palette. For further information, please refer to Figure 6 on page 20. Following is the 16B1P1C (5-6-5) pixel data transfer format: LPrvsi | Piva [ Prisi] Prat Pra evo] Pre | PRT] PI | PL] PL] Pa | PR] Pe P| PIT [Rr 6 RS Rs RS [G7 GS GS__Gé__G3__Gz | BY B68 Ba 3 | Note: — Lowest two or three bits of the DAC inputs are padded with zeros bpp = bits per pixel ’ P{i] = pixel input pin BI[7:3] = blue pixel data R[7:3] = red pixel data G{7:2] = green pixel data Secondary Mode: 8BIPIC: 8 bpp, | pixel address, 1 PCLK cycle, 256 colors Pixel address for the red, green, and blue color palette is latched on the rising edge of PCLK. Palette RAM contains 256 colors of 256K possible colors (6 bits each for the TOR, IOG, and IOB outputs). Pseudo color pixel address (P[7:0]) is then bit-wise “AND” ed with the pixel RMR. Following is the 8B1P1C pixel address transfer format: Pus) [Prva [Prvsi[ Prvai [Pay] PrAOr | Le) | Pre | PI | Pe] PL] PM] P| PT PT | Pa] [xxx xx x XX [7s Ps Pa PPP PO Note: bpp = bits per pixel X = unused bit P{i] = pixel input pin P[7:0] = pseudo color pixel address 10 Rev. 1.2, 5/12/95 mm 9004133 0000424 457 a

= SSSA Display Modes (continued) Mode 4 Primary Mode: 8B1P2C: 8 bpp (4 +4), 1 pixel address, 2 PCLK cycles, 256 colors Pixel address for the red, green, and blue color palette is latched on every two consecutive rising edges of PCLK. Palette RAM contains 256 colors of 256K possible colors (6 bits each for the IOR, IOG, and IOB outputs). Pseudo color pixel address (P[7:0]) is then bit-wise “AND” ed with the RMR. Following is the 8B1P2C (4 + 4) pixel address transfer: PPrisi [Pisa] | Prts}] PrtZ} | Pca] Peso] Pre) | Pre) | Pr | Pre | Pts) [Prat | PIS | Pret] PL | PIO | [fx x x x xX Xx xX X[xX x x XxX] Po PI POT [eng [XXX XXX XOX XOX SP PP Note: bpp = bits per pixel X= unused bit P{i] = pixel input pin Secondary Mode: 24B1P2C: 24 bpp (8-8-8), 1 pixel data, 2 PCLK cycles, 16.7M colors Pixel data is latched on every two consecutive rising edges of PCLK. Pixel data is organized as 8 bits of color information each for the red, green, and blue color palette. Following is the 24B1P2C (8-8-8) pixel data transfer format: fPrisi[ Prva | Ps3) | Prs2i [Pest cto] Pre | Peel | Pra | Pre | Pest | Pra [esi | Prat] Pe | PCO | [it | cr G6 G5 Ga G3 G2 Gi Go| 87 Bs 65 e4 B3 82 6180 | [ang [XXX XK XOX OX CPR _RG RS RA RR RT| Note: bpp = bits per pixel X = unused bit P{i] = pixel input pin R[7:0] = red pixel data G[7:0] = green pixel data B[7:0] = blue pixel data Ist = first pixel data latched in 2nd = second pixel data latched Rev. 1.2, 5/12/95 il M$ 9004133 0000415 396 mt

Display Modes (continued) Mode 5 Primary Mode: 24B1P2C: 24 bpp (8-8-8), 1 pixel data, 2 PCLK cycles, 16.7M colors Pixel data is latched on every two consecutive rising edges of PCLK. Pixel data is organized as 8 bits of color information each for the red, green, and blue color palette. Following is the 24B1P2C (8-8-8) pixel data transfer format: PUSIT Pra] PLAS} | PLia} | PLAT Peto} Piel | Pre) | Pe | Pre | Pre | ral | Pest | Pre] Pe | PIT | [ist [G7 G6 G5 G4 G3 G2 Gi GO[ 687 B66 BS B4 83 62 Bi 60 Note: bpp = bits per pixel X = unused bit Pi] = pixel input pin R[7:0] = red pixel data G[7:0] = green pixel data B[7:0] = blue pixel data Ist = first pixel data latched in 2nd = second pixel data latched Secondary Mode: 16B1P2C: 16 bpp (5-6-5), 1 pixel data, 2 PCLK cycles, 64K colors Pixel data is latched on every two consecutive rising edges of PCLK. Pixel data is organized as 5 bits of color information for red and blue, and 6 bits of color information for the green color palette. For further information, please refer to Figure 6 on page 20. Following is the 16B1P2C (5-6-5) pixel data transfer format: [ Prisi] Pt) | Pris) | Pe121 | Pt1 ty] Pe1o}] Pest | Peel | Pra | Piel | Pre) | Pra | rst | Prt] Pr | Prod | [px x x x x x x Xx Land] xX xX xX xX XX XX PR? RE ORS —R4 SOR | G7 —CGSSC*CGSS Note: Lowest two or three bits of the DAC inputs are padded with zeros bpp = bits per pixel X= unused bit P[i} = pixel input pin R[7:0] = red pixel data G[7:0] = green pixel data B[7:0] = blue pixel data Ist = first pixel data latched in 2nd = second pixel data latched 12 Rev. 1.2, 5/12/95 @™@ 9004133 GO0041b 222

$$ SSsSSsSsSSSSSSSSSSSSSSSSSSMESOEN Display Modes (continued) Mode 6 Primary Mode: 16B1P2C: 16 bpp (5-6-5), 1 pixel data, 2 PCLK cycles, 64K colors Pixel data is latched on every two consecutive rising edges of PCLK. Pixel data is organized as 5 bits of color information for red and blue, and 6 bits of color information for the green color palette. For further information, please refer to Figure 6 on page 20. Following is the 16B1P2C (5-6-5) pixel data transfer format: Prisi| Pra) Pisa) | Prva} Peay | Peo} Pts) | Pre) | Pi | Pret | Pel | Prat | Pest | Pray] PI | Prot | [it [x xX xX x x x x xX [Gs G3 G2] 87 56 65 6463 | [and [ XXX XXX XX RY _R6__RS__RA__-RS] G7 Ga G8 | Note: Lowest two or three bits of the DAC inputs are padded with zeros bpp = bits per pixel X = unused bit P[i] = pixel input pin R[7:3] = red pixel data G[7:2] = green pixel data B[7:3] = blue pixel data Ist = first pixel data latched in 2nd = second pixel data latched Secondary Mode: 24B1P2C: 24 bpp (8-8-8), 1 pixel data, 2 PCLK cycles, 16.7M colors Pixel data is latched on every two consecutive rising edges of PCLK. Pixel data is organized as 8 bits of color information each for the red, green, and blue color palette. Following is the 24B1P2C (8-8-8) pixel data transfer format: ervey PLA [PUA PA PO] POT] P| re P| PL] eT | Pal | P| P| PT | P| [ist [cr G5 Gs G4 G3 G2_Gi_Go| 87 86 85 4 63 82 81 __B0 [ang [Xx XX XXX _ xX [R7_R6__RER4_RS_RZ RT RO] Note: —_bpp = bits per pixel X = unused bit P[i] = pixel input pin R{7:0] = red pixel data G[7:0] = green pixel data B[7:0] = blue pixel data Ist = first pixel data latched in 2nd = second pixel data latched Mode 7 Primary / Secondary Modes: 24B1P3C: 24 bpp (8-8-8), 1 pixel data, 3 PCLK cycles, 16.7M colors Pixel data is latched on every three consecutive rising edges of PCLK. Pixel data is organized as 8 bits of color information each for the red, green, and blue color palette. Following is the 24B1P3C (8-8-8) pixel data transfer format: [Pre [Pra PRS] Presper] Pra] Pre | | P| Pe Pe PT PO | P| [atx x x x xX x x Xx /|87 66 65 64 B63 82 61 BO [ana [Xxx XOXO SOX * e7_ca Gas G2 Gt GO Note: _ bpp = bits per pixel X = unused bit P[i] = pixel input pin R[7:0] = red pixel data G(7:0] = green pixel data B[7:0] = blue pixel data Ist = first pixel data latched in 2nd = second pixel data latched 3rd = third pixel data latched Rey. 1.2, 5/12/95 13 mB 9004133 0000417 165 mm TT 44adat4é#ée#eénnnn

Display Modes (continued) Mode 8 Primary Mode: 8B1P2C: 8 bpp (4 + 4), 1 pixel address, 2 PCLK cycles, 256 colors Pixel address for the red, green, and blue color palette is latched on every two consecutive rising edges of PCLK. Palette RAM contains 256 colors of 256K. possible colors (6 bits each for the IOR, IOG, and IOB outputs). Pseudo color pixel address (P[7:0}) is then bit-wise “AND”ed with the RMR. Following is the 8B1P2C (4 + 4) pixel address transfer format: I OO 8 eS SO [ang xX XXX KKK KX PP Note: bpp = bits per pixel X = unused bit P[i] = pixel input pin Secondary Mode: 16B1P2C: 16 bpp (5-6-5), 1 pixel data, 2 PCLK cycles, 64K colors Pixel data is latched on every two consecutive rising edges of PCLK. Pixel data is organized as 5 bits of color information for red and blue, and 6 bits of color information for the green color palette. For further information, please refer to Figure 6 on page 20. Following is the 16B1P2C (5-6-5) pixel data transfer format: [ Prisy | Pray | Presi] Pray] Prvay| Priory Prey Pre [Pra | Peel | PIL | Pel | P| PA] PM] PLOT | Patp x x x x xX xX xX x [Gs G3 G2 | 87 BG Bs ba [ant] XX XXX XOX XP RY_ RRS Re] G7 Go Note: — Lowest two or three bits of the DAC inputs are padded with zeros bpp = bits per pixel X = unused bit P[i] = pixel input pin R[7:3] = red pixel data G[7:2] = green pixel data BY7:3] = blue pixel data Ist = first pixel data latched in 2nd = second pixel data latched 14 Rev. 1.2, 5/12/95 M@™ 9004133 0000418 OTS | Neen nene een

———$ SSS IO Display Modes (continued) Mode 9 Primary Mode: 8B1P2C: 8 bpp (8 + 0), 1 pixel address, 2 PCLK cycles, 256 colors Pixel address for the red, green, and blue color palette is latched on every two consecutive rising edges of PCLK. Palette RAM contains 256 colors of 256K possible colors (6 bits each for the IOR, IOG, and IOB outputs). Pseudo color pixel address (P[7:0]) is then bit-wise “AND” ed with the RMR. Following is the 8B1P2C (8 + 0) pixel address transfer format: LPrisi Pra) Pes} [ Prva} Pray] Prton] Prey | Pre) | Pr | Pre) | POI | PLT | PI] Pri] Pr | PIO | [and [ XX XXX XXX SOS” Note: bpp = bits per pixel X=unused bit P{i} = pixel input pin P[7:0] = pseudo color pixel address Ist = first pixel data latched in 2nd = second pixel data latched Secondary Mode: 24B1P2C: 24 bpp (8-8-8), 1 pixel data, 2 PCLK cycles, 16.7M colors Pixel data is latched on every two consecutive rising edges of PCLK. Pixel data is organized as 8 bits of color information each for the red, green, and blue color palette. Following is the 24B1P2C (8-8-8) pixel data transfer format: Push Pita) [Pts] Priai[ Petty] Prva] Pret [ Pre) | Prat | Pre! | Pel | Pll | PRI] Peel] Pm | Pro | [it [er Gs 5 G4 G3 G2 Gi_GO| 876685 Bs 63 82 BI BO | [ang [XXX XK XXX PR _ RSS RAR RRR Note: bpp = bits per pixel X= unused bit P{i] = pixel input pin R[7:0] = red pixel data G[7:0] = green pixel data B[7:0] = blue pixel data Ist = first pixel data latched in 2nd = second pixel data latched Rev. 1.2, 5/12/95 15 @™ 9004133 0000415 T3L a

EEE EE OOO, ,OG,G,QO OO CHRONTEL OT Display Modes (continued) Mode A Primary Mode: 8B2P1C: 8 bpp, 2 pixel addresses, 1 PCLK cycle, 256 colors Pixel addresses for the red, green, and blue color palette are latched on the rising edge of PCLK. Palette RAM contains 256 colors of 256K possible colors (6 bits each for the IOR, IOG, and IOB outputs). Pseudo color pixel addresses (P[7:0]) are then bit-wise “AND”ed with the RMR. Following is the 8B2P1C pixel address transfer format: Peasy | Prva) [Pts [Prva | tia) | Pron] Pri T Pret | Prd | Pre | Ptsl | Peal | P| PR] Pe | PPO | Note: Intemal clock doubler enabled to produce twice the pixel resolution per PCLK period . bpp = bits per pixel P{i) = pixel input pin P[7:0] = pseudo color pixel address Secondary Mode: 15B1P1C: 15 bpp (5-5-5), 1 pixel data, 1 PCLK cycle, 32K colors Pixel data is latched on the rising edge of PCLK. Pixel data is organized as 5 bits of color information each for the red, green, and blue color palette. For further information, please refer to Figure 5 on page 20. Following is the 15B1P1C (5-5-5) pixel data transfer format: Pts) [Peat] Pes) [ Prvai| Pera Pro Pret | Peel | Pr | Peel | PST | PAL] Pel | Pe] P| rol | Note: Lowest three bits of the DAC inputs are padded with zeros . bpp = bits per pixel X = unused bit Pi] = pixel input pin R[7:3] = red pixel data G[7:3] = green pixel data B(7:3] = blue pixel data Mode B Primary/ Secondary Modes: 24B2P3C: 24 bpp (8-8-8), 2 pixel data, 3 PCLK cycles, 16.7M colors Pixel data is latched on every three consecutive rising edges of PCLK. Pixel data is organized as 8 bits of color information each for the red, green, and blue color palette. Following is the 24B2P3C (8-8-8) pixel data transfer format: [Prssi} Pra) Prtsy fPci2i [Peasy] Prvo] rer | Pre | Prat | Pre | Peel | Pal | PR] P| PL | Pld | [ ist | G7 G6 G5 G4 G3 G2 Gi GO B7 B6 BS B4 B83 B2 Bi BO [znd [e786 85 B4 6362 BI BO] R7__RG__RS_R4 RO R21 AO | Land [R7 R6 RS R4 RS R2 RI RO G7 G6 G5 G4 G3 G2 G1 GO Note: —_Intemal clock doubler enabled to produce twice the pixel resolution per PCLK period bpp = bits per pixel P[i] = pixel input pin R[7:0] = red pixel data G[7:0] = green pixel data B[7:0] = blue pixel data Ist = first pixel data latched in 2nd = second pixel data latched 3rd = third pixel data latched 16 Rev. 1.2, 5/12/95 mM 9004133 coo0420 753 a

Display Modes (continued) Mode C Primary Mode: 15B1P2C: 15 bpp (5-5-5), 1 pixel data, 2 PCLK cycles, 32K colors Pixel data is latched on every two consecutive rising edges of PCLK. Pixel data is organized as 5 bits of color information each for the red, green, and blue color palette. For further information, please refer to Figure 5 on page 20. Following is the 15B1P2C (5-5-5) pixel data transfer format: [Prtsi Pca) ] Pris] Pcv2i| Prva Prvoy] Pret | Peel | P| Pel | PRL] P| PE | PA] PM | PO] [ta [xxx xxx xx «fos G4 G3 | 87 8685 Bs 83 [and |XX XK XX XXX LR _RG_RE RA RS | GT Note: Lowest three bits of DAC inputs are padded with zeros bpp = bits per pixel X = unused bit Pi] = pixel input pin R{7:3] = red pixel data G{7:3] = green pixel data B[7:3] = blue pixel data Ist = first pixel data latched in 2nd = second pixel data latched Secondary Mode: 8B1P2C: 8 bpp (4 +4), 1 pixel address, 2 PCLK cycles, 256 colors Pixel address for the red, green, and blue color palette is latched on every two consecutive rising edges of PCLK. Palette RAM contains 256 colors of 256K possible colors (6 bits each for the IOR, IOG, and IOB outputs). Pseudo color pixel address (P[7:0]) is then bit-wise “AND”ed with the RMR. Following is the 8B1P2C (4 + 4) pixel address transfer format: fPrssy Prva) [Pris] [Praia Prvo | PLL | Pre) | PIT | PIL | PT] Pra] PT] Pel] P| PLOT] [ast [xxx xxx Kx dP es Pe PPO | [and [xX XX KX PP] Note: _ bpp = bits per pixel X = unused bit P{i] = pixel input pin Rev. 1.2, 5/12/95 17 me 9004133 O0004e] b5T

Display Modes (continued) Mode D Primary Mode: 8B2P1C: 8 bpp, 2 pixel addresses, 1 PCLK cycle, 256 colors Pixel addresses for the red, green, and blue color palette are latched on the rising edge of PCLK. Palette RAM contains 256 colors of 256K possible colors (6 bits each for the IOR, IOG, and IOB outputs). Pseudo color pixel addresses (P[7:0]) are then bit-wise “AND” ed with the RMR. Following is the 8B2P1C pixel address transfer format: [ Pts) | Pca) | Pres} [ Prtay| Prt} [Peto] Pret | Piel | Pr | Pre] Pret] Pra T Prs) [Prt] Pe [PIO | Note: Internal clock doubler enabled to produce twice the pixel resolution per PCLK period bpp = bits per pixel P[7:0] = pseudo color pixel address P{i] = pixel input pin Secondary Mode: 16B1P1C: 16 bpp (5-6-5), 1 pixel data, 1 PCLK cycle, 64K colors Pixel data is latched on the rising edge of PCLK. Pixel data is organized as 5 bits of color information for red and blue, and 6 bits of color information for the green color palette. For further information, please refer to Figure 6 on page 20. Following is the 16B1P1C (5-6-5) pixel data transfer format: [ Pts) | Pea) | Peta) | Prtzy] Pita} | Peto] Pre) | Piel | Pia | Pre) | Pre [Prat | Pes [Prey Pet | PI | Note: Lowest two or three bits of DAC inputs are padded with zeros bpp = bits per pixel P{i] = pixel input pin R[7:3] = red pixel data G[7:2] = green pixel data BI7:3] = blue pixel data 18 Rev. 1.2, 5/12/95 WM 9004133 cooo4ee 52h

ra} —opre} fone rar} pre Ef te Pra} pet poe / at et) A erp tee Pri} pet) v V 6 rr} tert —Serca\\ fort tet fe Per} sree ]_f DAC rer} —stes{_| isa Peat} —tet | fe fet te) per} —tet | Pat tet v Pes} pe v cone Peer}—stest f “Joe \\ fra} ste} f” ] Exe reer} spas tS css reer} ses] ym se par} ert A pa} pec pra} pee} v peor} steep v Figure 5: 15-bit bypass mode Figure 6: 16-bit bypass mode (used in Modes 1, A, C) (used in Modes 0, 3, 5, 6, 8, D) Note: Lowest two or three bits of DAC inputs are padded with zeros P[i] = pixel input pin R[7:3] = red pixel data [7:2] = green pixel data B[7:3] = blue pixel data 20 Rev. 1.2, 5/12/95 @@ 9004133 0000424 379

8/2/2/2/@ 2/8 8)g zg 8 Zig 8/g Zlalg 2 Ble z/2 Sjc/ajala £/8 8/5 Ele 8 &ls 8/5 Elgiq =z Slx ely e(2{2/2/8[8 2/2 Sjg &jg 8 2/8 Sly 2/a/g & Ble vig E/2/2\\2/2/8 2/8 2\\g Zig 8 2/8 ele Ziglg 2 Bie Els S\\"jalzltl/zla £/5 £13 Z/z 3 E15 Elz ElBlz z= Slx x/5 Z| [S/2i2/218 2/8 2/8 2/8 8 2/8 #2 218/8 2 8|x x8 Z] |8leje/2/8 2/8 2/8 2/8 8 2/8 e/g elslg 2 8|x x18 8 $ SJElE/E|S &/5 Bis e/G FES E/S E/8le e Blx< x|3) = < gs z Blx|&|x]8 |x x|8 x] x x] x|8 x/8/8 g 2) «/8) 93 = Bll aicla <1 Sig X]% SX] x18 x18/9 @ Elx x/8] Be & O)x/8)x/9 x/x x1 x)x x x|x x/O x/2/8 9 Bx x</5] Fg ° @[x|8|x}B x|/x x]B x/x x x{x x/8 x/EZ/8 g Bix ~/2] 4 g E}x|£|x/B x|x «|B x|x x xlx x] x/2I/S g¥ Fix x/z] #= @/x<|/2}x/8 x|x x|B x|x x x/x x/8 x/2/8 B 2lx xe] BB 2/</2)x/B x|x x/G x|x x x/x x/8 xlE/8 g elx x/2] Be @/X/G|x|G <|x x|/G x|x x xl x1B «1x1 B El x / 33 gs ° g |e le le 9 |e easjsis |2 |g |g 8 i8 [8/5 8 2/8) 52 gs, 2\\@je\\8le sia 2/2 8/3 8 Ble ze x|e/g 2 8/8 Blog| 222 a/8]a|8/z gle /% 8) 5 Ele kz xlelg = S/S Slz| 3 3B wlf]2/2/8]o off 218 Sia 8 Sia ela xlaja 2 8/2 gia] ee 5 E/e/sj2|a\\5 -/8 2/8 Zig 8 ie ele xi/elg 2 8/8 sip] az x B/]s|G]z/5/2 Sle z/5 Fz 3 Z| xls xl¥/z = 3/5 Liz] s £ 2/8/2/8\\, 2/8 2/8 2/8 8 2|x «le xjelg 2 8/3 glel a BZ} je/Ss2\\8]x x/8 2/8 21g 8 ex xle x/el/g 2 8/3 Ele s f/8le|o/< x|5 2/3 2/5 & Fix xl/E <j/E/5 & S18 xf c Fe x|8/218)< |B x/x |x x x/x x]x xl2/8 g 2]. x2 Fs */9/E/8)x x/O x[x x]x x x[x x}x x]E/5 5 Elx x/z 5/2 */B/ BB) x</8 x|x x/x x xx |x x]8/8 a Bl x/a 3|° </E/R/Bix x/O x|x x|x x x|/x |x x/2/8 g 2/x x/2] 33 s x/@/z]z]x |B x|x x)x x x|x x|x x]z]5 a z|x x|z] Es sg x/2/2/2)< x|8 x|x x|/x x x/x x}x x/2/8 8 2lx x/e] 2s fo} </E/2/2/< <|G xx x|x «x «Ix x]x x/218 89 Bix x/e £3 gs * |x] 8 [| </8 x) x|x x x|x x|x </5/5 5 E|< x/e] 23 iy 32 s g]2/o}/2le sig {g |g g slg slels g lol ge g ayajajaya Fa je js aye als 2 ale 4 . s/2/8/8/8 <8 |8 |g B= ees/s |B jal <5 ” ee 2 = 2 lei be | Ie le |e [als e z Rev.12,51295 SS mi 90904133 oo004e5 235 mm

oo SsSsSsSssssSsSsSssSSSSSssSSSSSSSsssSSSSSS MIX-COLOR® CH8398A offers an enhanced feature called MIX-COLOR® mode, which allows the simultaneous display of image regions with different spatial resolution and color depth in a single bitmapped frame. MIX-COLOR® is. capable of displaying 64K colors within a high resolution (1280 x 1024 @ 75 Hz) graphics window. This feature is particularly useful in Windows® applications where a colorful picture is placed within a page of text. Window Frame reroduction woe ceeceeecceeeel High spatial resolution wexcozone! ne s Cont i : Display Resolution: 1280 x 1024 Seicocayerne ates : Refresh Rate: 75 Hz Fomor boiyend--atpentored : 128 colors or 256 colors AG ant Cnet ot : (cHa94A ChrenDAC™ MX-COLL : MX-COLORS mode n CHEIOEA ‘ Moda : Le : ‘Seconcany mee: : ' : High color depth : = : ‘ : Display Resolution: 640x 1024 | Piney oa —— + (equivalent full-screen resolution) : ‘Secondary mode: + 32K colors or 64K colors : harcore made: : : Figure 7: MIX-COLOR® Mode MIX-COLOR® mode is available in modes A and D: Mode A Primary mode: Pseudo-color mode embedded mode: 128 colors hardware mode: 256 colors Secondary mode: Bypass color mode embedded mode: 32K colors hardware mode: 32K colors Mode D Primary mode: Pseudo-color mode hardware mode: 256 colors Secondary mode: Bypass color mode hardware mode: 64K colors 22 Rey. 1.2, 5/12/95 MB 9004133 O00042b 17)

—_— ss on Comparison of MIX-COLOR® and PixMix™ Modes CH8398A supports both MIX-COLOR® and PixMix™ modes for displaying high resolution graphics in addition to high color depth within the same frame of data. MIX-COLOR® PixMix™ * MIX-COLOR® has flexibility for both on-the-fly * PixMix™ implementation is only available in the hardware and software (embedded) switching embedded switching mode. modes. * MIX-COLOR® maintains the maximum possible + PixMix™ pixel resolution does not fully utilize resolution for the given clock rate by utilizing all the pixel bus bandwidth or the frame buffer pixel data available. memory pixel data. * 2 pixel addresses per pixel clock. * 1 pixel address per pixel clock. * MIX-COLOR® efficiently correlates pixel data * PixMix™ inefficiently maps between pixel data stored in memory with pixel data displayed. stored in memory with pixel data displayed. * MIX-COLOR® simultaneously displays bypass * PixMix™ simultaneously displays bypass and and pseudo-color modes with the following specs: pseudo-color modes with the following specs: Bypass mode: 16-bit or 64K colors Bypass mode: 15-bit or 32K colors Pseudo-color mode: 256 colors Pseudo-color mode: 256 colors Standard resolution (max): Standard resolution (max): 1280 x 1024 @ 75 Hz 800 x 600 @ 72 Hz Note: 1280 x 1024 can be achieved using Chrontel’s MIX-COLOR® Window Frame display resolution: 800 x 600 refresh rate: 72 Hz : 256 colors : : : up to 32K colors : Figure 8: PixMix™ Mode Rey. 1.2, 5/12/95 23 mm 9004133 ooo04e7 008 mm

TT .uaa$oO Examples of Embedded Mode Switching for MIX-COLOR® and PixMix™ Example # 1; Embedded mode switching for MIX-COLOR® Mode A Primary mode: Pseudo-color mode P[7] and P[15] set to 0 Secondary mode: Bypass color mode P[15] set to 1 [Prisi] Piva [Pray] PezyT PEAT] Prvol] PIT | PL) | PVT | PIL | Peel | Peal] P| Pe] PTT] PIT] [sss [1 [a7 RS RS RA RS G7 GSS GaGa | 7 B65 Ba 03 | Note: Embedded case requires palette RAM table to be reconfigured for 128 colors instead of 256 colors P{i] = pixel input pin é R[7:3] = red pixel data G[7:3] = green pixel data B(7:3] = blue pixel data CEs CH8398A is capable of implementing PixMix™ mode, using P[15] as a mode switch control signal. Example #2: Embedded mode switching for PixMix™ Mode 1 Primary mode: Bypass color mode P[I5] set to 0 Secondary mode: Pseudo-color mode P[15] set to 1 [Prey Ptsai[Prt3) | Peal Pray Prior] Peel | Pred [ Pr | Pel | Pe | P| P| P| P| P| fess [0 [R7 Re RS R4 RS | G7_Ge_G5__Gs_G3 | 67 86 85 Ba A | [Pseudo] 1 [xx XX Xxx [P76 PSP PSP PTO Note: P{i] = pixel input pin P[7:0] = pseudo pixel address X= unused bit R[7:3] = red pixel data G[7:3] = green pixel data B[7:3] = blue pixel data 24 Rev. 1.2, 5/12/95 me 9004133 o000428 TH4 me

sane ; PLS] R7 RT| Pita] R6 R6| PU13) RS RS PLZ} Rs Ra Pini] R3 R3 pe i s Pla cs ics P(e) PS Pe G3} G3| PIs} | PS PS ic2| G2! Pi4) P4 PS 87 87 P13] P3 P3; Be 186 | Py [p2 P2 BS Bs P(t) PL Pt Be 4 Po} PO. PO B3 8B Pipeline delay not shown Pixel output Primary mode: 8-bit bypass (8B1P1C) Secondary mode: 16-bit bypass (16B1P1 C) Figure 9: PCLK Timing Mode 0 Using Hardware Mode Switching? [Mode [CRITI] CRI6] | CRISI[CRIA]] Primary Mode | Secondary Mode] Lo To [0 [0 [0 [ebitpseudo | 16-bts-6-5 bypass] Note: CR[7:4] corresponds to display mode control bits located in the control register

1 Figures 9 through 12 represent the most commonly used options

For information on other available options, please call Chrontel Rey, 1.2, 5/12/95 25 @™@ 9004133 o000425 980

PCLK Timing Diagrams (continued) eu ff Lf Ly Ly lL pane 7 PIS) G7 Pid) |Ge| P13] Gs Pft2] G4 Pita) G3} PLO} ee Pel eo Pixel i = bond = = ixel inputs pm : Pie} x x 86) RS PIS] x x BS IRS| Pts] x x Ba Re PEs] P3 °7 B3 IR PR] |p2 Ps 82 R2 P(t) PI PS Bt Rt Pio} Po P4 ‘Bo Ro SD 4 eae" “ Pipeline delay not shown ~ Pixel outputs Primary mode: 8-bit pseudo (8B1P2C) Secondary mode: 24-bit bypass (24B1P2C) Figure 10: PCLK Timing for Mode 4 Using Hardware Mode Switching! [Mode [CRITI] CRIG]] CRIGI] CRIA]] Primary Mode | Secondary Mode] [aT fo [of 0 [ebitpseudo ara] 26-bit 88-8 bypass | Note: CR(7:4] corresponds to display mode control bits located in the control register For information on other available options, please call Chrontel 26 Rev. 1.2, 5/12/95 mM 9004133 0000430 LT? mm

PCLK Timing Diagrams (continued) exe _f Lf LJ Lyle BLANK* ‘ ‘ : : INTERNAL 2X PCLK : : : ‘ (13) P41 Pt BS BS Pitz] |P2 P2 Bs 88 Pitt} PS P3 87 B7| P{10) Pq P4 G3 G3| pis} | PS PS ca} Gal Pte} G5| Gs) . om [| fo] Pe] [Po PO ic? G7! P{5) PA Pt RS RS Pf} P2 P2 R4 Re Ppl |P3 P3 RS RS Piz} PS Pa Ré RS Pty PS, PS R7 R7, PIO) Lt [4] Mode switch wn “a Na Pipeline delay not shown Pixel outputs Two pixel addresses are latched per PCLK Primary mode: 8-bit pseudo (8B2P1C) Secondary mode: 15-bit bypass (15B1P1C) Figure 11: PCLK Timing for Mode A, MIX-COLOR®, Using Software Mode Switching! [Mode [CRIMI] CRIG][CRISI| CRIA] Primary Mode | Secondary Woda] La [1 [0 [4 | 0 [MXxcOLOR® &-i pseudo] MIX-COLOR® 16-08 555 bypass| Note: CR[7:4] corresponds to display mode control bits located in the control register For information on other available options, please call Chrontel Rey. 1.2, 5/12/95 27 @™ 9004133 0000431 535 a

——_- eee PCLK Timing Diagrams (continued) eue J Lf Ly Li Le BLANK* : : ; : INTERNAL 2X PCLK : : : 1 : | : pay | P2 P2 BS Bs i {12} P3 PS Bs Bs Pity | |PA iz} 87 87 Pio} | PS PS G2! cs| Pig} Ps Pe G3} G4) Pa} | P7 P7, Ica Gs| Pixel inputs = t = — Pry PO Po G5 GS) PIs} P41 Pt G6 | Ge | Pfs} P2 P2 G7| G7 Play P3 P3 RS R3} P(2] PS PS RS RS Pt} Pé P6 R6) RE Plo) P7 P7 R77) R7 Pipeline delay not shown Pixel outputs ‘Two pixel addresses are latched per PCLK Primary mode: 8-bit pseudo (8B2P1C) Secondary mode: 16-bit bypass (16B1P1C) Figure 12: PCLK Timing for Mode D, MIX-COLOR®, Using Hardware Mode Switching’ [Mode TCRI7I[CRIGI[CRIS]] CRI¢]] Primary Mode | Secondary Mode] [ot [1 [0 [4 [Mix coLore obit pseudo] MIXCOLOR® 16 ba SSS bypass] Note: CR[(7:4] corresponds to display mode control bits located in the control register For information on other available options, please call Chrontel 28 Rev. 1.2, 5/12/95 MB 9004133 0000432 475

Table 4 * Register Maps and Definitions ms [| mm =e Power Up [PwA|"7 [0 | 0 | 0 _|Palete RAM Wie Address Register | wa [Por [+ [0 | 0 | 1 | Paletie RAM DataRegister waa

1 Pixel Read Mask Register (IDR, altemate access IDR = COH

to control register) CR = 00H [pRA__| 7 | 0 [1 [1 [Palette RAM Read Adcress Register | wa] Clock RAM Write Address Register (altemate N/A access to clock select register) [eon | 4_[-1_|_0 | 1_| Giock RAW Data Register fer" [4 [1 [7 _[_ 0 | Gontrot Reaistr [oon] feRa [1 _[1_| 1 _| _1_| Glock RAM Read Address Register fesk™ [1 [0 [0 | 0 |Ciock SelectRegister OH rest” [0 |_0 [0 | 7 _| Test Register intemal use oni) [__——_] [auxR? |= [ = Jawary Register oo Note: 1 These registers can also be accessed by using the alternate accessing method

2 This register can only be accessed by using the alternate accessing method

PWA: Palette RAM Write Address Register PWA specifies the address to the palette RAM for write access. PDR: Palette RAM Data Register PDR contains the data read from the palette RAM or the data to be written to the RAM. The tead address is specified by PRA, the write address is specified by PWA. RMR: Read Mask Register RMR is used in pseudo and MIX-COLOR® modes. Each bit of RMR is bit-wise logically “AND” ed with the 8-bit palette RAM address. The resulting address is used to point to the palette RAM. Under the alternate register access method, this register is used to access the ID Register, Control Register, Auxiliary Register, and Test Register. For further information, please refer to “Alternate Access Method” on page 37. Note: This register is NOT initialized upon power up When pseudo mode is activated, the pixel address uses the RMR. The RMR content is bit- wise “AND”ed with the pixel address, and the result is used to address the color palette RAM. On the 15-bit or 16-bit bypass mode, the lowest 2 or 3 bits of the DACs are padded with zeros For further information, please refer to Figures 5 and 6 (page 20). In MIX-COLOR® mode, the masking operation is enabled for pseudo-color mode. To disable the masking operation, write FFH into the RMR. PRA: Palette RAM Read Address Register PRA specifies the address to the palette RAM for read access. CWA: PLL Clock RAM Write Address Register CWA specifies the address to the PLL RAM for write access. Using the alternate register access, CWA accesses the Clock Select Register. For further information, please refer to “Alternate Access Method” on page 37. Rev. 1.2, 5/12/95 29 @™ 9004133 0000433 301 a

OO eeeeeSSSSSSSSSSSSSSSSSSSSSS CDR: PLL Clock RAM Data Register CDR contains data read from the PLL RAM or data to be written to the RAM. CRA specifies the read address and CWA specifies the write address. CR: Control Register CR determines the display modes, power down modes, and MPU interface to the color palette RAM. | cri | cris} | crisi | cra) [ cRii [ CR] [ CRI | CRIO_| . [ows ~bM2——DMi Mo | Pbt_[ wspis-|_viP [P00 | CR[0]:PD0 = Power Down control bit 0 These power down modes are well-suited for both LCD and CRT applications, and support “Green PC” applications. CH8398A supports both LCD graphics- only controllers and LCD graphics controllers with simultaneous CRT and LCD display. Power consumption of the graphics subsystem can be greatly reduced using these power down modes. CR[1]:V / P = Select VCLK / PCLK ratio if the MNK values of VCLK are chosen so VCLK / PCLK = 1, then: _ set CR[1]=0 - This is used only for optimization of the internal doubler. Please note that whether CR[1] is set to “O” or “1,” a change may not be readily apparent to the user. For example: PCLK = 28.322 MHz, and the VGA controller requires VCLK = 2x PCLK Step 1. Program the proper M, N, and K values in the PLL RAM to generate 56.444 MHz (i.e. M=21, N= 174, K= 1) Step 2. Set CR[I]=1 This example requires the following data format: a [07 [06 [ds | 04 | b3 [D2 1 | 00 | b7 [6 | 05 [D4] 03 | 02] 67] DO [oto 7 0 1 0 7/7 070 777 04 CR[2]: MSDIS = MSW input pin disable 0 = MSW pin control display mode switching (default) 1 = MSW pin in interpreted as 0 regardless of its state CR[3]: PD1 = Power Down control bit 1 cs TS RTC. mM 9004133 0000434 245 mm

SSSSSsSSSSSSSSSSSsSsssssSSSSSESIION CR: Control Register (continued) Table 5 « Power Down Control Bits. [Pbt_| PDO |Description? [0 | 0 [MPLL, VPLL, and LUTDAC are ON. Normal operation mode. MPLL and VPLL are ON, LUTDAC is OFF. Used for flat panel controller where LUTDAC is not required. Both PLL and palette RAMs can still be accessed from the MPU bus. MPLL is ON, VPLL and LUTDAC are OFF. MPLL is on, memory image is retained. Used in CRT and flat panel applications. Both PLL and palette RAMS can still be accessed from the MPU bus. 1 [MPLL, VPLL and LUTDAC are OFF. Graphics subsystem is completely powered down. Only palette RAM can still be accessed from the MPU bus. CR{[7:4]: Display mode control bits These bits correspond to DM[3:0] in the control register are used to select the display modes. Table 6 » Display Mode Control Bits [crrm|crie] iCR[S5]} a) Description [Mode] DM3 | Dm2| DM1 | pmo | MSW = 0, PRIMARY MODE MSW = 1, SECONDARY MODE | o | o | o | 0 | 0 [8-bitpseudo 16-bit 5-6-5 bypass | 1 | o | o | o | 4 [15-bit5-5-5 bypass 8-bit pseudo let} o fo [1 [0 [etipseudo —_———~—=*r abt pseudo | 3 [| o | o [| 1 | 1 [16-bitS6-5 bypass 8-bit pseudo [4 | o | 1 | 0 | 0 [@bitpseudo (4 +4) 24-bit 8-8-8 bypass | s* [| o | 1 | 0 | 1 [24-bite-2-8 bypass 16-bit 5-6-5 bypass |e | o | 1 [| 1 [| 0 | 16-bit5-6-5 bypass 24-bit 8-8-8 bypass [7 [| o | 1 | 1 | 1 [24-bite-2-8 bypass 24-bit 8-8-8 bypass [ar | 1 | o | 0 [ 0 |&bitpseudo (4+ 4) 16-bit 5-6-5 bypass |] 1 | 0 [ o [1 Jebitpseudo (6 +0) 24-bit 6-8-8 bypass | at | 1 | o | 14 [ 0 [MIxX-COLOR®, 8-bit pseudo MIX-COLOR®, 15-bit 5-5-5 bypass [et] 1 | o | 1 [ 1 |[24bits-8-8 bypass 24-bit 8-8-8 bypass | c [ 1] 1 | 0 [ 0 [15-bit5-55 bypass 8-bit pseudo (4 + 4) [ot [| 1 [ 1 | 0 | 1 [MIX-COLOR®, 8bit pseudo MIX-COLOR®, 16-bit 5-6-5 bypass Note: *= ATT20C498 compatible mode = on-chip clock doubler enabled CRA: PLL Clock RAM Read Address Register CRA specifies the address to the PLL RAM for read access. Rev. 1.2, 5/12/95 31 M® 9004133 0000435 164 mt

ooo SSSSSSSSSSSsssseeeeSSSSSSSSSSS CSR:Clock Select Register CSR internally selects MPLL and VPLL frequencies. See Table 11 on page 40 for further details on PLL RAM data organization. CSR[3:0]: VS[3:0] = VPLL Select These bits are logically bit-wise “OR” ed with the external FS[3:0]. Selects 1 of 16 entries. CSR[6:4]: MS[2:0] = MPLL Select Selects 1 of 8 entries. CSR[7]: PH* = PLL Frequency Hold CSR[7]=0 PLL frequency holds at the current value. No change to MCLK or VCLK outputs, regardless of the value written to CSR[6:0] of this register, or the state of external FS[3:0]. CSR[7]=1 PLL frequency releases the current value. MCLK frequency depends on the value of MS[2:0] (CSR[6:4]). VCLK frequency depends on the logically bit-wise “OR”ed value of external FS[3:0] with the internal VS[3:0] (CSR[3:0]). IDR: Identification Register IDR is a read only register with a predefined value of COH. - [RET TORIE, ORGY | TORAT_[ TORT] TORE [ORR [TORT] TEST: Test Register TEST is for internal use only. AUXR: Auxiliary Register AUXR sets both the video and memory clock output voltage levels to a target 50% duty cycle. See Tables 7 and 8 page 33 for available voltage levels. AUXR[1:0]: VL[1:0] = Select bits for video clock voltage level output AUXR[3:2]: ML[1 :0) = Select bits for memory clock voltage level output AUXR[4]: Reserved bit. 99 9 ee AUXR[5]:. =O frequency doubler enabling base on Color Mode selection 4 (it is recommended AUXR[S5] be set to 0) = z =1 — frequency doubler enabled (independent of. ‘Color Mode) AUXR{[6]: =0 normal operation : eee -. = 10 invertMSW oe 32 Rey. 1.2, 5/12/S5 @@ 9004133 Gaco43b O10

AUXR: Auxiliary Register (continued) _ . a | AUXR[7] used to eliminate requirement of RS2 pin. © “= 4 AE 'RS2 pin is used, then the user should keep AUXR[7] = 0 and RS(2.0}} fe "Will "be “decoded as ‘specified in Table 4, “Register Maps ‘and! oe __ . Definitions,” on page29. Jo SS eo ae) 5 aes - =e Tf-RS2-pin is not_used.- Geek in. connects ‘to; GND permanently) = Lele oN Seok UBER ITT Gant be sa ta chaos the Sing. as showheiGy ee ge ee Sco Ga ee ee ee «SS SSE AUXRITT = OBS rea Ss TAUXRIT] Seen oS ee Be ees Colo RAM iclated hardware when RS? “0a Fe ee RPL Ram rele hardvarenen nso 1) Eee Table 7 * Video Clock Table 8 * Memory Clock [AUXRI]|AUXRIO]|" Targeted 50% Duty Cycle | [AUXRIS][AUXR[2]|___ Targeted 50% Duty Cycle _| D:D POP et OO OO | a © SO OO | Me 9004139 usenuse TS? i

All MPU access is through D[7:0] bus, with RD* and WR* control signals, and RS[3:0] to select which register is to be accessed. Some registers have an alternate access method for graphics controllers that do not provide an RS3 output signal. Access to the Palette RAM 6-bit Access to the Palette RAM CH8398A supports access to the Palette RAM only in a 6-bit format, as indicated in Figures 13 and 14 below. MPU PALETTE MPU PALETTE A = We ae Ze i pent Figure 13: 6-bit Write Mode Figure 14: 6-bit Read Mode To write the palette RAM: Step 1. Load the initial RAM write address to PWA. Step 2. Write PDR with the red, green, and blue values. The first write is accessed to write the data to be stored in the red temporary register, the second is the green, and the third is the blue. Internally there is a modulo 3 counter. After the third (blue) write to the PDR, the red, green, and blue data is written to the palette RAM and the address is incremented. The entire palette RAM can be written by sequential writes to PDR. The address rolls over to 00H after reaching FFH. The modulo 3 counter resets after each write to PRA or PWA. To read the palette RAM: Step 1. Load the initial RAM read address to PRA. This action triggers a fetch from the palette RAM, transferring the red, green, and blue data to the temporary register. The address is automatically incremented after the fetch. Step 2. Read the PDR for the red, green, and blue values. The first read is accessed to read the data stored in the red temporary register, the second to green, and the third to blue. Internally there is a modulo 3 counter. After the third (blue) access, the device triggers another fetch followed by an address increment. The entire palette RAM can be read by sequential reads of the PDR. The address rolls over to 0OH after reaching FFH. The modulo 3 counter resets after each write to PRA or PWA. 34 Rey. 1.2, 5/12/95 mM 9004133 0000438 993 a

SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSeeeeee CN ETOIOR Table 9 « Palette RAM Data Organization a a ee ee a Rev. 1.2, 5/12/95 35 mm 9004133 0000439 4e2T =

Access to the PLL Clock RAM Access to PLL Clock RAM is similar to the palette RAM, except the modulus counter is modulo 2. Each PLL is two bytes wide: the first access is the LSB, the second is the MSB value. VPLL has 16 locations, occupying the first 32 bytes, while MPLL occupies the next 16 bytes with 8 locations. To write the PLL Clock RAM: Step 1. Load the initial RAM write address to the CWA. Step 2. Write CDR with the PLL values. The first write is the LSB, the second is the MSB. After the MSB write, the PLL data is written to the PLL RAM and the address is incremented. The entire PLL RAM can be written by sequential writes to CDR. The internal modulo 2 counter resets after each write to the CRA or CWA. To read the PLL Clock RAM: Step 1. Load the initial RAM read address to the CRA. This triggers a fetch from the PLL Clock RAM, and the data transfers to the temporary register. The address automatically increments after the fetch. Step 2. Read the CDR for the PLL values. The first read is the access to the LSB, the second is the MSB. After the MSB access, the device triggers another fetch followed by an address increment. The entire PLL RAM can be read by sequential reads of the CDR. The internal modulo 2 counter resets after each write to CRA or CWA. Table 10 * PLL Clock RAM Data Organization Address Frequency Outputs CSRI6:4] CSRI3:0)' Location (MHz) MS[2:0] VS[3:0] a a a ee a a Note: 1 CSR[3:0] is logically bit-wise “OR”ed with external FS[3:0] inputs respectively “Locations 0 — 1 of the VPLL RAM, providing the following frequencies, are initialized buts “may be overwritten: EEE G7 SU Sareea se RET Uh! eS Location 0. VCLK=25.175 MHz es Location 1 VCLK = 28.322 MHz - See 36 Rey. 1.2, 5/12/95 we 9004133 o000440 54) a

CH8398A offers an alternate method to access several registers. This method is designed for graphics controllers that do not use an RS3 signal. The alternate access method applies to the following registers: * CSR * CR + IDR ° AUXR Note: The AUXR register can only be accessed through the alternate access method. CR can be accessed without using the altemate access method even though the RS3 signal from the graphics controller is not used. Access to the Clock Select Register There are two methods of accessing the CSR. The first method requires RS[3:0] to be driven to [0000]. The alternate method does not require the RS3 signal. With RS3 internally pulled high, alternate access to CSR is achieved by: Step 1. Set RS[2:0] to [100]. Step2. Read CWA four consecutive times without accessing any other register between reads. Step3. The fifth access (read or write) is directed to the CSR. Only one access is allowed for each sequence. During the alternate access sequence, RS[2:0] must be set to [100]. To terminate the access sequence, access a register other than the CWA. other than the CWA (i.e., set RS[2:0] to a value other than (100). a 7 oN OOOOO © CACC AC Ae>, Read Read Read Read Read / Write CWA CWA CWA CWA CWA RS3 Intemally pulled high Figure 15: State for Alternate Access to Clock Select Register Rev. 1.2, 5/12/95 37 Ml 9004133 OOO0441 488

Alternate Access Method (continued) Access to the Control Register There are two ways of accessing the CR. The first method requires RS[2:0] to be driven to [110]. The alternate method does not require the RS3 signal. With RS3 internally pulled high, alternate access to CR is achieved by: Step 1. Set RS[2:0] to [010]. Step2. Read RMR four consecutive times, without accessing any other register between reads. Please note the fourth read access returns the value of the IDR. Step 3. The fifth access (read or write) is directed to the CR. Only one access is allowed for each sequence. During the alternate access sequence, RS[2:0] must be set to [010]. The sequence will terminate and return to its initial state at any point when the content of RS[2:0] # [010]. other than the RMR (i.e., set RS[2:0] to a value other than [010)). : Read Read Read Read Read/Write Read/Write Read/Write RMR RMR RMR RMR RMR RMR RMR RS3 Internally pulled high Figure 16: State for Alternate Access to ID, Control, Auxiliary, and Test Registers Access to the Identification Register Access to the IDR is achieved by: Step 1. Set RS[2:0] to [010]. Step 2. Read the RMR three consecutive times, without accessing any other register between reads. Step3. The fourth read returns the content of the IDR. Only one access is allowed for each sequence. During the alternate access sequence, RS(2:0] must be set to [010]. The sequence will terminate and return to its initial state at any point when the content of RS[2:0] # [010]. 38 Rey. 1.2, 5/12/95 me 9004133 oo00442 314 a

Alternate Access Method (continued) Access to the Auxiliary Register Access to AUXR is achieved by: Step 1. Set RS[2:0] to [010]. Step2. Read RMR four consecutive times, without accessing any other register between reads, Please note the fourth read access retums the value of the IDR, and the fifth access (read or write) is directed to the CR. Step3. The sixth access (read or write) is directed to AUXR. Only one access is allowed for each sequence. During the alternate access sequence, RS[2:0] must be set to [010]. The sequence will terminate and return to its initial state at any point when the content of RS[2:0] + [010]. Writing 00H to the next access will also terminate the sequence. PLL Clock Generator CH8398A incorporates Chrontel’s proprietary PLL technology, which is capable of generating any frequency from 8 MHz — 135 MHz, by writing the appropriate values to the PLL RAM. To synthesize various frequencies used in different graphics modes, a stable reference frequency is required. The source of this reference frequency can come from either: * anon-chip crystal oscillator (a crystal with a nominal frequency of 14.318 MHz is required between pins 6 and 7), or * an external frequency source being applied to pin 7 of CH8398A with pin 6 grounded. XTAL Divide Phase Loop vco Divide Osc bym Detector Filter byk Four aT byn Figure 17: PLL Block Diagram The formula for calculating the output frequency is achieved by: where: n FREF = 14.318 MHz (for normal operation) Four = Frer x —— m=M+2 mxk n=N+8 k=2* a | O7 [be [ os | b4 [ os | bz [pi [bo [br [06 | os | o4 | bs [ bz] 07 | DO | L«i [ko [ms [ma [oma [M2 [mi [mo [N7 [Ne [NS | Na [Na [2 [NT | NO | Note: Table 11 on page 40 shows some samples of M, N, and K values to be programmed. For frequencies not listed below, please contact Chrontel. D[7:0] = data bus input from graphics controller K[1:0] = output frequency scale M{[5:0] = reference frequency input divider N[7:0] = VCO frequency divider Rev. 1.2, 5/12/95 39 M™ 9004133 0000443 250 mm

Table 11 * Sample Frequency Coefficients (reference frequency = 14.318 MHz) [ Four [| om [| N [ Kk [ Four [om [ NT Kk | ET [| sess [ 8 | 7 [7 | | 2744 [| 7 | 61 [2 Ee | 3375 [| 5 | 58 [2 | | ao49 | 6 | 42 | oT | a7so | 6 | 34 | 1 | 100.23 | 4 | 34 | oT | 5190 | 6 | 50 | 1 | [13500 [ 5 | 58 | o | Note: Use M values of 10 or less for best circuit performance 40 Rev, 1.2, 5/12/95 me 9004239 oooo444s 197 ae

Table 12 * Absolute Maximum Ratings ["symbot [Description ————«dY in| Typ | Max] Units — | __ [Woo relative to GND a [_____Finput voltage of all digital pins [enb-05 |_| voo+os |v] | —_[Anaiog output shor circuit duration [J indefinite “| Seo] Storage temperature [= t80 Junction temperature [80 Vapor phase soldering (one minute) a ee Note: Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated under the normal operating conditions is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1 The device is fabricated using high-performance CMOS technology. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5V can induce destructive latchup. Table 13 * Recommended Operating Conditions [symber_] Description [win [typ [Max [Units] Supply vatage [475_| 600 [825 | v | Ambient operating temperature [of [ot Output oad to DAC outputs re IREF Reference current RS-343A output -3.0 8.39 10.0 PS/2™ compatible -3.0 8.88 10.0 Table 14 * DC Characteristics (Operating Conditions: Ta = 0°C — 70°C, Von = 5V+ 5%) [symbor_] Description Test Condition @TA= 250 | Min | Typ | Max | Uni] [Resolution (each BAC) a [| Aecuracy (each DAG) a Integral linearity error ee ee [to | Diferentalinearty enor | Sid id at | _[6rayscaleenor CSS [| Menetonicty Garanteed [Leong inary 7 Rev. 1.2, 5/12/95 41 me 9004133 oooo44s O23

_—_Y ORK Table 18 * AC Characteristics [Symbei[oeeenpton «dO J [Fw | Siglestge data cocerte [tnt | 0 [ewe [Dustedge cate ceekrate no] tas [tn [RSI setptine 0 0 or J [ew | Re01Peme 0 0 a [Wm | RO"actvetocawassored «dP 8 [wwe [RO cto ie datavetd [500s a [tem [Resdsearostine ds Pe [ens | Wit data stupine te [ten | We datahowtime 010] re [tm | Ro* WRtiow puso 80 ae [it vw | Pasinptseupame de [ta nn | Patinputoine de I EP I OO A a CZ [tenn Clek ise waanigm ae [tn [Gockpusewianiow as [ews [arog oututaeiay [a0 dtm [re [Araogouparee time a [we Ansiog ouputsotingtine [8 ae [teu in| Setuptine aetsioswobe si te [ Ticwo.wn | Holdtine.stobetedeia de [Terns wn [ Sibepusewith | Pe SS [wx Anaog ouput stew te ie PCLK cycles | teo_re —| Veosuppy carers ne | 200m] IPD2_TYP Mode 1: MPLL & VPLL ON, LUTDAC OFF mA IPD3_TYP. Mode 2: MPLL ON, VPLL & LUTDAC OFF mA Mode 3: MPLL, VPLL, & LUTDAC OFF mA Note: 1 MCLK = 40 MHz and VCLK = 28.32 MHz Test Unless otherwise specified, the testing conditions are the same as in Table 13, “Recommended Operating Conditions: — Conditions,” on page 41. TTL input values are 0 — 3V, with input rise / fall times < 3 ns, measured between the VIL and Vin. Timing reference points at $0% for non-TTL inputs and outputs. TTL reference points at 1.5V for inputs and outputs. Analog output load < 10 pF, D[7:0] output load < 45 pF Rev.12,51295 SSS =e mm 9004133 o000447 4Tb =

PC Board Layout Considerations CH8398A is a high performance mixed signal IC containing precision analog and digital circuits. In order to achieve high performance, it is important to optimize the PC board layout (PCB) for the CH8398A. Care should be taken in laying out the power and ground planes to ensure good decoupling. In general, analog outputs should be short and wide to minimize inductive ringing, and analog signal traces crossover to digital signals should be minimized. When operating the device at high frequencies (> 50 MHz), the pixel data bus (P[15:0]) and the clock signals should have dedicated drivers. These signal traces should be kept short and placed beside each other the signal delays through the interconnects are matched, to minimize clock and data skew of the pixel bus. Ground Planes For four-layer PCBs with a uniform ground plane, CH8398A and its associated analog components (e.g., decoupling circuitry, current reference, and voltage reference) can be connected to the ground plane directly. The connections to the ground plane should be made with wide traces to minimize inductance. Connecting the analog and digital ground pins directly to the ground plane is highly recommended. ae Supply Decoupling : For the digital power supply, bypass capacitors (0.1 F) are recommended. Make leads as short as possible and place the capacitor as close as possible to the device. Connect the ground side of the capacitors directly to the ground plane. For AVDD pin 42, a pi-filter configuration is recommended, with a 10 uF tantalum capacitor, in parallel with a 0.1 uF ceramic capacitor to GND, followed by a ferrite bead in series, then a 0.1 uF ceramic capacitor close to the AVDD pin. For AVDD pin 3, a 5.1V zener diode with a 0.1 uF ceramic capacitor for supply conditioning that would result in optimal performance. In general, short leads and direct connection to the power supply and ground planes are highly desirable. For details, please refer to Figure 23 on page 47. Digital Signal Interconnect Place digital signals of the pixel bus, P[15:0] and PCLK, alongside each other to minimize data and clock skew. At high frequencies, these signals should have short traces, dedicated drivers, and series termination damping resistors to minimize signal reflections. Analog Signal Interconnect In general, analog signal traces should be as short as possible. Therefore, CH8398A should be located as close as possible to the VGA controllers and output connectors to minimize the amount of noise and transmission line reflection due to impedance mismatch between the PCB and the cable. Video outputs should overlay the analog ground plane to maximize supply rejection. To cut down the amount of transmission line reflection, connect a 75 Q resistor with short leads between each video output and ground. Make the connection as close to the device as possible. Some designs, such as VESA local bus, may have restrictions on component placement. For further discussion of this issue, please refer to“Component Placement” on page 50. Clock Signals In applications where either the video or memory clock frequencies are pushed toward the performance limit of the system, AC coupling circuitries should be used. This will allow for minor duty cycle adjustments for these high frequency signals. For additional information, please request a copy of AN-03, “Application Notes on AC Coupling.”

6 Rev £8, 5729S

$SSSSSCNFIOSGA IREF 10G 2||O2 Te ee] me LL Ka . Chrontel ot \\/ ChronDAC™ RS Figure 23: Typical Connection Using External Current Reference Table 19 « List of Parts for Figure 23 a [RRR «dS metal fim sits a mm 9004133 000451 327 a

1OR {@) well, Te cr 2 eZ Chrontel Ra ChronDAC™ Figure 24: Typical Connection Using Internal Voltage Reference Table 20 « List of Parts for Figure 24 a PRERRRS «dS eta ests SCS 48 Rev. 1.2, 5/12/95 i 9004133 oo004s2 2b

AAA SSSSSSSSSSSSSSSSSOSNTISEIOA +12V 2202 +5V 62] yop Supply po 27) vb ee Se Re -Y) Lp— 221 avi ul } 3 | app c4_|cs Al +le1 _|c2 ics es _lc7 * Chrontel ChronDAC™ P p P p p GND, AGND 10, 36, 37, 60, 2, 41 Figure 25: Recommended Supply Decoupling Table 21 ¢ List of Parts for Figure 25 a 2,63, CH C5, 68, C7 [ROSCS™SCSC~SRO Weston SSSC~S~S Rev. 1.2, 5/12/95 49 wa 9004133 0000453 1TT a

Figure 26 below is an example of typical placement of VGA components on a local bus VGA adapter. CH8398A should be placed as close as possible to the VGA controller, since there are high speed signals between these two devices. For most local bus implementation, the VGA controller will be placed in close proximity to the local bus connector. Due to the low impedance nature of the CH8398A RGB outputs, they can be located farther from the VGA monitor connector. Micro-strips or strip lines with characteristic impedance of 75 Q should be used to route these outputs to the video connector. IOR, 10G, IOB L To Ht _| monitor VGA CH8398A [7] . controller

75 Q characteristic

VESA LocaL Bus CONNECTOR ISA Bus CONNECTOR Figure 26: Recommended Placement of VGA Components for Local Bus VGA Adapter

ORDERING INFORMATION

A ee SSSeeeeeeSee

2210 O’Toole Avenue

San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 ©1994 Chrontel, inc. All Rights Reserved. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR ANO SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE ‘SPECIFIC WRITTEN CONSENT OF Chrontet. Life support sysiems are those intended to support or sustain life and whose failure to perform when used as directed can reasonably ‘expect to result in personal injury or death. ‘Chrontel reserves the right to make changes at any time without notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no werranty for the ute of our products and assume no liability for errors contained in this document. Printad in the U.S.A. 47012 BO Ry, 1.2, SARS @@ 9004133 0000454 O3b

Product Information

CH8398A specifications and overview.

Summary

TRUE-COLOR CHRONDAC WITH 16-BIT INTERFACE

Description

TRUE-COLOR CHRONDAC WITH 16-BIT INTERFACE

Source title CH8398A Datasheet(PDF) - List of Unclassifed Manufacturers

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