CH7301C

CH7301C CHRONTEL | Alldatasheet

Document overview

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• PDF pages: 30

Technical content

Features

• DVI Transmitter up to 165M pixels/second
• DVI low jitter PLL
• DVI hot plug detection
• Supporting graphics resolutions up to 1600x1200 pi xels and 1920x1200 reduced blanking
• Providing RGB output
• DAC connection detection
• Programmable power management
• Fully programmable through serial port
• Complete Windows and DOS driver support
• Low voltage interface support to graphics device
• Three 10-bit video DAC outputs
• Offered in a 64-pin LQFP package General Description The CH7301C is a display controller device which ac cepts a digital graphics input signal, and encodes and tr ansmits data through a DVI or DFP (Digital flat panel). The device accepts data over one 12-bit wide variable voltage data port which supports different data formats includin g RGB and YCrCb. The DVI processor includes a low jitter PLL for generation of the high frequency serialized clock, and all cir cuitry required to encode, serialize and transmit data. T he CH7301C comes in versions able to drive a DFP display at a pixel rate of up to 165MHz, supporting UXGA resolution displays. No scaling of input data is pe rformed on the data output to the DVI device. See Figure 1 for the functional block diagram of the CH7301C. Color space conversion from YCrCb to RGB is support ed in both DVI and VGA bypass modes.

Figure 1. Functional Block Diagram

1.1 Package Diagram

Figure 2. 64-Pin LQFP

1.2 Pin Description

Table 1. Pin Description bus. The internal pull-up will be to the DVDD supply. has been detected on the HPDET input). This is an open drain output. The output is released through serial port control. This pin provides a general purpose I/O controlled via the serial port.

corresponding to data on the TDC[0:2] outputs. This pin is used for factory test and should be tied to GND or left N/C. A buffered version of VGA vertical sync can be acquired from this pin.

12 In D[11] -

signal is used as the threshold level. are not available, the XCLK* input should be connec ted to VREF. reversed under the control of the MCP bit (in regis ter 1Ch).

3 Power TGND

operating mode, with a block diagram of the data flow within the device is shown on Figure 1 .

2.1 RGB Bypass

and the XCLK clock signal can be 1X or 2X times the pixel rate. The CH7301C can support a pixel rate of 165MHz. conversion or flicker filtering is applied in RGB bypass.

2.2 DVI Output

controller’s digital output port. Data will be 2X m ultiplexed, and the clock inputs can be 1X or 2X ti mes the pixel rate. format must be selected to be one of the RGB input formats. 1This mode is implemented with reduced blanking. Table 2. DVI Outputs

• Multiplexed data, clock input at 1X pixel rate
• Multiplexed data, clock input at 2X pixel rate For the multiplexed data, clock at 1X pixel rate, t he data applied to the CH7301C is latched with both edges of the clock (also referred to as dual-edge transfer mode or DDR). For the multiplexed data, clock at 2X pixel rate, the data applied to the CH7301C is latched with one edge of the clock (also known as single edge transfer mode or SDR). The polarity of the pixel clock can be reversed under serial port contr ol. In single edge transfer modes, the clock edge u sed to latch data is programmable. In dual edge transfer modes, the clock edge used to latch the first half of each pixel is programmable.

3.1 Interface Voltage Levels

cally done using a resistor divider.

3.2 Input Clock and Data Timing Diagram

input clock for the multiplexed data, clock at 1X pixel rate method. Figure 3. Interface Timing 1 D[11:0], H, V DE times measured when input equals Vref+100mV on rising edges, Vref-100mV on falling edges. Table 3. Interface Timing

64 P-OUT

1 VGA Line

8 201-0000-056 Rev. 2.1, 01/07/2014

3.3 Input Clock and Data Formats

The 12 data inputs support 5 different multiplexed data formats, each of which can be used with a 1X c lock latching data on both clock edges, or a 2X clock latching data wi th a single edge. The data received by the CH7301C can be used to drive the DVI output, the VGA to TV encoder, or dir ectly drive the DAC’s. The multiplexed input data formats are (IDF[2:0]): IDF Description 0 12-bit multiplexed RGB input (24-bit color), (mult iplex scheme 1) 1 12-bit multiplexed RGB2 input (24-bit color), (mul tiplex scheme 2) 2 8-bit multiplexed RGB input (16-bit color, 565) 3 8-bit multiplexed RGB input (15-bit color, 555) 4 8-bit multiplexed YCrCb input (24-bit color), (Y , Cr and Cb are multiplexed) For multiplexed input data formats, either both tra nsitions of the XCLK/XCLK* clock pair, or each risi ng or falling edge of the clock pair (depending upon MCP bit, rising r efers to a rising edge on the XCLK signal, a fallin g edge on the XCLK* signal) will latch data from the graphics chip. The multiplexed input data formats are shown in the figures below. The Pixel Data bus represents a 12-bit or 8-bit mul tiplexed data stream, which contains either RGB or YCrCb formatted data. The input data rate is 2X the pixel rate, an d each pair of Pn values (eg; P0a and P0b) will con tain a complete pixel encoded as shown in the tables 4 ~ 7 below. It is assumed that the first clock cycle following the le ading edge of the incoming horizontal sync signal contains the first word (Pxa) of a pixel, if an active pixel was prese nt immediately following the horizontal sync. This does not mean that active data should immediately follow the hori zontal sync, however. When the input is a YCrCb data stream the color-difference data will be transmitted at half the data rate of the luminance data, with the sequence being set as Cb, Y, Cr, Y , where Cb0,Y0,Cr0 refers to co-sited luminance and color- difference samples and the following Y1 byte refers to the next luminance sample, per CCIR-656 standar ds (the clock frequency is dependent upon the current mode, and is not 27MHz as specified in CCIR-656). All non-active pixels should be 0 in RGB formats, and 16 for Y and 128 for CrCb in YCrCb formats.

3.3.1 Data De-skew Feature

The de-skew feature allows adjustment of the input setup and hold time. The input data D[11:0] can be latched slightly before or after the latching edge of XCLK depending on the amount of the de-skew. Note that the XCLK is not changed, only the time at which the data is latch relative to XCLK. .The de-skew is controlled using the XCMD[3:0] bits located in register 1Dh. The delay t CD between clock and data is given by the following formula: tCD = - XCMD[3:0] * t STEP for 0 ≤ XCMD[3:0] ≤ 7 t CD = (XCMD[3:0] – 8) * t STEP for 8 ≤ XCMD[3:0] ≤ 15 where XCMD is a number between 0 and 15 represented as a binary code tSTEP is the adjustment increment (See Table 17 ) The delay is also tabulated in Table 9 .

Figure 4. Multiplexed Input Data Formats (IDF = 0, 1)

Figure 5. Multiplexed Input Data Formats (IDF = 2, 3, 4)

Table 4. Multiplexed Input Data Formats (IDF = 0, 1) Table 5. Multiplexed Input Data Formats (IDF = 2, 3) Table 6. Multiplexed Input Data Formats (IDF = 4)

Bits S[7] and S[3..0] are ignored. Table 7. Embedded Sync

201-0000-056 Rev. 2.1, 01/07/2014 13 CHRONTEL CH7301C 4. R EGISTER C ONTROL The CH7301C is controlled via a serial port. The s erial port bus uses only the SPC clock to latch dat a into registers, and does not use any internally generated clocks so tha t the device can be written to in all power down mo des. The device retains all register states.

4.1 Control Registers Map

The controls are listed below, divided into three s ections: general controls, input / output controls, DVI controls. A register map and register description follows.

• General Controls ResetIB Software serial reset ResetDB Software datapath reset PD[7:0] Power down controls (DVIP, DVIL, TVD, DACPD[ 2:0], FDP) VID[7:0] Version ID register DID[7:0] Device ID register TSTP[1:0] Enable/select test pattern generation (col or bar, ramp)
• Input/Output Controls XCM XCLK 1X, 2X select XCMD[3:0] Delay adjust between XCLK and D[11:0] MCP XCLK polarity control IDF[2:0] Input data format GPIOL[1:0] Read or write level for GPIO pins GOENB[1:0] Direction control for GPIO pins SYNCO[1:0] Enables/selects sync output for RGB and b ypass modes DACG[1:0] DAC gain control DACBP DAC bypass DES Decode embedded sync HSP H sync polarity control VSP V sync polarity control T_RGB YCrCb to RGB enable
• DVI Controls CTL[3:0] DVI Control Inputs DVID[2:0] DVI transmitter drive strength control DVIP DVI Power Down Control DVIL DVI Power Down Control DVIT Hot Plug Detection Pin Level HPDD Hot Plug Detection Disable HPIE Hot Plug Interrupt Enable on GPIO[1] HPIR Hot Plug Interrupt Reset TPFBD[3:0] DVI PLL feed back divider TPCP[1:0] DVI PLL charge pump trim TPFFD[1:0] DVI PLL feed forward divider TPPSD[1:0] DVI PLL post scale divider TPLPF[3:0] DVI PLL low pass filter DVII DVI output invert TMSYO DVI Sync Direction LOCKST DVI PLL lock state

4.2 Registers Read/Write

Regarding the CH7301C registers read/write operation, please see applications note AN-41 for details. All register bits not defined in the register map are reserved bits, and should be left at the default value. Table 8. Serial Port Register Map

the following table. t STEP is given in Table 17 . Table 9. Delay applied to XCLK before latching input data D[11:0]

16 201-0000-056 Rev. 2.1, 01/07/2014 Bit 3 of register GPIO resets the hot plug detectio n circuitry. A value of ‘1’ causes the CH7301C to release the GPIO[1]/HPINT pin. When a hot plug interrupt is as serted by the CH7301C, the CH7301C driver should re ad the DVIT bit in register 20h to determine the state of the DVI termination. After having read this, the H PIR bit should be set high to reset the circuit, and then set low again. In order to reset the HPIR bit high, DVIP an d DVIL bits of register 49h[7:6] must first be set to ’11’. Bits 5-4 of register GPIO defines the GPIO Read or Write Data bits [1:0]. When the corresponding GOEN B bits (GOENB[1:0]) are ’0’, the values in GPIOL[1:0] are driven out at the corresponding GPIO pins. When th e corresponding GOENB bits are ’1’, the values in GPI OL[1:0] can be read to determine the level forced i nto the corresponding GPIO pins. Bits 7-6 of register GPIO are GPIO Direction Contro l bits [1:0]. GOENB[1:0] control the direction of the GPIO[1:0] pins. A value of ‘1’ sets the correspond ing GPIO pin to an input, and a value of ‘0’ sets t he corresponding pin to a non-inverting output. The le vel at the output depends on the value of the corre sponding bit GPIOL[1:0]. Input Data Format Register Symbol: IDF Address: 1Fh Bits 2-0 of register IDF select the input data form at. See Input Interface on section 3.3 on page 8 f or a listing of available formats. HSP (bit 3) of register IDF controls the horizontal sync polarity. A value of ’0’ defines the horizon tal sync to be active low, and a value of ’1’ defines the horizont al sync to be active high. VSP (bit 4) of register IDF controls the vertical s ync polarity. A value of ’0’ defines the vertical sync to be active low, and a value of ’1’ defines the vertical sync t o be active high. DES (bit 6) of register IDF signifies when the CH73 01C is to decode embedded sync signals present in t he input data stream instead of using the H and V pins. This feature is only available for input data format #4. A value of ’0’ selects the H and V pins to be used as the sync inp uts, and a value of ’1’ selects the embedded sync s ignal. Connection Detect Register Symbol: CD Address: 20h The Connection Detect Register provides a means to determine the status of the DAC outputs and the DVI hot plug BIT: 7 6 5 4 3 2 1 0 SYMBOL: Reserved DES Reserved VSP HSP IDF2 IDF1 IDF0 TYPE: R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT: 1 0 0 0 0 0 0 0 BIT: 7 6 5 4 3 2 1 0 SYMBOL: HPIE Reserved DVIT Reserved DACT2 DACT1 DACT0 SENSE TYPE: R/W R/W R R/W R R R R/W DEFAULT: 0 0 0 0 X X X 0

201-0000-056 Rev. 2.1, 01/07/2014 17 CHRONTEL CH7301C detect pin. The status bits, DACT[2:0] correspond to the termination of the three DAC outputs. However, the values contained in these STATUS BITS ARE NOT V ALID until a sensing procedure is performed. Use of this regis ter requires a sequence of events to enable the sensing of outputs, then reading out the applicable status bits. The detection sequence works as follows: 1) Set the power management register (Register 49h) to enable all DAC’s, and set register 21h[0] = ’0’ . 2) Set the SENSE bit to a 1. This forces a constan t output from the DAC’s. 3) Reset the SENSE bit to 0. This triggers a comp arison between the voltage present on these analog outputs and the reference value. During this step, each of the three status bits corresponding to individual DAC outputs will be set if they are CONNECTED. 4) Read the status bits. The status bits, DACT[2:0 ] now contain valid information which can be read t o determine which outputs are connected to a display monitor. Again, a “1” indicates a valid connection, a “0” indicate s an unconnected output. Bit 5 of register CD can be read at any time to determine the level of the hot plug detection pin (HPDET). When the HPDET is low, the DVI output driver will be shut do wn. When the hot plug detect pin changes state, and the DVI output is selected, the HPINT output pin will be pu lled low signifying a change in the DVI termination . At this point, the HPIR bit in register 1Eh should be set h igh, then low to reset the hot plug detect circuit. Bit 7 of register CD enables the hot plug interrupt detection signal output from the GPIO[1]/HPINT pin. A value of ‘1’ allows the hot plug detect circuit to pull the GPIO[1]/HPINT pin low when a change of state has ta ken place on the hot plug detect pin (HPDET). A value of ‘0’ di sables the interrupt signal. See also the descript ion of the DVIT bit. DAC Control Register Symbol: DC Address: 21h Bit 0 of register DC selects the DAC bypass mode. If the input data format is digital RGB, a value of ‘1’ outputs the incoming data directly at the DAC[2:0] outputs for the VGA-Bypass RGB output. If the input data forma t is digital YCrCb, bit 0 of register 56h must be set to ’1’, to gether with bit 0 of register 21h set to ’1’, to ou tput the analog RGB from the DACs. Bits 2-1 of register DC control the DAC gain. DACG 1 should be low when the input data format is RGB ( IDF = 0- 3), and high when the input data format is YCrCb (I DF = 4). Bits 3 of register DC enables the HSYNC and VSYNC o utputs. BIT: 7 6 5 4 3 2 1 0 SYMBOL: Reserved Reserved Reserved Reserved SYNCO0 DACG1 DACG0 DAC BP TYPE: R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT: 0 0 0 0 0 0 0 0

18 201-0000-056 Rev. 2.1, 01/07/2014 Hot Plug Detection Register Symbol: HPD Address: 23h HPDD (bit 2) of register HPD disables the hardware hot plug detection function. This function (default on) tri-states the DVI outputs when the hot plug detect pin (HPDET) is pulled low in accordance with the DVI specification, revision 1.0. This function is independent of the hot plug interrupt function (HPIE, register 20h, bit 7) controlled via the SPP interface. HPDD = 0 => hardware hot plug interrupt is enabled = 1 => hardware hot plug interrupt is disabled DVI Control Input Register Symbol: TCTL Address: 31h Bits 3-0 of register TCTL set the DVI control input s applied to the green and red channels during sync intervals. It is recommended to leave these controls at the defau lt value. Bits 7-4 of register TCTL control the DVI PLL phase detector. The default value is recommended. BIT: 7 6 5 4 3 2 1 0 SYMBOL: Reserved Reserved Reserved Reserved Reserved HPDD Reserve d Reserved TYPE: R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT: 0 0 0 0 0 0 0 0 BIT: 7 6 5 4 3 2 1 0 SYMBOL: TPPD3 TPPD 2 TPPD 1 TPPD 0 CTL3 CTL2 CTL1 CTL0 TYPE: R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT: 1 0 0 0 0 0 0 0

201-0000-056 Rev. 2.1, 01/07/2014 19 CHRONTEL CH7301C DVI PLL Charge Pump Control Register Symbol: TPCP Address: 33h Bit 0 of register TPCP control the DVI PLL charge p ump. Bits 3-2 of register TPCP control the DVI PLL post scale divider. The value should be set as shown in Table 10 depending on the input frequency range. Bit 4 of register TPCP inverts the DVI outputs. A value of 1 inverts the output. A value of 0 is rec ommended. Bits 7-5 of register TPCP control the DVI transmitt er output drive level. The value should be set as shown in Table 10. DVI PLL Divider Register Symbol: TPD Address: 34h Bits 3-0 of register TPD control the DVI PLL feedback divider. The default value is recommended. Bits 5-4 of register TPD control the DVI PLL feed forward divider. The default value is recommended. Please see Table 10 for the default values in terms of the frequency ranges. DVI PLL Supply Control Register Symbol: TPVT Address: 35h This register controls the voltage in the DVI PLL, use default settings for this register. BIT: 7 6 5 4 3 2 1 0 SYMBOL: DVID2 DVID1 DVID0 DVII TPPSD1 TPPSD0 Reserved TPCP0 TYPE: R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT: 1 1 1 0 0 1 0 0 BIT: 7 6 5 4 3 2 1 0 SYMBOL: Reserved Reserved TPFFD1 TPFFD0 TPFBD3 TPFBD2 TPFBD1 TPFBD 0 TYPE: R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT: 0 0 0 1 0 1 1 0 BIT: 7 6 5 4 3 2 1 0 SYMBOL: Reserved Reserved Reserved Reserved Reserved Reserved Res erved Reserved TYPE: R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT: 0 0 1 1 0 0 0 0

Bits 3-0 of register TPF are reserved bits, and sho uld be left at the default value. Bits 7-4 of register TPF control the DVI PLL low pa ss filter. The default value is recommended. Please see Table 10 for the default values in terms of the frequency ranges. This register is used for internal testing. The default value is recommended. Table 10. The Registers Default Settings In Terms Of The Frequency Ranges

output and the display monitor output. The pattern generated is determined by Table 11 below. generated power on reset signal. at power on by an internally generated power on res et signal. Register PM controls which circuitry within the CH7301C is operating, according to Table 12 below. Table 11. Test Pattern Control

00 No test pattern – Input data is used

01 Color Bars

Table 12. Power Management

22 201-0000-056 Rev. 2.1, 01/07/2014 Version ID Register Symbol: VID Address: 4Ah Register VID is a read only register containing the version ID number of the CH7301C. Device ID Register Symbol: DID Address: 4Bh Register DID is a read only register containing the device ID number of the CH7301C. Lock State Register Symbol: LOCK Address: 4Dh LOCKST (bit2 ) of register LOCK reveals the state o f the DVI PLL. "1" means locked. "0" otherwise. BIT: 7 6 5 4 3 2 1 0 SYMBOL: VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 TYPE: R R R R R R R R DEFAULT: 1 0 0 1 0 1 0 1 BIT: 7 6 5 4 3 2 1 0 SYMBOL: DID7 DID6 DID5 DID4 DID3 DID2 DID1 DID0 TYPE: R R R R R R R R DEFAULT: 0 0 0 1 0 1 1 1 BIT: 7 6 5 4 3 2 1 0 SYMBOL: Reserved Reserved Reserved Reserved Reserved LOCKST Reser ved Reserved TYPE: R R R R R R R R DEFAULT: 0 0 0 1 0 1 1 1

201-0000-056 Rev. 2.1, 01/07/2014 23 CHRONTEL CH7301C DVI Sync Polarity Register Symbol: DSP Address: 56h T_RGB (bit 0) of register DSP enables the YCrCb to RGB color space conversion T_RGB = 0 => Disable YCrCb to RGB conversion = 1 => Enable YCrCb to RGB conversion TMSYO (bit 5) of register DSP determines the polarity of embedded sync for DVI, if 0, flip H, V for DVI. BIT: 7 6 5 4 3 2 1 0 SYMBOL: Reserved Reserved TMSYO Reserved Reserved Reserved Reserv ed T_RGB TYPE: R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT: 0 0 0 0 0 0 0 0

1. E LECTRICAL S PECIFICATIONS
2. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. These

all standard and lead free parts.

1. The device is fabricated using high-performance C MOS technology. It should be handled as an ESD sens itive device.

V oltage on any signal pin that exceeds the power supply voltages by more than ± 0.5V can induce destructive latchup. Table 14. Recommended Operating Conditions Table 15. Electrical Characteristics (Operating Conditions: T A = 0 oC - 70 oC, VDD = 3.3V ± 5%)

HPDET inputs and GPIOx, VSYNC and HSYNC outputs. Table 16. DC Specifications

Table 17. AC Specifications

201-0000-056 Rev. 2.1, 01/07/2014 27 CHRONTEL CH7301C

5.1 Timing Information

5.1.1 Clock - Slave, Sync - Slave Mode

Figure 6: Timing for Clock - Slave, Sync - Slave M ode Table 18: Timing for Clock - Slave, Sync - Slave Mode Symbol Parameter Min Typ Max Unit tS Setup Time: D[11:0], H, V and DE to XCLK, XCLK* See Table 17 tH Hold Time: D[11:0], H, V and DE to XCLK, XCLK* See Table 17 t1 XCLK & XCLK* rise/fall time w/15pF load 1 ns t2 D[11:0], H, V & DE rise/fall time w/ 15pF load 1 ns D[11:0] XCLK H V P0a P0b P1a P1b DE

64 PIXELS

1 VGA

XCLK* t2 t2 tS tH V IH V IL V IH V IL V IH V IL V IH V IL V IH V IL V IH V IL tS tS tH

28 201-0000-056 Rev. 2.1, 01/07/2014 6. PACKAGE D IMENSIONS 64-pin LQFP Table of Dimensions Notes: 1. Conforms to JEDEC standard JESD-30 MS-026D. 2. Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm. 3. Dimension B does not include allowable mold protr usions up to 0.25 mm per side. No. of Leads SYMBOL 64 (10 X 10 mm) A B C D E F G H I J Milli- meters A C D I H J G E BA F .004 “ LEAD CO-PLANARITY B

201-0000-056 Rev. 2.1, 01/07/2014 29 CHRONTEL CH7301C 7. R EVISION H ISTORY Rev. # Date Section Description 1.0 03/07/03 All First official release of CH7301C dat asheet, rev. 1.0 1.1 09/08/03 Table 2 Edited Table 2 for DVI output res olutions 1.2 9/18/03 Figure 1 Added ’Color space conversion and sync decode’ block. 56h Added register 56h, bit 0 for YCrCb to RGB color space conversion. 56h Added bit 5 for DVI embedded sync polarity contr ol 1.3 7/12/04 1Eh Updated DVI hotplug description 1.31 2/1/05 6.0 Updated order information 1.32 5/24/05 6.0 Updated package dimension 1.33 2/6/08 Features, Table 2 Added 1920x1200 reduced blanking resolution. 1.4 8/4/08 Table 16 Updated Table 16. DC Specificaiton s. 1.5 3/17/2010 4Dh Added register 4Dh. 2.0 8/17/2011 5.0 Spec update 2.1 1/7/2014 5.0 Move TAMB from Table 13 to Table 14 and change its max. ambient operating temperature from 85 °C to 70 °C

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ORDERING INFORMATION

Part number Package type Number of pins Voltage supply CH7301C-TF Lead free LQFP 64 3.3V CH7301C-TF-TR Lead free LQFP in Tape & Reel 64 3.3V 30 201-0000-056 Rev. 2.1, 01/07/2014 CHRONTEL Disclaimer This document provides technical information for th e user. Chrontel reserves the right to make changes at any time with- out notice to improve and supply the best possible product and is not responsible and does not assume any liability for misapplication or use outside the limits specified in this document. We provide no warranty for the u se of our products and assume no liability for errors contained in thi s document. The customer should make sure that the y have the most recent data sheet version. Customers should take a ppropriate action to ensure their use of the produc ts does not infringe upon any patents. Chrontel, Inc. respects valid pa tent rights of third parties and does not infringe upon or assist others to infringe upon such rights. Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT TH E SPECIFIC WRITTEN CONSENT OF Chrontel. Life support systems are those intended to support or sustain life and whose failure to per form when used as directed can reasonably expect to result in personal injury or death.