CEM11M2 CET | Alldatasheet

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Technical content

Dual N-Channel Enhancement Mode Field Effect Transistor 5 | FEATURES oO, GA, Riwm=2ing —eVis=d. SY, Risan=31nQ —Vs=2. SV. Ds iy Oe ba Super high dense cell design for extreaely low Risww. LI LI ¢ High porer and current handing capability. (PAN (PAY Surface Mount Package, i a7 son S1 G1 S2 G2 ABSOLUTE MAXIMUM RATINGS (Ta=25°C unless otherwise noted) rom | ott Ce Drain Current-Continuous — ¢Tj=12 C pou {| to [oa | Phaeton |e] Operat ing Junction and Storage Ty, Ts 55 to 150 Py Teaperature Range : ” " THERMAL CHARACTERISTICS 5.2

ELECTRICAL CHARACTERISTICS (Ta=28°C unless otherwise noted) [tae tl oon | ts CS | Nie Sue Wein tae [ois | ebm To] | [v | eo tae cg tnt | os | to-mw | | [a [a] aehytate | ts | eet ieot | | fel | Ge rebihtge [tow | os oem [ese] 1 [| Paesecasitne |p PEER | tala Pease | fala fo] feiactantee [ow | westtnas tal | [a] iver tases | ts | wanna [1 [el [s | ane a Te watie® Ta mcs am | [ae [ol Both Cea mais il eee | Lelia fit Sid | re fe [| Ppa]

b Pulse Test:Pulse Width <300 ps, Duty Cycle < 2%. c.Guaranteed by design, not subject to production testing. Figure 1. Output Characteristics Figure 2. Transfer Characteristics

Figure 5. Gate Threshold Variation Figure 6. Breakdown Voltage Variation Figure 7. Transconductance Variation Figure 8. Body Diode Forward Voltage

3 LAL) = Basi: SEE Et

2 TV f et RS

Figure 9. Gate Charge Figure 10. Maximum Safe

Figure 11. Switching Test Circuit Figure 12. Switching Waveforms

2 SS eee ey

2 Fea Ps Satie tar

Figure 13. Normalized Thermal Transient Impedance Curve