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8-Channel Differential DAS with 18-Bit, Bipolar, Simultaneous Sampling ADC Data Sheet AD7609 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.

FEATURES

8 simultaneously sampled inputs True differential inputs True bipolar analog input ranges: ±10 V, ±5 V Single 5 V analog supply and 2.3 V to 5.25 V VDRIVE Fully integrated data acquisition solution Analog input clamp protection Input buffer with 1 MΩ analog input impedance Second-order antialiasing analog filter On-chip accurate reference and reference buffer 18-bit ADC with 200 kSPS on all channels Oversampling capability with digital filter Flexible parallel/serial interface SPI/QSPI™/MICROWIRE™/DSP compatible Performance 7 kV ESD rating on analog input channels 98 dB SNR, −107 dB THD Dynamic range: up to 105 dB typical Low power: 100 mW Standby mode: 25 mW 64-lead LQFP package

APPLICATIONS

Power line monitoring and protection systems Multiphase motor control Instrumentation and control systems Multiaxis positioning systems Data acquisition systems (DAS) COMPANION PRODUCTS External References: ADR421, ADR431 Digital Isolators: ADuM1402, ADuM5000, ADuM5402 Power: ADIsimPower, Supervisor Parametric Search Additional companion products on the AD7609 product page Table 1. High Resolution, Bipolar Input, Simultaneous

18 Bits AD7608 AD76091 8

16 Bits AD7606 8

14 Bits AD7607 8

Rev. A | Page 2 of 36 TABLE OF CONTENTS

REVISION HISTORY

2/12—Rev. 0 to Rev. A 7/11—Revision 0: Initial Version

Rev. A | Page 3 of 36 GENERAL DESCRIPTION The AD7609 is an 18-bit, 8-channel, true differential, simultaneous sampling analog-to-digital data acquisition system (DAS). The part contains analog input clamp protection, a second-order antialiasing filter, a track-and-hold amplifier, an 18-bit charge redistribution successive approximation analog- to-digital converter (ADC), a flexible digital filter, a 2.5 V reference and reference buffer, and high speed serial and parallel interfaces. The AD7609 operates from a single 5 V supply and can accommodate ±10 V and ±5 V true bipolar differential input signals while sampling at throughput rates up to 200 kSPS for all channels. The input clamp protection circuitry can tolerate voltages up to ±16.5 V. T h e AD7609 has 1 MΩ analog input impedance regardless of sampling frequency. The single supply operation, on-chip filtering, and high input impedance elimi- nate the need for driver op amps and external bipolar supplies. The AD7609 antialiasing filter has a −3 dB cutoff frequency of 32 kHz and provides 40 dB antialias rejection when sampling at 200 kSPS. The flexible digital filter is pin driven, yields improvements in SNR, and reduces the −3 dB bandwidth.

Rev. A | Page 4 of 36 SPECIFICATIONS noted.1 Table 2. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE fIN = 1 kHz sine wave unless otherwise noted Signal-to-Noise Ratio (SNR)2, 3 Oversampling by 16; ±10 V range; fIN = 160 Hz 98 101 dB Oversampling by 16; ±5 V range; fIN = 160 Hz 100 dB No oversampling; ±10 V range 90 91 dB No oversampling; ±5 V range 89.5 90.5 dB Signal-to-(Noise + Distortion) (SINAD)2 No oversampling; ±10 V range 89.5 91 dB No oversampling; ±5 V range 89 90 dB Dynamic Range No oversampling; ±10 V range 91.5 dB No oversampling; ±5 V range 90.5 dB Total Harmonic Distortion (THD)2, 3 No oversampling; ±10 V range −107 −97 dB No oversampling; ±5 V range −110 −96 dB Peak Harmonic or Spurious Noise (SFDR)2 −108 dB Intermodulation Distortion (IMD)2 fa = 1 kHz, fb = 1.1 kHz Second-Order Terms −110 dB Third-Order Terms −106 dB Channel-to-Channel Isolation2 fIN on unselected channels up to 160 kHz −95 dB ANALOG INPUT FILTER Full Power Bandwidth −3 dB, ±10 V range 32 kHz −3 dB, ±5 V range 23 kHz −0.1 dB, ±10 V range 13 kHz −0.1 dB, ±5 V range 10 kHz tGROUP DELAY ±10 V range 7.1 µs ±5 V range 10.2 µs DC ACCURACY Resolution No missing codes 18 Bits Differential Nonlinearity2 ±0.75 −0.99/+2 LSB4 Integral Nonlinearity2 ±3 ±7.5 LSB Total Unadjusted Error (TUE) ±10 V range ±10 LSB ±5 V range ±90 LSB Positive Full-Scale Error2, 5 External reference ±8 ±140 LSB Internal reference ±40 LSB Positive Full-Scale Error Drift External reference ±2 ppm/°C Internal reference ±7 ppm/°C Positive Full-Scale Error Matching2 ±10 V range 12 80 LSB ±5 V range 40 100 LSB Bipolar Zero Code Error2, 6 ±10 V range ±3 ±24 LSB ± 5 V range ±3 ±48 LSB Bipolar Zero Code Error Drift ±10 V range 10 µV/°C ± 5 V range 5 µV/°C Bipolar Zero Code Error Matching2 ±10 V range 2.7 30 LSB ±5 V range 13 65 LSB Negative Full-Scale Error2, 5 External reference ±8 ±140 LSB Internal reference ±40 LSB Negative Full-Scale Error Drift External reference ±4 ppm/°C Internal reference ±8 ppm/°C Negative Full-Scale Error Matching2 ±10 V range 12 80 LSB ±5 V range 40 100 LSB

Rev. A | Page 5 of 36 Parameter Test Conditions/Comments Min Typ Max Unit ANALOG INPUT Differential Input Voltage Ranges VIN = Vx+ − (Vx−) RANGE = 1; ±10 V −20 +20 V RANGE = 0; ±5 V −10 +10 V Absolute Voltage Input ±10 V range, see the Analog Input Clamp Protection section −10 +10 V ±5 V range, see the Analog Input Clamp Protection section −5 +5 V Common-Mode Input Range −4 ±5 +4 V CMRR −70 dB Analog Input Current 10 V, see Figure 28 5.4 µA 5 V, see Figure 28 2.5 µA Input Capacitance7 5 pF Input Impedance 1 MΩ REFERENCE INPUT/OUTPUT Reference Input Voltage Range 2.475 2.5 2.525 V DC Leakage Current ±1 µA Input Capacitance7 REF SELECT = 1 7.5 pF Reference Output Voltage REFIN/REFOUT 2.49/ 2.505 V Reference Temperature Coefficient ±10 ppm/°C LOGIC INPUTS Input High Voltage (VINH) 0.7 × VDRIVE V Input Low Voltage (VINL) 0.3 × VDRIVE V Input Current (IIN) ±2 µA Input Capacitance (CIN)7 5 pF LOGIC OUTPUTS Output High Voltage (VOH) ISOURCE = 100 µA VDRIVE − 0.2 V Output Low Voltage (VOL) ISINK = 100 µA 0.2 V Floating-State Leakage Current ±1 ±20 µA Floating-State Output Capacitance7 5 pF Output Coding Twos complement CONVERSION RATE Conversion Time All eight channels included 4 µs Track-and-Hold Acquisition Time 1 µs Throughput Rate Per channel, all eight channels included 200 kSPS POWER REQUIREMENTS AVCC 4.75 5.25 V VDRIVE 2.3 5.25 V ITOTAL Digital inputs = 0 V or VDRIVE Normal Mode (Static) 16 22 mA Normal Mode (Operational)8 fSAMPLE = 200 kSPS 20 28.5 mA Standby Mode 5 8 mA Shutdown Mode 2 11 µA

Rev. A | Page 6 of 36 Parameter Test Conditions/Comments Min Typ Max Unit Power Dissipation Normal Mode (Static) 80 115.5 mW Normal Mode (Operational)8 fSAMPLE = 200 kSPS 100 157 mW Standby Mode 25 42 mW Shutdown Mode 10 60.5 µW 1 Temperature range for B version is −40°C to +85°C. 2 See the Terminology section. 3 This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel and serial modes with VDRIVE = 5 V, SNR typically reduces by 1.5 dB and THD by 3 dB. 5 These specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from the external reference. 6 Bipolar zero code error is calculated with respect to the analog input voltage. See the Analog Input Clamp Protection section. 7 Sample tested during initial release to ensure compliance. 8 Operational power/current figure includes contribution when running in oversampling mode.

Rev. A | Page 7 of 36 TIMING SPECIFICATIONS unless otherwise noted.1 Table 3. Limit at TMIN, TMAX Parameter Min Typ Max Unit Description PARALLEL/SERIAL/BYTE MODE tCYCLE 1/throughput rate 5 µs Parallel mode, reading during; or after conversion VDRIVE = 2.7 V to 5.25 V; or serial mode: VDRIVE = 3.3 V to 5.25 V, reading during a conversion using DOUTA and DOUTB lines 5 µs Parallel mode reading after conversion VDRIVE = 2.3 V 10.1 µs Serial mode reading after conversion; VDRIVE = 2.7 V, DOUTA and DOUTB lines 11.5 µs Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines tCONV Conversion time 3.45 4 4.15 µs Oversampling off 7.87 9.1 µs Oversampling by 2 16.05 18.8 µs Oversampling by 4 33 39 µs Oversampling by 8 66 78 µs Oversampling by 16 133 158 µs Oversampling by 32 257 315 µs Oversampling by 64 tWAKE-UP STANDBY 100 µs STBY rising edge to CONVST x rising edge; power-up time from standby mode tWAKE-UP SHUTDOWN Internal Reference 30 ms STBY rising edge to CONVST x rising edge; power-up time from shutdown mode External Reference 13 ms STBY rising edge to CONVST x rising edge; power-up time from shutdown mode tRESET 50 ns RESET high pulse width tOS_SETUP 20 ns BUSY to OS x pin setup time tOS_HOLD 20 ns BUSY to OS x pin hold time t1 45 ns CONVST x high to BUSY high t2 25 ns Minimum CONVST x low pulse t3 25 ns Minimum CONVST x high pulse t4 0 ns BUSY falling edge to CS falling edge setup time t52 0.5 ms Maximum delay allowed between CONVST A, CONVST B rising edges t6 25 ns Maximum time between last CS rising edge and BUSY falling edge t7 25 ns Minimum delay between RESET low to CONVST x high PARALLEL READ OPERATION t8 0 ns CS to RD setup time t9 0 ns CS to RD hold time t10 RD low pulse width 19 ns VDRIVE above 4.75 V 24 ns VDRIVE above 3.3 V 30 ns VDRIVE above 2.7 V 37 ns VDRIVE above 2.3 V t11 15 ns RD high pulse width t12 22 ns CS high pulse width (see Figure 5); CS and RD linked

Rev. A | Page 8 of 36 Limit at TMIN, TMAX Parameter Min Typ Max Unit Description t13 Delay from CS until DB[15:0] three-state disabled 19 ns VDRIVE above 4.75 V 24 ns VDRIVE above 3.3 V 30 ns VDRIVE above 2.7 V 37 ns VDRIVE above 2.3 V t143 Data access time after RD falling edge 19 ns VDRIVE above 4.75 V 24 ns VDRIVE above 3.3 V 30 ns VDRIVE above 2.7 V 37 ns VDRIVE above 2.3 V t15 6 ns Data hold time after RD falling edge t16 6 ns CS to DB[15:0] hold time t17 22 ns Delay from CS rising edge to DB[15:0] three-state enabled SERIAL READ OPERATION fSCLK Frequency of serial read clock 20 MHz VDRIVE above 4.75 V 15 MHz VDRIVE above 3.3 V 12.5 MHz VDRIVE above 2.7 V 10 MHz VDRIVE above 2.3 V t18 Delay from CS until DOUTA/DOUTB three-state disabled/delay from CS until MSB valid 18 ns VDRIVE above 4.75 V 23 ns VDRIVE above 3.3 V 35 ns VDRIVE = 2.3 V to 2.7 V t193 Data access time after SCLK rising edge 20 ns VDRIVE above 4.75 V 26 ns VDRIVE above 3.3 V 32 ns VDRIVE above 2.7 V 39 ns VDRIVE above 2.3 V t20 0.4 tSCLK ns SCLK low pulse width t21 0.4 tSCLK ns SCLK high pulse width t22 7 SCLK rising edge to DOUTA/DOUTB valid hold time t23 22 ns CS rising edge to DOUTA/DOUTB three-state enabled FRSTDATA OPERATION t24 Delay from CS falling edge until FRSTDATA three-state disabled 18 ns VDRIVE above 4.75 V 23 ns VDRIVE above 3.3 V 30 ns VDRIVE above 2.7 V 35 ns VDRIVE above 2.3 V t25 ns Delay from CS falling edge until FRSTDATA high, serial mode 18 ns VDRIVE above 4.75 V 23 ns VDRIVE above 3.3 V 30 ns VDRIVE above 2.7 V 35 ns VDRIVE above 2.3 V t26 Delay from RD falling edge to FRSTDATA high 19 ns VDRIVE above 4.75 V 23 ns VDRIVE above 3.3 V 30 ns VDRIVE above 2.7 V 35 ns VDRIVE above 2.3 V

TA = 25°C, unless otherwise noted. 1 Transient currents of up to 100 mA do not cause SCR latch-up. specifications apply to a 4-layer board. Table 5. Thermal Resistance

Figure 7. Pin Configuration Table 6. Pin Function Descriptions amplifiers and to the ADC core. These supply pins should be decoupled to AGND. AGND pins should connect to the AGND plane of a system. analog inputs. The analog input range of these channels is determined by the RANGE pin. on this pin should be 180° out of phase with the corresponding Vx+ pin.

42 REF REFIN/

an external reference voltage must be applied to the REFIN/REFOUT pin. AGND using a low ESR 10 μF ceramic capacitor. 43, 46 REF REFGND Reference Ground Pins. These pins should be connected to AGND.

Rev. A | Page 13 of 36 Pin No. Type1 Mnemonic Description 8 DI RANGE Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog input channels. If this pin is tied to a logic high, the analog input range is ±10 V for all channels. If this pin is tied to a logic low, the analog input range is ±5 V for all channels. A logic change on this pin has an immediate effect on the analog input range. Changing this pin during a conversion is not recommended. See the Analog Input section for more details.

6 DI PAR/

Parallel/Serial Interface Selection Input. Logic input. If this pin is tied to a logic low, the parallel interface is selected. If this pin is tied to a logic high, the serial interface is selected. In serial mode, the RD/SCLK pin functions as the serial clock input. The DB7/DOUTA and DB8/DOUTB pins function as serial data outputs. When the serial interface is selected, the DB[15:9] and DB[6:0] pins should be tied to AGND. 9, 10 DI CONVST A, CONVST B Conversion Start Input A, Conversion Start Input B. Logic inputs. These logic inputs are used to initiate conversions on the analog input channels. For simultaneous sampling of all input channels, CONVST A and CONVST B can be shorted together and a single conversion start signal applied. Alternatively, CONVST A can be used to initiate simultaneous sampling for V1, V2, V3, and V4, and CONVST B can be used to initiate simultaneous sampling on the other analog inputs (V5, V6, V7, and V8). This is only possible when oversampling is not switched on. When the CONVST A or CONVST B pin transitions from low to high, the front-end track-and-hold circuitry for their respective analog inputs is set to hold. This function allows a phase delay to be created inherently between the sets of analog inputs. 13 DI CS Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic low in parallel mode, the output bus (DB[15:0]) is enabled and the conversion result is output on the parallel data bus lines. In serial mode, the CS is used to frame the serial read transfer and clocks out the MSB of the serial output data. 12 DI RD/SCLK Parallel Data Read Control Input When Parallel Interface is Selected (RD)/Serial Clock Input When Serial Interface is Selected (SCLK). When both CS and RD are logic low in parallel mode, the output bus is enabled. In parallel mode, two RD pulses are required to read the full 18 bits of conversion results from each channel. The first RD pulse outputs DB[17:2], and the second RD pulses outputs DB[1:0]. In serial mode, this pin acts as the serial clock input for data transfers. The CS falling edge takes the data output lines, DOUTA and DOUTB, out of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the serial data outputs, DOUTA and DOUTB. For further information, see the Conversion Control section. 14 DO BUSY Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising edges and indicates that the conversion process has started. The BUSY output remains high until the conversion process for all channels is complete. The falling edge of BUSY signals that the conversion data is being latched into the output data registers and will be available to be read after a time, t 4. Any data read while BUSY is high should be complete before the falling edge of BUSY occurs. Rising edges on CONVST A or CONVST B have no effect while the BUSY signal is high. 11 DI RESET Reset Input. When set to logic high, the rising edge of RESET resets the AD7609. The part must receive a RESET pulse after power-up. To achieve the specified performance after the RESET signal, the tWAKE_UP SHUTDOWN time should elapse between power-on and the RESET pulse. The RESET high pulse should be typically 100 ns wide. If a RESET pulse is applied during a conversion, the conversion is aborted. If a RESET pulse is applied during a read, the contents of the output registers reset to all zeros. 15 DO FRSTDATA Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back on either the parallel or serial interface. When the CS input is high, the FRSTDATA output pin is in three-state. The falling edge of CS takes FRSTDATA out of three-state. In parallel mode, the falling edge of RD corresponding to the result of V1 then sets the FRSTDATA pin high, indicating that the result from V1 is available on the output data bus. The FRSTDATA output returns to a logic low following the third falling edge of RD. In serial mode, FRSTDATA goes high on the falling edge of CS as this clocks out the MSB of V1 on DOUTA. It returns low on the 18th SCLK falling edge after the CS falling edge. See the Conversion Control section for more details. 7 DI STBY Standby Mode Input. This pin is used to place the AD7609 into one of two power-down modes: standby mode or shutdown mode. The power-down mode entered depends on the state of the RANGE pin, as shown in Table 8. When in standby mode, all circuitry except the on-chip reference, regulators, and regulator buffers is powered down. When in shutdown mode, all circuitry is powered down.

Rev. A | Page 14 of 36 Pin No. Type1 Mnemonic Description 5, 4, 3 DI OS [2:0] Oversampling Mode Pins. Logic inputs. These inputs are used to select the oversampling ratio. OS 2 is the MSB control bit, and OS 0 is the LSB control bit. See the Digital Filter section for additional details on the oversampling mode of operation and Table 9 for oversampling bit decoding. 33 DO/DI DB15 Parallel Output Data Bits, Data Bit 15. When PAR/SER SEL = 0, this pin acts as three-state parallel digital output pin. This pin is used to output DB17 of the conversion result during the first RD pulse and DB1 of the same conversion result during the second RD pulse. When PAR/SER SEL = 1, this pin should be tied to AGND. 32 DO/DI DB14 Parallel Output Data Bits, Data Bit 14. When PAR/SER SEL = 0, this pin acts as three-state parallel digital output pin. When CS and RD are low, this pin is used to output DB16 of the conversion result during the first RD pulse and DB0 of the same conversion result during the second RD pulse. When PAR/SER SEL = 1, this pin should be tied to AGND. 31 to 27 DO DB[13:9] Parallel Output Data Bits, Data Bit 13 to Data Bit 9. When PAR/SER SEL = 0, these pins act as three-state parallel digital input/output pins. When CS and RD are low, these pins are used to output DB15 to DB11 of the conversion result during the first RD pulse and output 0 during the second RD pulse. When PAR/SER SEL = 1, these pins should be tied to AGND. 24 DO DB7/DOUTA Parallel Output Data Bit 7 (DB7)/Serial Interface Data Output Pin (DOUTA). When PAR/SER SEL = 0, this pins acts as a three-state parallel digital input/output pin. When CS and RD are low, this pin is used to output DB9 of the conversion result. When PAR/SER SEL = 1, this pin functions as DOUTA and outputs serial conversion data. See the Conversion Control section for further details. 25 DO DB8/DOUTB Parallel Output Data Bit 8 (DB8)/Serial Interface Data Output Pin (DOUTB). When PAR/SER SEL = 0, this pins acts as a three-state parallel digital input/output pin. When CS and RD are low, this pin is used to output DB10 of the conversion result. When PAR/SER SEL = 1, this pin functions as DOUTB and outputs serial conversion data. See the Conversion Control section for further details. 22 to 16 DO DB[6:0] Parallel Output Data Bits, Data Bit 6 to Data Bit 0. When PAR/SER SEL = 0, these pins act as three-state parallel digital input/output pins. When CS and RD are low, these pins are used to output DB8 to DB2 of the conversion result during the first RD pulse and output 0 during the second RD pulse. When PAR/SER SEL = 1, these pins should be tied to AGND. 1 Refers to classification of pin type; P denotes power, AI denotes analog input, REF denotes reference, DI denotes digital input, DO denotes digital output.

16384 POINT FFT

Figure 8. FFT Plot, ±10 V Range Figure 9. FFT Plot, ±5 V Range

8192 POINT FFT

Figure 10. FFT Plot, ±10 V Range Figure 11. Typical INL, ±10 V Range Figure 12. Typical DNL, ±10 V Range Figure 13. Typical INL, ±5 V Range

Figure 26. Dynamic Range vs. Oversampling Ratio

2.4980 REFOUT VOLTAGE (V)

Figure 27. Reference Output Voltage vs. Temperature for Different Supply Figure 28. Analog Input Current vs. Input Voltage Over Temperature Figure 29. Supply Current vs. Oversampling Rate Figure 30. PSRR Figure 31. CMRR vs. Common-Mode Ripple Frequency

Rev. A | Page 19 of 36 TERMINOLOGY Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a ½ LSB below the first code transition, and full scale at ½ LSB above the last code transition. Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Bipolar Zero Code Error The deviation of the midscale transition (all 1s to all 0s) from the ideal V IN voltage, that is, AGND. Bipolar Zero Code Error Match The difference in bipolar zero code error between any two input channels. Positive Full-Scale Error complement coding) should occur for an analog voltage 1½ LSB below the nominal full scale (9.99977 V for the ±10 V range and 4.99988 V for the ±5 V range). The positive full-scale error is the deviation of the actual level of the last transition from the ideal level. Positive Full-Scale Error Match The difference in positive full-scale error between any two input channels. Negative Full-Scale Error complement coding) should occur for an analog voltage ½ LSB above the negative full scale (−9.999923 V for the ±10 V range and −4.9999618 for the ±5 V range). The negative full-scale error is the deviation of the actual level of the first transition from the ideal level. Negative Full-Scale Error Match The difference in negative full-scale error between any two input channels. Track-and-Hold Acquisition Time The track-and-hold amplifier returns to track mode at the end of the conversion. The track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1 LSB, after the end of the conversion. See the Track-and-Hold Amplifiers section for more details. Signal-to-(Noise + Distortion) Ratio The measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f S/2, excluding dc). The ratio depends on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Thus, for an 18-bit converter, this is 110.12 dB. Total Harmonic Distortion (THD) The ratio of the rms sum of the harmonics to the fundamental. For the AD7609, it is defined as THD (dB) = 20log 98765432 V VVVVVVVV 22222222 +++++++ where: V1 is the rms amplitude of the fundamental. V2 to V9 are the rms amplitudes of the second through ninth harmonics. Peak Harmonic or Spurious Noise The ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is determined by a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3. Intermodulation distortion terms are those for which neither m nor n is equal to 0. For example, the second-order terms include (fa + fb) and (fa − fb), and the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels (dB).

Rev. A | Page 20 of 36 Power Supply Rejection (PSR) Variations in power supply affect the full-scale transition but not the converter’s linearity. Power supply rejection is the maximum change in full-scale transition point due to a change in power supply voltage from the nominal value. The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC V DD and VSS supplies of Frequency fS. PSRR (dB) = 10 log (Pf/PfS) where: Pf is equal to the power at Frequency f in the ADC output. PfS is equal to the power at Frequency fS coupled onto the VDD and VSS supplies. Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between any two channels. It is measured by applying a full-scale, 10 kHz sine wave signal to all unselected input channels and determining the degree to which the signal attenuates in the selected channel with a 1 kHz signal. Common-Mode Rejection Ratio (CMRR) CMRR is defined as the ratio of the power in the ADC common-mode input at full-scale frequency, f, to the power in the output of a full-scale p-p sine wave applied to the common- mode voltage of VINX+ and VINX− of frequency, fS, CMRR (dB) = 20 log (Pf/PfS) where: Pf is equal to the power at Frequency f in the ADC input. PfS is equal to the power at Frequency fS in the ADC output.

Rev. A | Page 22 of 36 Analog Input Antialiasing Filter An analog antialiasing filter is also provided on the AD7609. The filter is a second-order Butterworth. Figure 35 and Figure 36 show the frequency and phase response respectively of the analog antialiasing filter. In the ±5 V range, the −3 dB frequency is typically 23 kHz. In the ±10 V range, the −3 dB frequency is typically 32 kHz. –40 –35 –30 –25 –20 –15 –10 100 1k 10k 100k ATTENUATION (dB) FREQUENCY (Hz) 10V DIFF 5V DIFF 09760-032 10V 0.1dBTEMP 3dB –40°C 13,354Hz 33,520Hz 25°C 12,769Hz 32,397Hz 85°C 12,427Hz 31,177Hz –40°C 10,303Hz 24,365Hz 25°C 9619Hz 23,389Hz 85°C 9326Hz 22,607Hz Figure 35. Analog Antialiasing Filter Frequency Response Figure 36. Analog Antialiasing Filter Phase Response to be sampled simultaneously in a system. for the next set of conversions begins. when reading during a conversion. transfer characteristic for the AD7609 is shown in Figure 37. Figure 37. AD7609 Transfer Characteristic Table 7. Output Codes and Ideal Input Values

Description

(V+ − (V−)

10 V Range

V+ − (V−)

5 V Range

Code (Hex) FSR − 0.5 LSB +19.99992 V 9.999961 V 0x1FFFF Midscale + 1 LSB +152.58 µV 76 µV 0x00001 Midscale 0 V 0 V 0x00000 Midscale – 1 LSB −152.58 µV −76 µV 0x3FFFF −FSR + 1 LSB −19.99984 V −9.99992 V 0x20001 −FSR −20 V −10 V 0x20000

single CONVST x signal is used to control both CONVST x inputs. simultaneous sampling on all analog input channels. bus (DB[15:0]) or the serial data lines, DOUTA and DOUTB. 60 Hz system, it allows for up to 10° of phase compensation. pendently and is only possible if oversampling is not in use. read process when using two separate CONVST x signals. because all channels are always converted. Figure 42. Simultaneous Sampling on Channel Sets Using Independent CONVST A/CONVST B Signals—Parallel Mode

rates. The OS pins are latched on the falling edge of BUSY . result is decimated to 18-bit resolution. input −3 dB bandwidth is limited to ~6 kHz. conversion time, see Table 9. Figure 45. OS Pin Timing Table 9. Oversampling Bit Decoding (100 Hz Input Signal)

111 Invalid

running in the north-to-south direction similar to Figure 62. Figure 62. Multiple AD7609 Layout, Top Layer and Supply Plane Layer

Figure 63. 64-Lead Low Profile Quad Flat Package [LQFP]

Rev. A | Page 35 of 36 NOTES

Rev. A | Page 36 of 36 NOTES ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D09760-0-2/12(A)