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8-/6-/4-Channel DAS with 16-Bit, Bipolar Input, Simultaneous Sampling ADC AD7606/AD7606-6/AD7606-4 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.

FEATURES

8/6/4 simultaneously sampled inputs True bipolar analog input ranges: ±10 V, ±5 V Single 5 V analog supply and 2.3 V to 5 V V DRIVE Fully integrated data acquisition solution Analog input clamp protection Input buffer with 1 MΩ analog input impedance Second-order antialiasing analog filter On-chip accurate reference and reference buffer 16-bit ADC with 200 kSPS on all channels Oversampling capability with digital filter Flexible parallel/serial interface SPI/QSPI™/MICROWIRE™/DSP compatible Performance 7 kV ESD rating on analog input channels 95.5 dB SNR, −107 dB THD ±0.5 LSB INL, ±0.5 LSB DNL Low power: 100 mW Standby mode: 25 mW 64-lead LQFP package

APPLICATIONS

Power-line monitoring and protection systems Multiphase motor control Instrumentation and control systems Multiaxis positioning systems Data acquisition systems (DAS) Table 1. High Resolution, Bipolar Input, Simultaneous

18 Bits AD7608 AD7609 8

16 Bits AD7606 8

14 Bits AD7607 8

Rev. 0 | Page 2 of 36 TABLE OF CONTENTS

REVISION HISTORY

5/10—Revision 0: Initial Version

Rev. 0 | Page 3 of 36 GENERAL DESCRIPTION The AD76061/AD7606-6/AD7606-4 are 16-bit, simultaneous sampling, analog-to-digital data acquisition systems (DAS) with eight, six, and four channels, respectively. Each part contains analog input clamp protection, a second-order antialiasing filter, a track-and-hold amplifier, a 16-bit charge redistribution successive approximation analog-to-digital converter (ADC), a flexible digital filter, a 2.5 V reference and reference buffer, and high speed serial and parallel interfaces. The AD7606/AD7606-6/AD7606-4 operate from a single 5 V supply and can accommodate ±10 V and ±5 V true bipolar input signals while sampling at throughput rates up to 200 kSPS for all channels. The input clamp protection circuitry can tolerate voltages up to ±16.5 V . The AD7606 has 1 MΩ analog input impedance regardless of sampling frequency. The single supply operation, on-chip filtering, and high input impedance eliminate the need for driver op amps and external bipolar supplies. The AD7606/AD7606-6/AD7606-4 antialiasing filter has a 3 dB cutoff frequency of 22 kHz and provides 40 dB antialias rejection when sampling at 200 kSPS. The flexible digital filter is pin driven, yields improvements in SNR, and reduces the 3 dB bandwidth. 1 Patent pending.

Rev. 0 | Page 4 of 36 SPECIFICATIONS Table 2. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE fIN = 1 kHz sine wave unless otherwise noted Signal-to-Noise Ratio (SNR)2, 3 Oversampling by 16; ±10 V range; fIN = 130 Hz 94 95.5 dB Oversampling by 16; ±5 V range; fIN = 130 Hz 93 94.5 dB No oversampling; ±10 V Range 88.5 90 dB No oversampling; ±5 V range 87.5 89 dB Signal-to-(Noise + Distortion) (SINAD)2 No oversampling; ±10 V range 88 90 dB No oversampling; ±5 V range 87 89 dB Dynamic Range No oversampling; ±10 V range 90.5 dB No oversampling; ±5 V range 90 dB Total Harmonic Distortion (THD)2 −107 −95 dB Peak Harmonic or Spurious Noise (SFDR)2 −108 dB Intermodulation Distortion (IMD)2 fa = 1 kHz, fb = 1.1 kHz Second-Order Terms −110 dB Third-Order Terms −106 dB Channel-to-Channel Isolation2 fIN on unselected channels up to 160 kHz −95 dB ANALOG INPUT FILTER Full Power Bandwidth −3 dB, ±10 V range 23 kHz −3 dB, ±5 V range 15 kHz −0.1 dB, ±10 V range 10 kHz −0.1 dB, ±5 V range 5 kHz tGROUP DELAY ±10 V Range 11 μs ±5 V Range 15 μs DC ACCURACY Resolution No missing codes 16 Bits Differential Nonlinearity2 ±0.5 ±0.99 LSB4 Integral Nonlinearity2 ±0.5 ±2 LSB Total Unadjusted Error (TUE) ±10 V range ±6 LSB ±5 V range ±12 LSB Positive Full-Scale Error2, 5 External reference ±8 ±32 LSB Internal reference ±8 LSB Positive Full-Scale Error Drift External reference ±2 ppm/°C Internal reference ±7 ppm/°C Positive Full-Scale Error Matching2 ±10 V range 5 32 LSB ±5 V range 16 40 LSB Bipolar Zero Code Error2, 6 ±10 V range ±1 ±6 LSB ± 5 V range ±3 ±12 LSB Bipolar Zero Code Error Drift ±10 V range 10 μV/°C ± 5 V range 5 μV/°C Bipolar Zero Code Error Matching2 ±10 V range 1 8 LSB ±5 V range 6 22 LSB Negative Full-Scale Error2, 5 External reference ±8 ±32 LSB Internal reference ±8 LSB Negative Full-Scale Error Drift External reference ±4 ppm/°C Internal reference ±8 ppm/°C Negative Full-Scale Error Matching2 ±10 V range 5 32 LSB ±5 V range 16 40 LSB

Rev. 0 | Page 5 of 36 Parameter Test Conditions/Comments Min Typ Max Unit ANALOG INPUT Input Voltage Ranges RANGE = 1 ±10 V RANGE = 0 ±5 V Analog Input Current 10 V; see Figure 31 5.4 μA 5 V; see Figure 31 2.5 μA Input Capacitance7 5 pF Input Impedance See the Analog Input section 1 MΩ REFERENCE INPUT/OUTPUT Reference Input Voltage Range See the ADC Transfer Function section 2.475 2.5 2.525 V DC Leakage Current ±1 μA Input Capacitance7 REF SELECT = 1 7.5 pF Reference Output Voltage REFIN/REFOUT 2.49/ 2.505 V Reference Temperature Coefficient ±10 ppm/°C LOGIC INPUTS Input High Voltage (VINH) 0.9 × VDRIVE V Input Low Voltage (VINL) 0.1 × VDRIVE V Input Current (IIN) ±2 μA Input Capacitance (CIN)7 5 pF LOGIC OUTPUTS Output High Voltage (VOH) ISOURCE = 100 μA VDRIVE − 0.2 V Output Low Voltage (VOL) I SINK = 100 μA 0.2 V Floating-State Leakage Current ±1 ±20 μA Floating-State Output Capacitance7 5 pF Output Coding Twos complement CONVERSION RATE Conversion Time All eight channels included; see Table 3 4 μs Track-and-Hold Acquisition Time 1 μs Throughput Rate Per channel, all eight channels included 200 kSPS POWER REQUIREMENTS AVCC 4.75 5.25 V VDRIVE 2.3 5.25 V ITOTAL Digital inputs = 0 V or VDRIVE Normal Mode (Static) AD7606 16 22 mA AD7606-6 14 20 mA AD7606-4 12 17 mA Normal Mode (Operational)8 fSAMPLE = 200 kSPS AD7606 20 27 mA AD7606-6 18 24 mA AD7606-4 15 21 mA Standby Mode 5 8 mA Shutdown Mode 2 6 μA

Rev. 0 | Page 6 of 36 Parameter Test Conditions/Comments Min Typ Max Unit Power Dissipation Normal Mode (Static) AD7606 80 115.5 mW Normal Mode (Operational)8 fSAMPLE = 200 kSPS AD7606 100 142 mW AD7606-6 90 126 mW AD7606-4 75 111 mW Standby Mode 25 42 mW Shutdown Mode 10 31.5 μW 1 Temperature range for the B version is −40°C to +85°C. 2 See the Terminology section. 3 This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel mode with VDRIVE = 5 V, SNR typically reduces by 1.5 dB and THD by 3 dB. 5 These specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from the external reference. 6 Bipolar zero code error is calculated with respect to the analog input voltage. 7 Sample tested during initial release to ensure compliance. 8 Operational power/current figure includes contribution when running in oversampling mode.

Rev. 0 | Page 7 of 36 TIMING SPECIFICATIONS Table 3. Limit at TMIN, TMAX Parameter Min Typ Max Unit Description PARALLEL/SERIAL/BYTE MODE tCYCLE 1/throughput rate 5 μs Parallel mode, reading during or after conversion; or serial mode: VDRIVE = 4.75 V to 5.25 V, reading during a conversion using DOUTA and DOUTB lines 5 μs Serial mode reading during conversion; VDRIVE = 3.3 V 9.7 μs Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines tCONV2 Conversion time 3.45 4 4.15 μs Oversampling off; AD7606 3 μs Oversampling off; AD7606-6 2 μs Oversampling off; AD7606-4 7.87 9.1 μs Oversampling by 2; AD7606 16.05 18.8 μs Oversampling by 4; AD7606 33 39 μs Oversampling by 8; AD7606 66 78 μs Oversampling by 16; AD7606 133 158 μs Oversampling by 32; AD7606 257 315 μs Oversampling by 64; AD7606 tWAKE-UP STANDBY 100 μs STBY rising edge to CONVST x rising edge; power-up time from standby mode tWAKE-UP SHUTDOWN Internal Reference 30 ms STBY rising edge to CONVST x rising edge; power-up time from shutdown mode External Reference 13 ms STBY rising edge to CONVST x rising edge; power-up time from shutdown mode tRESET 50 ns RESET high pulse width tOS_SETUP 20 ns BUSY to OS x pin setup time tOS_HOLD 20 ns BUSY to OS x pin hold time t1 40 ns CONVST x high to BUSY high t2 25 ns Minimum CONVST x low pulse t3 25 ns Minimum CONVST x high pulse t4 0 ns BUSY falling edge to CS falling edge setup time t53 0.5 ms Maximum delay allowed between CONVST A, CONVST B rising edges t6 25 ns Maximum time between last CS rising edge and BUSY falling edge t7 25 ns Minimum delay between RESET low to CONVST x high PARALLEL/BYTE READ OPERATION t8 0 ns CS to RD setup time t9 0 ns CS to RD hold time t10 RD low pulse width 16 ns VDRIVE above 4.75 V 21 ns VDRIVE above 3.3 V 25 ns VDRIVE above 2.7 V 32 ns VDRIVE above 2.3 V t11 15 ns RD high pulse width t12 22 ns CS high pulse width (see ); Figure 5 CS and RD linked

Rev. 0 | Page 8 of 36 Limit at TMIN, TMAX Parameter Min Typ Max Unit Description t13 Delay from CS until DB[15:0] three-state disabled 16 ns VDRIVE above 4.75 V 20 ns VDRIVE above 3.3 V 25 ns VDRIVE above 2.7 V 30 ns VDRIVE above 2.3 V t144 Data access time after RD falling edge 16 ns VDRIVE above 4.75 V 21 ns VDRIVE above 3.3 V 25 ns VDRIVE above 2.7 V 32 ns VDRIVE above 2.3 V t15 6 ns Data hold time after RD falling edge t16 6 ns CS to DB[15:0] hold time t17 22 ns Delay from CS rising edge to DB[15:0] three-state enabled SERIAL READ OPERATION fSCLK Frequency of serial read clock 23.5 MHz VDRIVE above 4.75 V 17 MHz VDRIVE above 3.3 V 14.5 MHz VDRIVE above 2.7 V 11.5 MHz VDRIVE above 2.3 V t18 Delay from CS until DOUTA/DOUTB three-state disabled/delay from CS until MSB valid 15 ns VDRIVE above 4.75 V 20 ns VDRIVE above 3.3 V 30 ns VDRIVE = 2.3 V to 2.7 V t194 Data access time after SCLK rising edge 17 ns VDRIVE above 4.75 V 23 ns VDRIVE above 3.3 V 27 ns VDRIVE above 2.7 V 34 ns VDRIVE above 2.3 V t20 0.4 tSCLK ns SCLK low pulse width t21 0.4 tSCLK ns SCLK high pulse width t22 7 SCLK rising edge to DOUTA/DOUTB valid hold time t23 22 ns CS rising edge to DOUTA/DOUTB three-state enabled FRSTDATA OPERATION t24 Delay from CS falling edge until FRSTDATA three-state disabled 15 ns VDRIVE above 4.75 V 20 ns VDRIVE above 3.3 V 25 ns VDRIVE above 2.7 V 30 ns VDRIVE above 2.3 V t25 ns Delay from CS falling edge until FRSTDATA high, serial mode 15 ns VDRIVE above 4.75 V 20 ns VDRIVE above 3.3 V 25 ns VDRIVE above 2.7 V 30 ns VDRIVE above 2.3 V t26 Delay from RD falling edge to FRSTDATA high 16 ns VDRIVE above 4.75 V 20 ns VDRIVE above 3.3 V 25 ns VDRIVE above 2.7 V 30 ns VDRIVE above 2.3 V

TA = 25°C, unless otherwise noted. specifications apply to a 4-layer board. Table 5. Thermal Resistance 1 Transient currents of up to 100 mA do not cause SCR latch-up.

Figure 10. AD7606-4 Pin Configuration Table 6. Pin Function Descriptions should be decoupled to AGND. connect to the AGND plane of a system. mode of operation and Table 9 for oversampling bit decoding.

6 DI PAR/SER/

this pin is logic high and DB15/BYTE SEL is logic high (see Table 8). with DB0 as the LSB of the data transfers. in shutdown mode, all circuitry is powered down.

Rev. 0 | Page 14 of 36 Pin No. Type 1 Mnemonic Description AD7606 AD7606-6 AD7606-4 8 DI RANGE RANGE RANGE Analog Input Range Selection. Logic input. The polarity on this pin deter- mines the input range of the analog input channels. If this pin is tied to a logic high, the analog input range is ±10 V for all channels. If this pin is tied to a logic low, the analog input range is ±5 V for all channels. A logic change on this pin has an immediate effect on the analog input range. Changing this pin during a conversion is not recommended for fast throughput rate applications. See the Analog Input section for more information. 9, 10 DI CONVST A, CONVST B CONVST A, CONVST B CONVST A, CONVST B Conversion Start Input A, Conversion Start Input B. Logic inputs. These logic inputs are used to initiate conversions on the analog input channels. For simultaneous sampling of all input channels, CONVST A and CONVST B can be shorted together, and a single convert start signal can be applied. Alternatively, CONVST A can be used to initiate simultaneous sampling: V1, V2, V3, and V4 for the AD7606; V1, V2, and V3 for the AD7606-6; and V1 and V2 for the AD7606-4. CONVST B can be used to initiate simultaneous sampling on the other analog inputs: V5, V6, V7, and V8 for the AD7606; V4, V5, and V6 for the AD7606-6; and V3 and V4 for the AD7606-4. This is possible only when oversampling is not switched on. When the CONVST A or CONVST B pin transitions from low to high, the front-end track-and-hold circuitry for the respective analog inputs is set to hold. 11 DI RESET RESET RESET Reset Input. When set to logic high, the rising edge of RESET resets the AD7606/AD7606-6/AD7606-4. The part should receive a RESET pulse after power-up. The RESET high pulse should typically be 50 ns wide. If a RESET pulse is applied during a conversion, the conversion is aborted. If a RESET pulse is applied during a read, the contents of the output registers reset to all zeros. 12 DI RD/SCLK RD/SCLK RD/SCLK Parallel Data Read Control Input When the Parallel Interface Is Selected (RD)/ Serial Clock Input When the Serial Interface Is Selected (SCLK). When both CS and RD are logic low in parallel mode, the output bus is enabled. In serial mode, this pin acts as the serial clock input for data transfers. The CS falling edge takes the DOUTA and DOUTB data output lines out of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the DOUTA and DOUTB serial data outputs. For more information, see the section. Conversion Control 13 DI CS CS CS Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic low in parallel mode, the DB[15:0] output bus is enabled and the conversion result is output on the parallel data bus lines. In serial mode, CS is used to frame the serial read transfer and clock out the MSB of the serial output data. 14 DO BUSY BUSY BUSY Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising edges and indicates that the conversion process has started. The BUSY output remains high until the conversion process for all channels is complete. The falling edge of BUSY signals that the conversion data is being latched into the output data registers and is available to read after a Time t 4. Any data read while BUSY is high must be completed before the falling edge of BUSY occurs. Rising edges on CONVST A or CONVST B have no effect while the BUSY signal is high. 15 DO FRSTDATA FRSTDATA FRSTDATA Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back on the parallel, byte, or serial interface. When the CS input is high, the FRSTDATA output pin is in three-state. The falling edge of CS takes FRSTDATA out of three-state. In parallel mode, the falling edge of RD corresponding to the result of V1 then sets the FRSTDATA pin high, indicating that the result from V1 is available on the output data bus. The FRSTDATA output returns to a logic low following the next falling edge of RD. In serial mode, FRSTDATA goes high on the falling edge of CS because this clocks out the MSB of V1 on DOUTA. It returns low on the 16th SCLK falling edge after the CS falling edge. See the section for more details. Conversion Control

Rev. 0 | Page 15 of 36 Pin No. Type 1 Mnemonic Description AD7606 AD7606-6 AD7606-4 22 to 16 DO DB[6:0] DB[6:0] DB[6:0] Parallel Output Data Bits, DB6 to DB0. When PAR/SER/BYTE SEL = 0, these pins act as three-state parallel digital input/output pins. When CS and RD are low, these pins are used to output DB6 to DB0 of the conversion result. When PAR/SER/BYTE SEL = 1, these pins should be tied to AGND. When operating in parallel byte interface mode, DB[7:0] outputs the 16-bit con- version result in two RD operations. DB7 (Pin 24) is the MSB; DB0 is the LSB. 23 P VDRIVE V DRIVE V DRIVE Logic Power Supply Input. The voltage (2.3 V to 5.25 V) supplied at this pin determines the operating voltage of the interface. This pin is nominally at the same supply as the supply of the host interface (that is, DSP and FPGA). 24 DO DB7/DOUTA DB7/D OUTA DB7/D OUTA Parallel Output Data Bit 7 (DB7)/Serial Interface Data Output Pin (DOUTA). When PAR/SER/BYTE SEL = 0, this pins acts as a three-state parallel digital input/output pin. When CS and RD are low, this pin is used to output DB7 of the conversion result. When PAR/SER/BYTE SEL = 1, this pin functions as DOUTA and outputs serial conversion data (see the section for more details). When operating in parallel byte mode, DB7 is the MSB of the byte. Conversion Control 25 DO DB8/DOUTB DB8/D OUTB DB8/D OUTB Parallel Output Data Bit 8 (DB8)/Serial Interface Data Output Pin (DOUTB). When PAR/SER/BYTE SEL = 0, this pin acts as a three-state parallel digital input/output pin. When CS and RD are low, this pin is used to output DB8 of the conversion result. When PAR/SER/BYTE SEL = 1, this pin functions as DOUTB and outputs serial conversion data (see the section for more details). Conversion Control 31 to 27 DO DB[13:9] DB[13:9] DB[13:9] Parallel Output Data Bits, DB13 to DB9. When PAR/SER/BYTE SEL = 0, these pins act as three-state parallel digital input/output pins. When CS and RD are low, these pins are used to output DB13 to DB9 of the conversion result. When PAR /SER/BYTE SEL = 1, these pins should be tied to AGND.

32 DO/DI DB14/

Parallel Output Data Bit 14 (DB14)/High Byte Enable (HBEN). When PAR SER/BYTE SEL = 0, this pin acts as a three-state parallel digital output pin. When CS and RD are low, this pin is used to output DB14 of the conversion result. When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1, the AD7606/ AD7606-6/AD7606-4 operate in parallel byte interface mode. In parallel byte mode, the HBEN pin is used to select whether the most significant byte (MSB) or the least significant byte (LSB) of the conversion result is output first. When HBEN = 1, the MSB is output first, followed by the LSB. When HBEN = 0, the LSB is output first, followed by the MSB.

33 DO/DI DB15/

Parallel Output Data Bit 15 (DB15)/Parallel Byte Mode Select (BYTE SEL). When PAR /SER/BYTE SEL = 0, this pin acts as a three-state parallel digital output pin. When CS and RD are low, this pin is used to output DB15 of the conversion result. When PAR/SER/BYTE SEL = 1, the BYTE SEL pin is used to select between serial interface mode and parallel byte interface mode (see ). When Table 8 PAR /SER/BYTE SEL = 1 and DB15/BYTE SEL = 0, the AD7606 operates in serial interface mode. When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1, the AD7606 operates in parallel byte interface mode. 34 DI REF SELECT REF SELECT REF SELECT Internal/External Reference Selection Input. Logic input. If this pin is set to logic high, the internal reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the REFIN/REFOUT pin. 36, 39 P REGCAP REGCAP REGCAP Decoupling Capacitor Pin for Voltage Output from Internal Regulator. These output pins should be decoupled separately to AGND using a 1 μF capacitor. The voltage on these pins is in the range of 2.5 V to 2.7 V.

42 REF REFIN/

Reference Input (REFIN)/Reference Output (REFOUT). The on-chip reference of 2.5 V is available on this pin for external use if the REF SELECT pin is set to logic high. Alternatively, the internal reference can be disabled by setting the REF SELECT pin to logic low, and an external reference of 2.5 V can be applied to this input (see the Internal/External Reference section). Decoupling is required on this pin for both the internal and external reference options. A 10 μF capacitor should be applied from this pin to ground close to the REFGND pins.

Rev. 0 | Page 16 of 36 Pin No. Type 1 Mnemonic Description AD7606 AD7606-6 AD7606-4 43, 46 REF REFGND REFGND REFGND Reference Ground Pins. These pins should be connected to AGND. 44, 45 REF REFCAPA, REFCAPB REFCAPA, REFCAPB REFCAPA, REFCAPB Reference Buffer Output Force/Sense Pins. These pins must be connected together and decoupled to AGND using a low ESR, 10 μF ceramic capacitor. The voltage on these pins is typically 4.5 V. 49 AI V1 V1 V1 Analog Input. This pin is a single-ended analog input. The analog input range of this channel is determined by the RANGE pin. 50, 52 AI GND V1GND, V2GND V1GND, V2GND V1GND, V2GND Analog Input Ground Pins. These pins correspond to Analog Input Pin V1 and Analog Input Pin V2. All analog input AGND pins should connect to the AGND plane of a system. 51 AI V2 V2 V2 Analog Input. This pin is a single-ended analog input. The analog input range of this channel is determined by the RANGE pin 53 AI/GND V3 V3 AGND Analog Input 3. For the AD7606-4, this is an AGND pin.

54 AI GND/

V3GND V3GND AGND Analog Input Ground Pin. For the AD7606-4, this is an AGND pin. 55 AI/GND V4 AGND AGND Analog Input 4. For the AD7606-6 and the AD7606-4, this is an AGND pin.

56 AI GND/

V4GND AGND AGND Analog Input Ground Pin. For the AD7606-6 and AD7606-4, this is an AGND pin. 57 AI V5 V4 V3 Analog Inputs. These pins are single-ended analog inputs. The analog input range of these channels is determined by the RANGE pin. 58 AI GND V5GND V4GND V3GND Analog Input Ground Pins. All analog input AGND pins should connect to the AGND plane of a system. 59 AI V6 V5 V4 Analog Inputs. These pins are single-ended analog inputs. 60 AI GND V6GND V5GND V4GND Analog Input Ground Pins. All analog input AGND pins should connect to the AGND plane of a system. 61 AI/GND V7 V6 AGND Analog Input Pins. For the AD7606-4, this is an AGND pin.

62 AI GND/

V7GND V6GND AGND Analog Input Ground Pins. For the AD7606-4, this is an AGND pin. 63 AI/GND V8 AGND AGND Analog Input Pin. For the AD7606-4 and AD7606-6, this is an AGND pin.

64 AI GND/

V8GND AGND AGND Analog Input Ground Pin. For the AD7606-4 and AD7606-6, this is an AGND pin. 1 P is power supply, DI is digital input, DO is digital output, REF is reference input/output, AI is analog input, GND is ground.

Figure 11. AD7606 FFT, ±10 V Range Figure 12. AD7606 FFT Plot, ±5 V Range

8192 POINT FFT

Figure 13. FFT Plot Oversampling By 16, ±10 V Range Figure 14. AD7606 Typical INL, ±10 V Range Figure 15. AD7606 Typical DNL, ±10 V Range Figure 16. AD7606 Typical INL, ±5 V Range

Figure 29. Dynamic Range vs. Oversampling Rate

2.4980 REFOUT VOLTAGE (V)

Figure 30. Reference Output Voltage vs. Temperature for Figure 31. Analog Input Current vs. Temperature for Various Supply Voltages Figure 32. Supply Current vs. Oversampling Rate Figure 33. PSRR

Rev. 0 | Page 21 of 36 TERMINOLOGY Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, at ½ LSB below the first code transition; and full scale, at ½ LSB above the last code transition. Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Bipolar Zero Code Error The deviation of the midscale transition (all 1s to all 0s) from the ideal, which is 0 V − ½ LSB. Bipolar Zero Code Error Match The absolute difference in bipolar zero code error between any two input channels. Positive Full-Scale Error The deviation of the actual last code transition from the ideal last code transition (10 V − 1½ LSB (9.99954) and 5 V − 1½ LSB (4.99977)) after bipolar zero code error is adjusted out. The positive full-scale error includes the contribution from the internal reference buffer. Positive Full-Scale Error Match The absolute difference in positive full-scale error between any two input channels. Negative Full-Scale Error The deviation of the first code transition from the ideal first code transition (−10 V + ½ LSB (−9.99984) and −5 V + ½ LSB (−4.99992)) after the bipolar zero code error is adjusted out. The negative full-scale error includes the contribution from the internal reference buffer. Negative Full-Scale Error Match The absolute difference in negative full-scale error between any two input channels. Signal-to-(Noise + Distortion) Ratio The measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f S/2, excluding dc). The ratio depends on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 16-bit converter, the signal-to-(noise + distortion) is 98 dB. Total Harmonic Distortion (THD) The ratio of the rms sum of the harmonics to the fundamental. For the AD7606/AD7606-6/AD7606-4, it is defined as THD (dB) = 20log 6 5 4 3 2 V V V V V V V V V2 2 22 2 2 2 2 8 7+ + + + + + + where: V1 is the rms amplitude of the fundamental. V2 to V9 are the rms amplitudes of the second through ninth harmonics. Peak Harmonic or Spurious Noise The ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is determined by a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3. Intermodulation distortion terms are those for which neither m nor n is equal to 0. For example, the second-order terms include (fa + fb) and (fa − fb), and the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels (dB). Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the converter’s linearity. PSR is the maximum change in full- scale transition point due to a change in power supply voltage from the nominal value. The PSR ratio (PSRR) is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the ADC’s V DD and VSS supplies of Frequency fS. PSRR (dB) = 10 log (Pf/PfS) where: Pf is equal to the power at Frequency f in the ADC output. PfS is equal to the power at Frequency fS coupled onto the AVCC supply. Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between all input channels. It is measured by applying a full-scale sine wave signal, up to 160 kHz, to all unselected input channels and then determining the degree to which the signal attenuates in the selected channel with a 1 kHz sine wave signal applied (see Figure 28).

configurations required to choose the desired power-down mode. the amplifiers and ADC core are powered down. decoupled with a 10 μF ceramic capacitor. hints, see the Layout Guidelines section. Table 7. Power-Down Mode Selection normal mode or in one of the two power-down modes. 1DECOUPLING SHOWN ON THE AVCC PIN APPLIES TO EACH AVCC PIN (PIN 1, PIN 37, PIN 38, PIN 48). DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AVCC PIN 37 AND PIN 38. 2DECOUPLING SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39). Figure 43. AD7606 Typical Connection Diagram

independently and is possible only if oversampling is not in use. all channels are always converted. Figure 44. AD7606 Simultaneous Sampling on Channel Sets While Using Independent CONVST A and CONVST B Signals—Parallel Mode

function, the output result is decimated to 16-bit resolution. is reduced, and the allowed sampling frequency is also reduced. bandwidth is limited to ~6 kHz. Figure 47. AD7606—No Oversampling, Oversampling × 2, and reading of conversion data should not occur on this edge. Figure 48. OS x Pin Timing Table 9. Oversample Bit Decoding

000 No OS 89 90 15 22 200

111 Invalid

Figure 65. 64-Lead Low Profile Quad Flat Package [LQFP] 2 This board can be used as a standalone evaluation board or in conjunction with the CED1Z for evaluation/demonstration purposes. 3 This board allows the PC to control and communicate with all Analog Devices, Inc., evaluation boards ending in the EDZ designator.

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