CE81

CE81 FUJITSU | Alldatasheet

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DS06-20110-5EFUJITSU SEMICONDUCTOR DATA SHEET Copyright©1999-2006 FUJITSU LIMITED All rights reserved Semicustom CMOS Embedded array CE81 Series ■ DESCRIPTION The CE81 series 0.18 µm CMOS embedded array is a line of highly integrated CMOS ASICs featuring high speed and low power consumption. This series incorporates up to 34 million gates which have a gate delay time of 12 ps, resulting in both integration and speed about three times higher than conventional products. In addition, CE81 series can operate at a power-supply vo ltage of down to 1.1 V, substantially reducing power consumption. ■ FEATURES

• Technology : 0.18 µm silicon-gate CMOS, 3- to 5-layer wiring  Supply voltage : + 1.8 V ± 0.15 V (normal) to + 1.1 V ± 0.1 V  Junction temperature range : −40 to +125 °C  Gate delay time : t pd = 12 ps (1.8 V, inverter, F/O = 1)  Gate power consumption : P d = 8 nW/MHz/BC (1.1 V, 2-NAND, F/O = 1)  High-load driving capability : I OL = 2/4/8/12 mA mixable  Output buffer cells with noise reduction circuits  Inputs with on-chip input pull-up/pull-down resistors (33 k Ω typical) and bidirectional buffer cells  Buffer cells dedicated to crystal oscillator  Special interface : P-CML, LVDS, PCI, AGP, USB, SDRAM-I/F, SSTL, and others (including those under development)  IP macros : CPU, DSP, PCI, IEEE1394, USB, IrDA, PLL, ADC, DAC, and others (including those under devel- opment)  Capable of incorporating compiled cells (RAM/ROM/multiplier, and others)  Configurable internal bus circuits  Advanced hardware/software co-design environment  Short-term development using a timing driven layout tool  Support for static timing sign-off Dramatically reducing the time for generating test vectors for timing verification and the simulation time (Continued)

(Continued)  Hierarchical design environment for supporting large-scale circuits  Simulation (before layout) considering the input slew ra te and detailed RC delay calculation (after layout) , supporting development with minimized timing trouble after trial manufacture  Support for memory (RAM/ROM) SCAN  Support for memory (RAM) BIST  Support for boundary SCAN  Support for path delay test  A variety of package options (TQFP, HQFP, EBGA, FBGA, TAB-BGA, LQFP) ■ MACRO LIBRARY (Including macros being prepared) 1. Logic cells (about 800 types) 2. IP macros 3. Special I/O interface macros  Adder  Decoder A N D - O R I n v e r t e r N o n - S C A N F l i p F l o p C l o c k B u f f e r I n v e r t e r L a t c h B u f f e r  NAND  OR-AND Inverter A N D O R N O R S e l e c t o r  SCAN Flip Flop  BUS Driver E N O R E O R A N D - O R O t h e r s CPU/DSP FR, SPARClite, standard CPU (under preparation) Communications DSP, DSP for AV Interface macro PCI, IEEE1394, USB, IrDA, etc. Multimedia processing macros JPEG, MPEG, etc. Mixed signal macros ADC, DAC, OPAMP, etc. Compiled macros RAM, ROM, multiplier, adder, multiplier-accumulator, etc. PLL Analog PLL, digital PLL  T-LVTTL  SSTL  HSTL  P-CML  LVDS  PCI  AGP  USB  IEEE1394

■ CHIP STRUCTURE The chip layout of the CE81 series consists of two major areas : chip peripheral area and basic cell area. The chip peripheral area contains the input/output buffer cells for interfacing with external devices and the associated bonding pads. The basic cell area contains some of input/output buffer cells, the unit cells and the compiled cells.  Chip configuration Bonding pad I/O buffer cell Basic cell area

■ COMPILED CELLS Compiled cells are macro cells which are automatically generated with the bit/word configuration specified. The CE81 series has the following types of compiled cells (N ote that each macro is different in word/bit range depending on the column type) . 1. Clock synchronous single-port RAM (1 address : 1 RW)  High density/Partial write type  High speed type  Large scale partial write type 2. Clock synchronous dual-port RAM (2 addresses : 1 RW, 1 R)  High density/Partial write type 3. Clock synchronous register file (3 addresses : 1 W, 2 R) 4. Clock synchronous register file (4 addresses : 2 W, 2 R) 5. Clock synchronous ROM (1 addresses : 1 R) 6. Clock synchronous delay line memory (2 addresses : 1 W, 1 R) Column type Memory capacity Word range Bit range Unit 4 16 to 72 K 16 to 1 K 1 to 72 Bit 16 64 to 72 K 64 to 4 K 1 to 18 Bit Column type Memory capacity Word range Bit range Unit 8 256 to 144 K 64 to 2 K 4 to 72 Bit Column type Memory capacity Word range Bit range Unit 16 24.5 K to 1179 K 4 to 16 K 6 to 72 Bit Column type Memory capacity Word range Bit range Unit 4 16 to 72 K 16 to 1 K 1 to 72 Bit 16 64 to 72 K 64 to 4 K 1 to 18 Bit Column type Memory capacity Word range Bit range Unit 1 4608 4 to 64 1 to 72 Bit Column type Memory capacity Word range Bit range Unit 1 4608 4 to 64 K 1 to 72 Bit Column type Memory capacity Word range Bit range Unit 16 256 to 512 K 128 to 4 K 2 to 128 Bit Column type Memory capacity Word range Bit range Unit 8 256 to 32 K 32 to 1 K 8 to 32 Bit 16 384 to 32 K 64 to 2 K 6 to 16 Bit 32 512 to 32 K 128 to 4 K 4 to 8 Bit

■ ABSOLUTE MAXIMUM RATINGS *1 : The parameter is based on VSS = 0 V. *2 : Internal gate part in case of signal power supply or dual power supply *3 : I/O part in case 3.3 V I/F or 2.5 V I/F is used by dual power supply *4 : DC current which continues more than 10 ms, or average DC current *5 : In case of using I/O cell for clock input *6 : bps = bit per second *7 : Supply pin current for one VDD/GND pin WARNING: Semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Parameter Symbol Rating Unit Min Max Supply voltage*1 VDD −0.5 +2.5 *2 V +4.0 *3 Input voltage*1 VI −0.5 V Output voltage*1 VO −0.5 V Storage temperature Tst −55 +125 °C Junction temperature T j −40 +125 °C Output current *4 IO ⎯± 4m A Input signal transmitting rate R I ⎯ Clock Input *5 : 200 Normal Input : 100 Mbps *6 Output signal transmitting rate R O ⎯ 100 Mbps * 6 Output load capacitance C O ⎯ 3000/RO pF Continuous time of indefinite input signal tZ ⎯ 10 ms Supply pin current I D ⎯ *7 mA Frame Source type Maximum current [mA] Number of layerStandard source Additional source YS/S, YI/I VDDE, VDDI, VDD, VSS 68 68 4, 5 VDDE 39 39 VDDI, VDD, VSS 68 68 AV DDE, VDDI, VDD, VSS 34 34 ⎯ BV DDE, VDDI, VDD, VSS 43 30 ⎯

■ RECOMMENDED OPERATING CONDITIONS  Single power supply (VDD = + 1.8 V ± 0.15 V)  Dual power supply (VDDE = + 3.3 V ± 0.3 V, VDDI = + 1.8 V ± 0.15 V) (VSS = 0 V) Parameter Symbol Value Unit Min Typ Max Supply voltage (1.8 V supply voltage) V DD 1.65 1.8 1.95 V “H” level input voltage (1.8 V CMOS) V IH VDD × 0.65 ⎯ VDD + 0.3 V “L” level input voltage (1.8 V CMOS) V IL −0.3 ⎯ VDD × 0.35 V Junction temperature T j −40 ⎯+ 125 °C (VSS = 0 V) Parameter Symbol Value Unit Min Typ Max Supply voltage 1.8 V supply voltage V DDI 1.65 1.8 1.95 V 3.3 V supply voltage V DDE 3.0 3.3 3.6 “H” level input voltage

1.8 V CMOS

VDD × 0.65 ⎯ VDDI + 0.3 V 3.3 V CMOS 2.0 ⎯ VDDE + 0.3 “L” level input voltage −0.3 ⎯ VDD × 0.35 V Junction temperature T j −40 ⎯+ 125 °C (VSS = 0 V) Parameter Symbol Value Unit Min Typ Max Supply voltage VDDE 3.0 3.3 3.6 V VDDI 1.0 1.1 1.2 V 1.4 1.5 1.6 V “H” level input voltage 3.3 V CMOS V IH 2.0 ⎯ VDDE + 0.3 V “L” level input voltage 3.3 V CMOS V IL −0.3 ⎯+ 0.8 V Junction temperature T j −40 ⎯+ 125 °C

 Dual power supply (VDDE = + 2.5 V ± 0.2 V, VDDI = + 1.8 V ± 0.15 V) WARNING: The recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. SS = 0 V) Parameter Symbol Value Unit Min Typ Max Supply voltage VDDE 2.3 2.5 2.7 V VDDI 1.65 1.8 1.95 V “H” level input voltage VDDI × 0.65 ⎯ VDDI + 0.3 V 2.5 V CMOS 1.7 ⎯ VDDE + 0.3 V “L” level input voltage −0.3 ⎯ VDDI × 0.35 V 2.5 V CMOS −0.3 ⎯+ 0.7 V Junction temperature T j −40 ⎯+ 125 °C (VSS = 0 V) Parameter Symbol Value Unit Min Typ Max Supply voltage VDDE 2.3 2.5 2.7 V VDDI 1.0 1.1 1.2 V 1.4 1.5 1.6 V “H” level input voltage 2.5 V CMOS V IH 1.7 ⎯ VDDE + 0.3 V “L” level input voltage 2.5 V CMOS V IL −0.3 ⎯+ 0.7 V Junction temperature T j −40 ⎯+ 125 °C

■ ELECTRICAL CHARACTERISTICS 1. DC CHARACTERISTICS

• Static supply current (single power supply/Dual power supply) A frame S frame I frame Note : When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditions are V IH = VDD, VIL = VSS, and Tj = + 25 °C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resister or a crystal oscillator buffer is used. The above values may not be guaranteed when a High-speed cell library is used.  Single power supply : V DD = 1.8 V * : Refer to the table on the previous page “Static supply current (single power supply/Dual power supply) ”. Frame A4 A5 A6 A7 A8 A9 AA AB AC AD AE CATLG Frame SA SB SC SD SE SF SG CATLG F r a m e I 1I 2I 3I 4I 5I 6I 7I 8I 9I A CATLG (VDD = 1.8 V ± 0.15 V, VSS = 0 V, Tj = −40 °C to +125 °C) Parameter Symbol Conditions Value Unit Min Typ Max Supply current I DDS ⎯⎯ ⎯ *m A “H” level output voltage V OH IOH = −100 µAV DD − 0.2 ⎯ VDD V “L” level output voltage V OL IOL = 100 µA0 ⎯ 0.2 V “H” level output V-I characteristics ⎯ VDD = 1.8 V±0.15 V ⎯⎯⎯ ⎯ “L” level output V-I characteristics ⎯ VDD = 1.8 V±0.15 V ⎯⎯⎯ ⎯ Input leakage current I L ⎯⎯ ⎯ ± 5 µA Pull-up/pull-down resistance RP Pull-up VIL = 0 Pull-down VIH = VDD ⎯ 18 ⎯ kΩ

 Dual power supply : VDDE = 3.3 V, VDDI = 1.8 V / 1.5 V / 1.1 V *1 : Refer to the table on the previous page “Static supply current (single power supply/Dual power supply) ”. *2 : Refer to the “• V-I Characteristics” Fig. 1, Fig. 2. Parameter Symbol Conditions Value Unit Min Typ Max Supply current I DDS ⎯⎯ ⎯ *1 mA “H” level output voltage VOH4

3.3 V output

IOH = −100 µA VDDE − 0.2 ⎯ VDDE V VOH2

1.8 V output

IOH = −100 µA VDDI − 0.2 ⎯ VDDI V “L” level output voltage VOL4 IOL = 100 µA 0 ⎯ 0.2 V VOL2 IOL = 100 µA 0 ⎯ 0.2 V “H” level output V-I characteristics ⎯ 3.3 V VDDE = 3.3 V±0.3 V *2 ⎯ 1.8 V VDDI = 1.8 V±0.15 V ⎯⎯ “L” level output V-I characteristics I OL 3.3 V VDDE = 3.3 V±0.3 V *2 ⎯ 1.8 V VDDE = 1.8 V±0.15 V ⎯⎯ Input leakage current I L ⎯⎯ ⎯ ± 5 µA Pull-up/pull-down resistance RP 1.8 V Pull up VIL = 0 Pull down VIH = VDDI ⎯ 18 ⎯ kΩ 3.3 V Pull up VIL = 0 Pull down VIH = VDDE 10 33 80

 Dual power supply : VDDE = 2.5 V, VDDI = 1.8 V / 1.5 V / 1.1 V * : Refer to the table on the previous page “Static supply current (single power supply/Dual power supply) ”. Parameter Symbol Conditions Value Unit Min Typ Max Supply current I DDS ⎯⎯ ⎯ *m A “H” level output voltage VOH3

2.5 V output

IOH = −100 µA VDDE − 0.2 ⎯ VDDE V VOH2 IOH = −100 µA VDDI − 0.2 ⎯ VDDI V “L” level output voltage VOL3 IOL = 100 µA 0 ⎯ 0.2 V VOL2 IOL = 100 µA 0 ⎯ 0.2 V “H” level output V-I characteristics I OH 2.5 V VDDE = 2.5 V±0.2 V ⎯⎯ 1.8 V VDDI = 1.8 V±0.15 V ⎯⎯ “L” level output V-I characteristics I OL 2.5 V VDDE = 2.5 V±0.2 V ⎯⎯ 1.8 V VDDI = 1.8 V±0.15 V ⎯⎯ Input leakage current I L ⎯⎯ ⎯ ± 5 µA Pull-up/pull-down resistance RP 1.8 V Pull up VIL = 0 Pull down VIH = VDDI ⎯ 18 ⎯ kΩ 2.5 V Pull up VIL = 0 Pull down VIH = VDDE ⎯ 25 ⎯

• V-I Characteristics −20 −40 −60 −80 −100 −120 IOH (mA) −4.0 Max Min Typ VOH−VDD (V) 100 IOL (mA) VOL (V) 0.0 Max Min Typ 1.0 2.0 3.0 4.0 −20 −40 −60 −80 −100 −120 −140 −160 IOH (mA) −4.0 Max Min Typ VOH−VDD (V) −3.0 −2.0 −1.0 0.0 160 140 120 100 IOL (mA) VOL (V) 0.0 Max Min Typ 1.0 2.0 3.0 4.0 Min : Process = Slow, Tj = + 125 °C, VDD = 3.6 V Typ : Process = Typical, Tj = + 25 °C, VDD = 3.3 V Max : Process = Fast, Tj = −40 °C, VDD = 3.0 V Fig.1 V-I characteristics (3.3 V normal I/O L, M type) Fig.2 V-I characteristics (3.3 V normal I/O H, V type) Min : Process = Slow, Tj = + 125 °C, VDD = 3.6 V Typ : Process = Typical, Tj = + 25 °C, VDD = 3.3 V Max : Process = Fast, Tj = −40 °C, VDD = 3.0 V

1. AC Characteristics *1 : Delay time = propagation delay time, Enable time, Disable time *2 : “typ” is calculated based on the cell specification. *3 : Measurement conditions. Note : tpd max is calculated according to the maximum junction temperature (Tj) . ■ INPUT/OUTPUT PIN CAPACITANCE Note : Capacitance varies according to the package and the location of the pin. ■ DESIGN METHOD Linking a floor plan tool and a logic synthesis tool enable s automatic circuit optimization using floor plan infor- mation. In addition, also available are CDDM (Clock Driven Design Method) clock tree synthesis tools using floor plan information. Using floor plan information at a pre-layout stage prevents major problems with setup and hold timings which can occur after layout. Using a hierarchical layout method to support larger-scale circuit design considerably shortens the overall design cycle time. DD = 1.8 V ± 0.15 V, VSS = 0 V, Tj = −40 °C to +125 °C) Parameter Symbol Rating Unit Min Typ Max Delay time t pd*1 typ*2 × tmin*3 typ*2 × ttyp*3 typ*2 × tmax*3 ns Measurement condition tmin ttyp tmax (f = 1 MHz, VDD = VI = 0 V, Ta = +25 °C) Parameter Symbol Value Unit Input pin C IN Max 16 pF Output pin C OUT Max 16 pF I/O pin C I/O Max 16 pF

■ PACKAGES The table below lists the package types available and the reference number of gates used. Consult Fujitsu for the combination of each package and the availability.  Number of gates used and package types Note : The packages that can be used depend on the circuit configuration. For details, contact Fujitsu. 304 352 480 560 660 720 T A B B G A 0.80 0.80 1.00 1.00 1.00 1.00 891k 9129k 3609k 2689k 1905k 1254k Package Pin Count Pin Pitch (mm) 112 176 192 240 272 288 F B G A 0.80 0.80 0.80 0.50 0.80 0.75 514k 2697k 1550k 2697k 1098k 722k 208 240 256 304 304 H Q F P 0.50 0.50 0.40 0.50 0.50 1098k 15158k 4712k 3764k 2085k 100 120T Q F P 0.50 0.40 514k 514k 144 176 208 L Q F P 0.50 0.50 0.50 722k 1098k 963k 576 660 672 E B G A 1.27 1.00 1.27 5982k 7952k 12727k 0 2000k 4000k 6000k 8000k 10000k 12000k 14000k 16000k 1 8000k 20000k

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