CE77

CE77 FUJITSU | Alldatasheet

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DS06-20112-2EFUJITSU SEMICONDUCTOR DATA SHEET Copyright©2002-2007 FUJITSU LIMITED All rights reserved Semicustom CMOS Embedded array CE77 Series ■ DESCRIPTION The CE77 series 0.25 µm CMOS embedded array is a line of highly integrated CMOS ASICs featuring high speed and low power consumption at the same time. CE77 series is available in 15 frames with the enhanced lineup of 470 K to 6980 K gates. ■ FEATURES

• Technology : 0.25 µm silicon-gate CMOS, 3- to 4-layer wiring  Supply voltage : +2.5 V ± 0.2 V (normal) to +1.5 V ± 0.1 V  Junction temperature range : −40 °C to +125 °C  Gate delay time : t pd = 33 ps (2.5 V, inverter cell High Speed type, F/O = 1, No load)  Gate power consumption : 0.02 µW/MHz (1.5 V, F/O = 1, No load)  High-load driving capability : I OL = 2 mA/4 mA/8 mA/12 mA mixable  Output buffer cells with noise reduction circuits  Inputs with on-chip input pull-up/pull-down resistors (25 k Ω typical) and bidirectional buffer cells  Buffer cells dedicated to crystal oscillator  Special interface (P-CML, LVDS, T-LVTTL, SSTL, PCI, USB, GTL+, and others including those under development)  IP macros (CPU, PCI, USB, IrDA, PLL, DAC, ADC, and others including those under development)  Capable of incorporating compiled cells (RAM/ROM/FIFO/Delay line, and others.)  Configurable internal bus circuits  Advanced hardware/software co-design environment  Support for static timing sign-off Dramatically reducing the time for generating test vectors for timing verification and the simulation time  Hierarchical design environment for supporting large-scale circuits  Simulation (before layout) considering the input slew ra te and detailed RC delay calculation (after layout) , supporting development with minimized timing trouble after trial manufacture (Continued)

(Continued)  Support for memory (RAM/ROM) SCAN  Support for memory (RAM) BIST  Support for boundary SCAN  Support for path delay test  A variety of package options (SQFP , HQFP , PBGA, LQFP , FBGA under development) ■ MACRO LIBRARY (Including macros being prepared) 1. Logic cells (about 700 types) 2. IP macros 3. Special I/O interface macros A d d e r A N D - O R  AND-OR Inverter  Decoder  Clock Buffer  Non-SCAN Flip Flop L a t c h I n v e r t e r N A N D B u f f e r A N D O R - A N D I n v e r t e r N O R O R  SCAN Flip Flop  Selector  BUS Driver  ENOR  EOR  Boundary Scan Register  Others CPU SPARClite, ARM7 Interface macro USB, IrDA, etc. Multimedia processing macros JPEG, etc. Mixed signal macros ADC, DAC, Analog switch, etc. Compiled macros RAM, RO M, FIFO, Delay Line, PLL Analog PLL P - C M L U S B

■ CHIP STRUCTURE The chip layout of the CE77 series consists of two major areas : chip peripheral area and basic cell area. The chip peripheral area contains the input/output buffer cells for interfacing with external devices and the associated bonding pads. The basic cell area contains some of input/output buffer cells, the unit cells and the compiled cells.  Chip configuration Bonding pad I/O buffer cell Basic cell area

■ COMPILED CELLS Compiled cells are macro cells which are automatically generated with the bit/word configuration specified. The CE77 series has the following types of compiled cells (Note that each macro is different in word/bit range depending on the column type) . 1. Clock synchronous single-port RAM (1 address, 1 RW) (High density type) / (Partial write type) (Ultra high density type) (Low power consumption type) (High speed type) 2. Clock synchronous dual-port RAM (2 addresses, 1 RW/1 R) 3. Clock synchronous register file (3 addresses, 1W/2R) 4. Clock synchronous register file (4 addresses, 2W/2R) Column type Memory capacity Word range Bit range Unit 4 16 to 72 K 16 to 1 K 1 to 72 bit 16 64 to 72 K 64 to 4 K 1 to 18 bit Column type Memory capacity Word range Bit range Unit 4 64 to 72 K 32 to 1 K 2 to 72 bit 4 2064 to 512 K 1032 to 4 K 2 to 128 bit 16 4160 to 512 K 2080 to 16 K 2 to 32 bit Column type Memory capacity Word range Bit range Unit 4 128 to 72 K 32 to 1 K 4 to 72 bit 8 256 to 72 K 64 to 2 K 4 to 36 bit Column type Memory capacity Word range Bit range Unit 8 128 to 144 K 32 to 2 K 4 to 72 bit Column type Memory capacity Word range Bit range Unit 4 16 to 72 K 16 to 1 K 1 to 72 bit 16 64 to 72 K 64 to 4 K 1 to 18 bit Column type Memory capacity Word range Bit range Unit 1 4608 4 to 64 1 to 72 bit Column type Memory capacity Word range Bit range Unit 1 4608 4 to 64 1 to 72 bit

1. Clock synchronous ROM (1 address, 1R) 6. Clock synchronous delay line memory (2 addresses, 1W/1R) 7. Clock synchronous FIFO memory (2 addresses, 1W/1R) Column type Memory capacity Word range Bit range Unit 8 128 to 512 K 32 to 4 K 4 to 128 bit 16 128 to 512 K 64 to 8 K 2 to 64 bit Column type Memory capacity Word range Bit range Unit 8 512 to 32 K 32 to 1 K 16 to 32 bit 16 512 to 32 K 64 to 2 K 8 to 16 bit 32 512 to 32 K 128 to 4 K 4 to 8 bit Column type Memory capacity Word range Bit range Unit 8 512 to 32 K 32 to 1 K 16 to 32 bit 16 512 to 32 K 64 to 2 K 8 to 16 bit 32 512 to 32 K 128 to 4 K 4 to 8 bit

■ ABSOLUTE MAXIMUM RATINGS *1 : VSS = 0 V *2 : Maximum output current which can be supplied constantly. *3 : Maximum supply current which can be supplied constantly. *4 : Internal gate part in case of single power supply or dual power supply. *5 : I/O part in case 3.3 V I/F or 2.5 V I/F is used by dual power supply. WARNING: Semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Parameter Symbol Application Rating Unit Min Max Power supply voltage*1 VDD VDD = 1.4 V to 2.7 V − 0.5 +3.0*4 V VDD = 2.7 V to 3.6 V +4.0*5 Input voltage *1 VI ⎯ − 0.5 V Output voltage*1 VO ⎯ − 0.5 V Storage temperature Tst ⎯− 55 +125 °C Junction temperature Tj ⎯− 40 +125 °C Output current*2 L type IO Powerless type (IOL = 2 mA) ⎯± 13 mA M type Normal type (IOL = 4 mA) ⎯± 13 H type Power type (IOL = 8 mA) ⎯± 13 V type High power type (IOL = 12 mA) ⎯± 26 Power-supply pin current *3 ID Per VDD, GND pin ⎯ 60 mA

■ RECOMMENDED OPERATING CONDITIONS 1. Single power supply

• Conditions: VDD = 2.5 V±0.2 V, VSS = 0 V
• Conditions: VDD = 1.8 V±0.15 V, VSS = 0 V
• Conditions: VDD = 1.5 V±0.1 V, VSS = 0 V Parameter Symbol Value Unit Min Typ Max Power supply voltage V DD 2.3 2.5 2.7 V “H” level input voltage CMOS normal VIH 1.7 ⎯ VDD + 0.3 V CMOS schmitt V DD × 0.8 “L” level input voltage CMOS normal VIL −0.3 ⎯ +0.7 V CMOS schmitt V DD × 0.2 Junction temperature T j −40 ⎯+ 125 °C Parameter Symbol Value Unit Min Typ Max Power supply voltage V DDI 1.65 1.8 1.95 V “H” level input voltage CMOS normal VIH VDD × 0.65 ⎯ VDD + 0.3 V CMOS schmitt V DD × 0.8 “L” level input voltage CMOS normal VIL −0.3 ⎯ VDD × 0.35 V CMOS schmitt V DD × 0.2 Junction temperature T j −40 ⎯+ 125 °C Parameter Symbol Value Unit Min Typ Max Power supply voltage V DDI 1.4 1.5 1.6 V “H” level input voltage CMOS normal VIH VDD × 0.7 ⎯ VDD + 0.3 V CMOS schmitt V DD × 0.8 “L” level input voltage CMOS normal VIL −0.3 ⎯ VDD × 0.3 V CMOS schmitt V DD × 0.2 Junction temperature T j −40 ⎯+ 125 °C

1. Dual power supply Parameter Symbol Value Unit Min Typ Max Power supply voltage VDDE 3.0 3.3 3.6 V VDDI 1.4 ⎯ 2.7 “H” level input voltage

1.5 V CMOS normal

VDDI × 0.7 VDDI + 0.3 V 1.8 V CMOS normal V DDI × 0.65 2.5 V CMOS normal 1.7 3.3 V CMOS normal 2.0 V DDE + 0.3

1.5 V CMOS schmitt

VDDI × 0.8 V DDI + 0.31.8 V CMOS schmitt

2.5 V CMOS schmitt

3.3 V CMOS schmitt V DDE × 0.8 V DDE + 0.3 5 V Tolerant 2.0 5.5 “L” level input voltage VIL −0.3 ⎯ VDDI × 0.3 V 1.8 V CMOS normal V DDI × 0.35 2.5 V CMOS normal + 0.7 3.3 V CMOS normal + 0.8 VDDI × 0.21.8 V CMOS schmitt

3.3 V CMOS schmitt V

DDE × 0.2 5 V Tolerant + 0.8 Junction temperature T j −40 ⎯+ 125 °C

WARNING: The recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Parameter Symbol Value Unit Min Typ Max Power supply voltage V DDE 2.3 2.5 2.7 V VDDI 1.4 ⎯ 1.95 “H” level input voltage VDDI × 0.7 VDDI + 0.3 V 1.8 V CMOS normal V DDI × 0.65 2.5 V CMOS normal 1.7 V DDE + 0.3 VDDI × 0.8 V DDI + 0.3

1.8 V CMOS schmitt

2.5 V CMOS schmitt V DDE × 0.8 V DDE + 0.3 “L” level input voltage VIL −0.3 ⎯ VDDI × 0.3 V 1.8 V CMOS normal V DDI × 0.35 2.5 V CMOS normal 0.7 V DDI × 0.2 2.5 V CMOS schmitt V DDE × 0.2 Junction temperature T j −40 ⎯+ 125 °C

■ DC CHARACTERISTICS  Single power supply : VDD = 2.5 V (Standard) *1 : When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditions are VIH = VDD, VIL = VSS, and Tj = +25 °C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used. *2 : Refer to “(2) 2.5 V” in ■ V-I CHARACTERISTICS. (VDD = 2.5 V ± 0.2 V, VSS = 0 V, Tj = −40 °C to +125 °C) Parameter Symbol Conditions Value Unit Min Typ Max Power supply current*1 IDDS T2 ⎯⎯ 0.1 mA T3, T4 ⎯⎯ 0.2 T5 to T7 ⎯⎯ 0.3 T8, T9 ⎯⎯ 0.4 TA ⎯⎯ 0.5 TB, TC ⎯⎯ 0.6 TD ⎯⎯ 0.8 TE ⎯⎯ 1.0 TF ⎯⎯ 1.1 TG ⎯⎯ 1.3 “H” level output voltage V OH IOH = −100 µAV DD − 0.2 ⎯ VDD V “L” level output voltage V OL IOL = 100 µA0 ⎯ 0.2 V “H” level output voltage V-I characteristics ⎯ 2.5 V VDD = 2.5 V±0.2 V *2 ⎯⎯ ⎯ “L” level output current V-I characteristics ⎯ 2.5 V VDD = 2.5 V±0.2 V *2 ⎯⎯ ⎯ Input leakage current I L ⎯⎯ ⎯ ± 5 µA Pull-up/pull-down resistance RP Pull-up VIL = 0 V Pull-down VIH = VDD 10 25 120 k Ω

 Single power supply : VDD = 1.8 V *1 : When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditions are VIH = VDD, VIL = VSS, and Tj = +25 °C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used. *2 : Refer to “(3) 1.8 V” in ■ V-I CHARACTERISTICS. (VDD = 1.8 V ± 0.15 V, VSS = 0 V, Tj = −40 °C to +125 °C) Parameter Symbol Conditions Value Unit Min Typ Max Power supply current*1 IDDS T2 ⎯⎯ 0.1 mA T3, T4 ⎯⎯ 0.2 T5 to T7 ⎯⎯ 0.3 T8, T9 ⎯⎯ 0.4 TA ⎯⎯ 0.5 TB, TC ⎯⎯ 0.6 TD ⎯⎯ 0.8 TE ⎯⎯ 1.0 TF ⎯⎯ 1.1 TG ⎯⎯ 1.3 “H” level output voltage V OH IOH = −100 µAV DD − 0.2 ⎯ VDD V “L” level output voltage V OL IOL = 100 µA0 ⎯ 0.2 V “H” level output voltage V-I characteristics ⎯ 1.8 V VDD = 1.8 V±0.15 V *2 ⎯⎯ ⎯ “L” level output current V-I characteristics ⎯ 1.8 V VDD = 1.8 V±0.15 V *2 ⎯⎯ ⎯ Input leakage current I L ⎯⎯ ⎯ ± 5 µA Pull-up/pull-down resistance RP Pull-up VIL = 0 V Pull-down VIH = VDD 10 40 120 k Ω

 Single power supply : VDD = 1.5 V *1 : When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditions are VIH = VDD, VIL = VSS, and Tj = +25 °C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used. *2 : Refer to “(4) 1.5 V” in ■ V-I CHARACTERISTICS. (VDD = 1.5 V ± 0.1 V, VSS = 0 V, Tj = −40 °C to +125 °C) Parameter Symbol Conditions Value Unit Min Typ Max Power supply current*1 IDDS T2 ⎯⎯ 0.1 mA T3, T4 ⎯⎯ 0.2 T5 to T7 ⎯⎯ 0.3 T8, T9 ⎯⎯ 0.4 TA ⎯⎯ 0.5 TB, TC ⎯⎯ 0.6 TD ⎯⎯ 0.8 TE ⎯⎯ 1.0 TF ⎯⎯ 1.1 TG ⎯⎯ 1.3 “H” level output voltage V OH IOH = −100 µAV DD − 0.2 ⎯ VDD V “L” level output voltage V OL IOL = 100 µA0 ⎯ 0.2 V “H” level output voltage V-I characteristics ⎯ 1.5 V VDD = 1.5 V±0.1 V *2 ⎯⎯ ⎯ “L” level output current V-I characteristics ⎯ 1.5 V VDD = 1.5 V±0.1 V *2 ⎯⎯ ⎯ Input leakage current I L ⎯⎯ ⎯ ± 5 µA Pull-up/pull-down resistance RP Pull-up VIL = 0 V Pull-down VIH = VDD 10 55 120 k Ω

 Dual power supply : VDDE = 3.3 V/VDDI = 2.5 V, 1.8 V, 1.5 V *1: When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditions are VIH = VDD, VIL = VSS, and Tj = +25 °C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used. *2: Refer to “(1) 3.3 V” in ■ V-I CHARACTERISTICS. *3: Refer to “(2) 2.5 V” in ■ V-I CHARACTERISTICS. *4: Refer to “(3) 1.8 V” in ■ V-I CHARACTERISTICS“. *5: Refer to “(4) 1.5 V” in ■ V-I CHARACTERISTICS. Parameter Symbol Conditions Value UnitMin Typ Max Power supply current*1 IDDS T2 ⎯⎯ 0.1 mA T3, T4 ⎯⎯ 0.2 T5 to T7 ⎯⎯ 0.3 T8, T9 ⎯⎯ 0.4 TA ⎯⎯ 0.5 TB, TC ⎯⎯ 0.6 TD ⎯⎯ 0.8 TE ⎯⎯ 1.0 TF ⎯⎯ 1.1 TG ⎯⎯ 1.3 “H” level output voltage VOH4 3.3 V output IOH = −100 µAV DDE − 0.2 ⎯ VDDE VVOH3 2.5 V output IOH = −100 µAV DDI − 0.2 ⎯ VDDI VOH2 1.8 V output IOH = −100 µAV DDI − 0.2 ⎯ VDDI VOH1 1.5 V output IOH = −100 µAV DDI − 0.2 ⎯ VDDI “L” level output voltage VOL4 3.3 V output IOL = 100 µA0 ⎯ 0.2 VVOL3 2.5 V output IOL = 100 µA0 ⎯ 0.2 VOL2 1.8 V output IOL = 100 µA0 ⎯ 0.2 VOL1 1.5 V output IOL = 100 µA0 ⎯ 0.2 “H” level output V-I characteristics “L” level output V-I characteristics Input leakage current I L ⎯⎯ ⎯ ± 5 µA Pull-up/pull-down resistance RP

3.3 V Pull-up VIL = 0

Pull-down VIH = VDDE 10 25 70 kΩ

2.5 V Pull-up VIL = 0

Pull-down VIH = VDDI 10 25 120

1.8 V Pull-up VIL = 0

Pull-down VIH = VDDI 10 40 120

1.5 V Pull-up VIL = 0

Pull-down VIH = VDDI 10 55 120

 Dual power supply : VDDE = 2.5 V/VDDI = 2.5 V, 1.8 V, 1.5 V *1: When the memory is in a standby mode and analog macro is in a power-down mode. At both cases, conditions are VIH = VDD, VIL = VSS, and Tj = +25 °C. The above values may not be guaranteed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used. *2: Refer to “(2) 2.5 V” in ■ V-I CHARACTERISTICS. *3: Refer to “(3) 1.8 V” in ■ V-I CHARACTERISTICS“. *4: Refer to “(4) 1.5 V” in ■ V-I CHARACTERISTICS. Parameter Symbol Conditions Value Unit Min Typ Max Power supply current*1 IDDS T2 ⎯⎯ 0.1 mA T3, T4 ⎯⎯ 0.2 T5 to T7 ⎯⎯ 0.3 T8, T9 ⎯⎯ 0.4 TA ⎯⎯ 0.5 TB, TC ⎯⎯ 0.6 TD ⎯⎯ 0.8 TE ⎯⎯ 1.0 TF ⎯⎯ 1.1 TG ⎯⎯ 1.3 “H” level output voltage VOH3 2.5 V output IOH = −100 µAV DDE − 0.2 ⎯ VDDE VVOH2 1.8 V output IOH = −100 µAV DDI − 0.2 ⎯ VDDI VOH1 1.5 V output IOH = −100 µAV DDI − 0.2 ⎯ VDDI “L” level output voltage VOL3 2.5 V output IOL = 100 µA0 ⎯ 0.2 VVOL2 1.8 V output IOL = 100 µA0 ⎯ 0.2 VOL1 1.5 V output IOL = 100 µA0 ⎯ 0.2 “H” level output V-I characteristics “L” level output V-I characteristics Input leakage current I L ⎯⎯ ⎯ ± 5 µA Pull-up/pull-down resistance RP Pull-down VIH = VDDE 10 25 120 kΩ1.8 V Pull-up VIL = 0 Pull-down VIH = VDDI 10 40 120 Pull-down VIH = VDDI 10 55 120

■ V-I CHARACTERISTICS (1) 3.3 V  3.3 V normal I/O V-I characteristics [ Condition : V DD = 3.0 V ]  3.3 V normal I/O V-I characteristics [ Condition : V DD = 3.3 V ]  3.3 V normal I/O V-I characteristics [ Condition : V DD = 3.6 V ] 0.0 −10.0 −20.0 −30.0 −40.0 −50.0 0.0 1.0 2.0 VOH (V) 3.0 40.0 30.0 20.0 10.0 0.0 0.0 1.0 2.0 VOL (V) 3.0 “H” level output V-I characteristics (VDD = 3.0 V) 3.0 V normal I/O VOH-IOH (Min) <VDD = 3.0 V> “L” level output V-I characteristics (VDD = 3.0 V) 3.0 V normal I/O VOL-IOL (Min) <VDD = 3.0 V> L type M type H type V type L type M type H type V type IOH (Min) (mA) IOL (Min) (mA) 0.0 −10.0 −20.0 −30.0 −40.0 −50.0 0.0 1.0 2.0 VOH (V) 3.0 40.0 30.0 20.0 10.0 0.0 0.0 1.0 2.0 VOL (V) 3.0 “H” level output V-I characteristics (VDD = 3.3 V) 3.3 V normal I/O VOH-IOH (Min) <VDD = 3.3 V> “L” level output V-I characteristics (VDD = 3.3 V) 3.3 V normal I/O VOL-IOL (Min) <VDD = 3.3 V> L type M type H type V type L type M type H type V type IOH (Min) (mA) IOL (Min) (mA) 0.0 −10.0 −20.0 −30.0 −40.0 −50.0 0.0 1.0 2.0 VOH (V) 3.0 40.0 30.0 20.0 10.0 0.0 0.0 1.0 2.0 VOL (V) 3.0 “H” level output V-I characteristics (VDD = 3.6 V) 3.3 V normal I/O VOH-IOH (Min) <VDD = 3.6 V> “L” level output V-I characteristics (VDD = 3.6 V) 3.3 V normal I/O VOL-IOL (Min) <VDD = 3.6 V> L type M typeH type V type L type M type H type V type IOH (Min) (mA) IOL (Min) (mA)

(2) 2.5 V  2.5 V normal I/O V-I characteristics [ Condition : V DD = 2.3 V ]  2.5 V normal I/O V-I characteristics [ Condition : V DD = 2.5 V ]  2.5 V normal I/O V-I characteristics [ Condition : V DD = 2.7 V ] 0.0 −10.0 −20.0 −30.0 0.0 1.0 VOH (V) 2.0 3.0 30.0 20.0 10.0 0.0 0.0 1.0 VOL (V) 2.0 3.0 “H” level output V-I characteristics (VDD = 2.3 V) 2.5 V normal I/O VOH-IOH (Min) <VDD = 2.3 V> “L” level output V-I characteristics (VDD = 2.3 V) 2.5 V normal I/O VOL-IOL (Min) <VDD = 2.3 V> L type M type H type V type IOH (Min) (mA) L type M type H type V type IOL (Min) (mA) 0.0 −10.0 −20.0 −30.0 0.0 1.0 VOH (V) 2.0 3.0 30.0 20.0 10.0 0.0 0.0 1.0 VOL (V) 2.0 3.0 “H” level output V-I characteristics (VDD = 2.5 V) 2.5 V normal I/O VOH-IOH (Min) <VDD = 2.5 V> “L” level output V-I characteristics (VDD = 2.5 V) 2.5 V normal I/O VOL-IOL (Min) <VDD = 2.5 V> L type M type H type V type IOH (Min) (mA) L type M type H type V type IOL (Min) (mA) 0.0 −10.0 −20.0 −30.0 −40.0 0.0 1.0 VOH (V) 2.0 3.0 30.0 20.0 10.0 0.0 0.0 1.0 VOL (V) 2.0 3.0 “H” level output V-I characteristics (VDD = 2.7 V) 2.5 V normal I/O VOH-IOH (Min) <VDD = 2.7 V> “L” level output V-I characteristics (VDD = 2.7 V) 2.5 V normal I/O VOL-IOL (Min) <VDD = 2.7 V> L type M type H type V type IOH (Min) (mA) L type M type H type V type IOL (Min) (mA)

(3) 1.8 V  1.8 V normal I/O V-I characteristics [ Condition : V DD = 1.65 V ]  1.8 V normal I/O V-I characteristics [ Condition : V DD = 1.8 V ]  1.8 V normal I/O V-I characteristics [ Condition : V DD = 1.95 V ] 0.0 −10.0 −20.0 0.0 1.0 VOH (V) 2.0 20.0 10.0 0.0 0.0 1.0 VOL (V) 2.0 “H” level output V-I characteristics (VDD = 1.65 V) 1.8 V normal I/O VOH-IOH (Min) <VDD = 1.65 V> “L” level output V-I characteristics (VDD = 1.65 V) 1.8 V normal I/O VOL-IOL (Min) <VDD = 1.65 V> L type M type H type V type IOH (Min) (mA) L type M type H type V type IOL (Min) (mA) 0.0 −10.0 −20.0 0.0 1.0 VOH (V) 2.0 20.0 10.0 0.0 0.0 1.0 VOL (V) 2.0 “H” level output V-I characteristics (VDD = 1.8 V) 1.8 V normal I/O VOH-IOH (Min) <VDD = 1.8 V> “L” level output V-I characteristics (VDD = 1.8 V) 1.8 V normal I/O VOL-IOL (Min) <VDD = 1.8 V> L type M type H type V type IOH (Min) (mA) L type M type H type V type IOL (Min) (mA) 0.0 −10.0 −20.0 −30.0 0.0 1.0 VOH (V) 2.0 20.0 10.0 0.0 0.0 1.0 VOL (V) 2.0 “H” level output V-I characteristics (VDD = 1.95 V) 1.8 V normal I/O VOH-IOH (Min) <VDD = 1.95 V> “L” level output V-I characteristics (VDD = 1.95 V) 1.8 V normal I/O VOL-IOL (Min) <VDD = 1.95 V> L type M type H type V type IOH (Min) (mA) L type M type H type V type IOL (Min) (mA)

(4) 1.5 V  1.5 V normal I/O V-I characteristics [ Condition : V DD = 1.4 V ]  1.5 V normal I/O V-I characteristics [ Condition : V DD = 1.5 V ]  1.5 V normal I/O V-I characteristics [ Condition : V DD = 1.6 V ] 0.0 −5.0 −10.0 −15.0 0.0 0.5 1.0 VOH (V) 1.5 15.0 10.0 5.0 0.0 0.0 0.5 1.0 VOL (V) 1.5 “H” level output V-I characteristics (VDD = 1.4 V) 1.5 V normal I/O VOH-IOH (Min) <VDD = 1.4 V> “L” level output V-I characteristics (VDD = 1.4 V) 1.5 V normal I/O VOL-IOL (Min) <VDD = 1.4 V> L type M type H type V type IOH (Min) (mA) L type M type H type V type IOL (Min) (mA) 0.0 −5.0 −10.0 −15.0 0.0 0.5 1.0 VOH (V) 1.5 15.0 10.0 5.0 0.0 0.0 0.5 1.0 VOL (V) 1.5 “H” level output V-I characteristics (VDD = 1.5 V) 1.5 V normal I/O VOH-IOH (Min) <VDD = 1.5 V> “L” level output V-I characteristics (VDD = 1.5 V) 1.5 V normal I/O VOL-IOL (Min) <VDD = 1.5 V> L type M type H type V type IOH (Min) (mA) L type M type H type V type IOL (Min) (mA) 0.0 −5.0 −10.0 −15.0 −20.0 0.0 0.5 1.0 VOH (V) 1.5 15.0 10.0 5.0 0.0 0.0 0.5 1.0 VOL (V) 1.5 “H” level output V-I characteristics (VDD = 1.6 V) 1.5 V normal I/O VOH-IOH (Min) <VDD = 1.6 V> “L” level output V-I characteristics (VDD = 1.6 V) 1.5 V normal I/O VOL-IOL (Min) <VDD = 1.6 V> L type M type H type V type IOH (Min) (mA) L type M type H type V type IOL (Min) (mA)

■ AC CHARACTERISTICS *1 : Delay time = propagation delay time, enable time, disable time *2 : “typ” is calculated from the cell specification. *3 : Measurement condition Note : tpd Max is calculated according to the maximum junction temperature (Tj) . ■ INPUT/OUTPUT CAPACITANCE ■ DESIGN METHOD Linking a floor plan tool and a logic synthesis tool enable s automatic circuit optimization using floor plan infor- mation. In addition, CDDM (Clock Driven Design Method) clock tree synthesis tools using floor plan information is also available. Using floor plan information at a pre-layout stage prevents major problems with setup and hold timings which can occur after layout. Using a hierarchical layout method to support larger-scale circuit design considerably shortens the overall design cycle time. DD = 1.8 V ± 0.15 V, VSS = 0 V, Tj = −40 °C to +125 °C) Parameter Symbol Value Unit Min Typ Max Delay time t pd*1 typ*2 × tmin*3 typ*2 × ttyp*3 typ*2 × tmax*3 ns Measurement condition tmin ttyp tmax (f = 1 MHz, VDD = VI = 0 V, Tj = +25 °C) Parameter Symbol Value Unit Input pin C IN Max 16 pF Output pin C OUT Max 16 pF Input/output capacitance C I/O Max 16 pF

■ THE NUMBER OF GATES USED AND PACKAGES 1. Counting the number of the gates used Evaluation of the basic cell count used has revealed some problems including the circuit complexities, difference of the utilization depending on the circuit design scheme (whether it is designed with the logic synthesis) or being unable to achieve the minimum layout with the logically synthesized circuit. To cope with those problems, Fujitsu developed the AREA as a criteria where the circuit size and the layout feasibility is determined. The AREA is a basic cell concei ved from the viewpoint of congestion of the wiring; it has been calculated from the actual basic cell count and pin count in units of BC. Estimate method for the frame include the conventional one by the basic cell count and the one by the AREA for more detailed estimate. Hard macro basic cell count and AREA count for unit cell, I/O buffer cell or compiled cell are listed in the respective cell characteristic table. 2. Packages The table below lists the package types available and the reference number of gates used. Consult Fujitsu for the combination of each package and the availability. CE77 (V-FRAME) Note : The packages that can be used depend on the circuit configuration. For details, contact Fujitsu. 176 208 240 S Q F P 0.5 0.5 0.5 274k 803k 965k 208 240 256 304 H Q F P 0.5 0.5 0.4 0.5 1776k 2276k 1776k 256P B G A 1.27 61 8k 7128k 0k 1000k 2000k 3000k 4000k 5000k 6000k 7000k 8000k~Package Pin Count Pin Pitch (mm)

CE77 (T-FRAME) Note : The packages that can be used depend on the circuit configuration. For details, contact Fujitsu. 144 176 208 256 L Q F P 0.5 0.5 0.5 0.4 1241k 744k 1375k 2109k 208 240 256 304 H Q F P 0.5 0.5 0.4 0.5 2678k 2109k 2109k 4538k 144 176 224 228 F B G A 0.8 0.8 0.8 0.75 461k 646k 1375k 2109k 256 352 420 P B G A 1.27 1.27 1.27 2109k 2678k 3789k 0k 500k 1000k 1500k 2000k 2500k 3000k 3500k 4000k 4500k 5000k 5500kPackage Pin Count Pin Pitch (mm)

■ BASIC CHARACTERISTICS (Continued) 2.0 1.5 1.0 0.5 0.0 VDD = 1.4 V VDD = 1.5 V VDD = 1.6 V VDD = 1.8 V VDD = 1.95 V VIN (V) VOUT (V) VDD = 2.3 V VDD = 2.5 V VDD = 2.7 V 3.0 2.5 2.0 1.5 1.0 0.5 0.0 VIN (V) VOUT (V) 1.25 1.30 1.35 1.40 VIN (V) VOUT (V) VDD = 1.95 V VDD = 1.8 V VDD = 1.6 V VDD = 1.5 V VDD = 1.4 V VDD = 1.4 V VDD = 1.5 V VDD = 1.6 V VDD = 1.8 V VDD =1.95 V 2.0 1.5 1.0 0.5 0.0 3.0 2.5 2.0 1.5 1.0 0.5 0.0 VIN (V) VOUT (V) VDD = 2.7 V VDD = 2.5 V VDD = 2.3 V VDD = 2.3 V VDD = 2.5 V VDD = 2.7 V Transfer characteristics (Typical CMOS input buffer) 1 Transfer characteristics (Typical CMOS input buffer) 2 Transfer characteristics (Typical schmitt input buffer) 1 Transfer characteristics (Typical schmitt input buffer) 2

(Continued) 3.00 2.50 2.00 1.50 1.00 0.50 0.00 −0.50 VDDE = 3.0 V VDDE = 3.3 V VDDE = 3.6 V VIN (V) VOUT (V) 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0.80 1.30 1.80 2.30 VDDE = 3.0 V VDDE = 3.6 V VDDE = 3.3 V VDDE = 3.0 V VDDE = 3.6 V VDDE = 3.3 V VIN (V) VOUT (V) Transfer characteristics (3.3 V normal CMOS input buffer VDDI = 2.5 V) Transfer characteristics (3.3 V normal schmitt input buffer VDDI = 2.5 V)

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