CDS-1402MC-C

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Technical content

Figure 1. CDS-1402 Functional Block Diagram

7 S/H1 ROUT

8 S/H2

22 V OUT

18 A/D CLOCK 1

6 S/H1 OUT

17 A/D CLOCK 1

19 A/D CLOCK 2

20 A/D CLOCK 2

signal and its video signal and subtracting the two. amplifi ers and appropriate support/control circuitry. mum throughput, in a 14-bit application, of 5MHz. be used with most 10 to 14-bit A/D converters.

FEATURES

„Use with 10 to 14-bit A/D converters „5 Megapixels/second minimum throughput (14 bits) „±2.5V input/output ranges, Gain = –1 „Low noise, 200μVrms „Two independent S/H amplifi ers „Gain matching between S/H's „Offset adjustments for each S/H „Four external A/D control lines „Small package, 24-pin ceramic DDIP „Low power, 350mW „Low cost DATEL, Inc. 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com CDS-1402 14-Bit, Very Fast-Settling Correlated Double Sampling Circuit 06 Oct 2015 MDA_CDS-1402.B03 Page 1 of 9

PARAMETERS MIN. TYP . MAX. UNITS Operating Temp. Range, Case CDS-1402MC 0 — +70 °C CDS-1402MM –55 — +125 °C Thermal Impedance θjc — 5 — °C/Watt θca — 22 — °C/Watt Storage Temperature Range –65 — +150 °C Package Type 24-pin, metal-sealed ceramic DDIP Weight 0.42 ounces (12 grams) ABSOLUTE MAXIMUM RATINGS PARAMETERS LIMITS UNITS +5V Analog Supply (Pin 24) 0 to +6.3 Volts –5V Analog Supply (Pin 13) 0 to –6.3 Volts +5V Digital Supply (Pin 16) –0.3 to +6 Volts Digital Inputs (Pins 11, 12) –0.3 to +VDD +0.3 Volts Analog Inputs (Pins 3, 4) ±3.2 Volts Lead Temperature (10 seconds) +300 °C +25°C 0 TO +70°C –55 TO +125°C Input Voltage Range ±2.5 — — ±2.5 — — ±2.5 — — Volts Input Resistance — 500 — — 500 — — 500 — Ohms Input Capacitance — 7 15 — 7 15 — 7 15 pF DIGITAL INPUT Logic Levels Logic Loading "1" — — +10 — — +10 — — +10 μA PERFORMANCE Sample Mode Offset Error - S/H1 — ±3 ±15 — ±4 ±15 — ±5 ±15 mV Pedestal - S/H1 — ±5 ±25 — ±10 ±25 — ±15 ±25 mV Sample Mode Offset Error - S/H2 — ±3 ±15 — ±4 ±15 — ±5 ±15 mV Pedestal - S/H2 — ±5 ±25 — ±10 ±25 — ±15 ±25 mV Sample Mode Offset Error - CDS — ±3 ±15 — ±4 ±15 — ±5 ±15 mV Pedestal - CDS — ±10 ±25 — ±10 ±25 — ±15 ±30 mV Pixel Rate (14-bit settling) ➁ 5 — — 5 — — 5 — — MSPS Input Bandwidth, ±2.5V Small Signal (–20dB input) — 24 — — 24 — — 24 — MHz Large Signal (–0.5dB input) — 8 — — 8 — — 8 — MHz Aperture Delay Time — ±10 — — ±10 — — ±10 — ns Aperture Uncertainty — ±5 — — ±5 — — ±5 — ps rms S/H Acquisition Time ➀ (to ±0.01%, 5V step) — 90 130 — 90 130 — 90 130 ns Hold Mode Settling Time Noise — 200 — — 200 — — 200 — μVrms Feedthrough Rejection — 72 — — 72 — — 72 — dB Overvoltage Recovery Time — 200 — — 200 — — 200 — ns S/H Saturation Voltage — ±3.2 — — ±3.2 — — ±3.2 — V Droop Rate — ±30 ±50 — ±30 ±100 — ±30 ±100 mV/μs ANALOG OUTPUTS ➂ Output Voltage Range ±2.5 — — ±2.5 — — ±2.5 — — Volts Output Impedance — 0.5 — — 0.5 — — 0.5 — Ohms DIGITAL OUTPUTS Logic Levels Logic Loading "0" — — +4 — — +4 — — +4 mA FUNCTIONAL SPECIFICATIONS (TA = +25°C, ±VCC = ±5V, +VDD = +5V, pixel rate = 5MHz, and a minimum warmup time of 2 minutes unless otherwise noted.) DATEL, Inc. 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com CDS-1402 14-Bit, Very Fast-Settling Correlated Double Sampling Circuit 06 Oct 2015 MDA_CDS-1402.B03 Page 2 of 9

Footnotes: ➀ Pins 3 and 4. ➁ See Figure 4 for relationship between input voltage, accuracy, and acquisition time. ➂ Pins 6 and 22. 1. 1. To achieve specifi ed performance, all power supply pins should be bypassed with 2.2μF tantalum capacitors in parallel with 0.1μF ceramic ca- pacitors. All ANALOG GROUND (pins 5, 14, 21 and 23) and DIGITAL GROUND (pin 15) pins should be tied to a large analog ground plane beneath the package. 2. In the CDS confi guration, to avoid saturation of the S/H amplifi ers, the maximum analog inputs and conditions are as follows: ANALOG INPUT 1 < ±3.2V (ANALOG INPUT 1 – ANALOG INPUT 2) < ±3.2V 3. The combined video and reference/offset signal from the CCD array must be applied to S/H2, while the reference/offset signal is applied to S/H1. 4. To use as a CDS circuit, tie pin 8 (S/H2 SUMMING NODE) to either pin 6 (S/H1 OUT), through a 100 Ohm potentiometer, or directly to pin 7 (S/H1 ROUT). In both cases, the CCD's output is tied to pins 3 (ANALOG INPUT 1) and 4 (ANALOG INPUT 2). As shown in Figure 5, the 100Ω potentiometer is for gain matching. 5. To use as a dual S/H, leave pin 7 (S/H1 ROUT) and pin 8 (S/H2 SUMMING NODE) fl oating. Pin 6 (S/H1 OUT) will be the output of S/H1 and pin 22 (V OUT) will be the output of S/H2. 6. See Figure 4 for acquisition time versus accuracy and input voltage step amplitude. INPUT/OUTPUT CONNECTIONS PIN FUNCTION PIN FUNCTION

1 OFFSET ADJUST V1 24 +5V ANALOG SUPPLY

2 DO NOT CONNECT 23 ANALOG GROUND

3 ANALOG INPUT 1 22 V OUT

4 ANALOG INPUT 2 21 ANALOG GROUND

5 ANALOG GROUND 20 A/D CLOCK2

6 S/H1 OUT 19 A/D CLOCK2

7 S/H1 ROUT 18 A/D CLOCK1

8 S/H2 SUMMING NODE 17 A/D CLOCK1

9 OFFSET ADJUST V2 16 +5V DIGITAL SUPPLY

10 DO NOT CONNECT 15 DIGITAL GROUND

11 S/H

1 COMMAND 14 ANALOG GROUND

12 S/H 2 COMMAND 13 –5V ANALOG SUPPLY

+25°C 0 TO +70°C –55 TO +125°C Power Supply Ranges Power Supply Currents +5V Analog Supply — +21 +50 — +21 +50 — +21 +50 mA –5V Analog Supply — –16 –50 — –16 –50 — –16 –50 mA +5V Digital Supply — +2 +5 — +2 +5 — +2 +5 mA Power Dissipation — 350 500 — 350 500 — 350 500 mW Power Supply Rejection — 60 — — 60 — — 60 — dB DATEL, Inc. 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com CDS-1402 14-Bit, Very Fast-Settling Correlated Double Sampling Circuit 06 Oct 2015 MDA_CDS-1402.B03 Page 3 of 9

CORRELATED DOUBLE SAMPLING All photodetector elements (photodiodes, photomultiplier tubes, focal plane arrays, charge coupled devices, etc.) have unique output character- istics that call for specifi c analog-signalprocessing (ASP) functions at their outputs. Charge coupled devices (CCD’s), in particular, display a number of unique characteristics. Among them is the fact that the "offset error" associated with each individual pixel (i.e., the apparent photonic content of that pixel after having had no light incident upon it) changes each and every time that particular pixel is accessed. Most of us think of an offset as a constant parameter that either can be compensated for (by performing an offset adjustment) or can be measured, recorded, and subtracted from subsequent readings to yield more accurate data. Contending with an offset that varies from reading to reading requires measuring and recording (or capturing and storing) the offset each and every time, so it can be subtracted from each subsequent data reading. The "double sampling" aspect of CDS refers to the operation of sampling and storing/recording a given pixel’s offset and then sampling the same pixel’s output an instant later (with both the offset and the video signal present) and subsequently subtracting the two values to yield what is referred to as the "valid video" output for that pixel. The "correlated" in CDS refers to the fact that the two samples must be taken close together in time because the offset is constantly varying. Reasons for this phenomena are discussed below. At the output of all CCD's, transported pixel charge (electrons) is converted to a voltage by depositing the charge onto a capacitor (usually called the output or "fl oating" capacitor). The voltage that develops across this capacitor is obviously proportional to the amount of deposited charge (i.e., the number of electrons) according to DV = DQ/C. Once settled, the resulting capacitor voltage is buffered and brought to the CCD’s output pin as a signal whose amplitude is proportional to the total number of photons incident upon the relevant pixel. After the output signal has been recorded, the fl oating capacitor is discharged ("reset", "clamped", "dumped") and made ready to accept charge from the next pixel. This is when the problems begin. (This is a somewhat oversimplifi ed explanation in that the fl oating capacitor is not usually "discharged" but, in fact, "recharged" to some predetermined dc voltage, usually called the "reference level". The pixel offset appears as an output deviation from that reference level.) The fl oating capacitor is normally discharged (charged) via a shunt switch (typically a FET structure) that has a non-zero "on" resistance. When the switch is on, its effective series resistance exhibits thermal noise (Johnson noise) due to the random motion of thermally energized charge. Because the shunt switch is in parallel with the fl oating capacitor, the instanta- neous value of the thermal noise (expressed in either Volts or electrons) appears across the cap. When the shunt switch is opened, charge/voltage is left on the fl oating cap. The magnitude of this "captured noise voltage" is a function of absolute temperature (T), the value of the fl oating capacitor (C) and Boltzman’s constant (k). It is commonly referred to as "kTC" noise. The second contributor to the constantly varying pixel offsets is the fact that, at high pixel rates, the fl oating capacitor never has time to fully discharge (charge) during the period in which its shunt switch is closed. There is always some "residual" charge left on the cap, and the amount of this charge varies as a function of what was the total charge held during the previous pixel. This amount of residual charge is, in fact, deterministic (if you know the previous charge and the number of time constants in the discharge period), however, it is less of a contributor than "kTC" noise. The third major contributor to pixel offset is the fact that as the shunt FET is turned off, the voltage across (and the charge stored on) its parasitic junction capacitances changes. The result is an "injection" of excess charge onto the fl oating cap causing a voltage step normally called a "pedestal". The fourth major contributor to pixel offset is a low-frequency noise component (usually called 1/f noise or pink noise) associated with the CCD's output buffer amplifi er. Due to all of these contributing factors, "pixel offsets" vary from sample to sample in an inconsistent, unpredictable manner. TRADITIONAL APPROACH TO CDS There are a number of techniques for dealing with the varying-offset idiosyncrasy of CCD's. The most prevalent has been what can be called the "sample-sample-subtract" technique. This approach requires the use of two high-speed sample-hold (S/H) amplifi ers and a difference amplifi er. The fi rst S/H is used to acquire and hold a given pixel's offset. Imme- diately after that, the second S/H acquires and holds the same pixel’s offset+video signal. After both the S/H outputs have fully settled, the difference amplifi er subtracts the offset from the offset+video yielding the valid video signal. CDS-1402 APPROACH (SEE FIGURE 1) The DATEL CDS-1402 takes a slightly different, though clearly superior, approach to CDS. It can be called the “sample-subtract-sample” approach. Note that the CDS-1402 has been confi gured to offer the greatest amount of user fl exibility. Its two S/H circuits function independently. They have separate input and output pins. Each has its own independent control lines. The control-line signals are delayed, buffered, and brought back out of the package so they can be used to control other circuit functions. Each S/H has two pins for offset adjusting (if required), one for current and one for voltage. In normal operation, the output signal of the CCD is applied simultane- ously to the inputs (pins 3 and 4) of both S/H amplifi ers. S/H1 will normally be used to capture and hold each pixel’s offset signal. Therefore, S/H1 is initially in its signal-acquisition mode (logic "1" applied to pin 11, S/ H1 COMMAND). This is also called the sample or track mode. Following a brief interval during which the output of the CCD and the output of S/H1 are allowed to settle, S/H1 is driven into its hold mode by applying a logic "0" to pin 11. S/H1 is now holding the pixel's offset value. In most straightforward confi gurations, the output of S/H1 is connected to the summing node of S/H2 by connecting pin 7 (S/H1 ROUT) to pin 8 (S/H2 SUMMING NODE). When the offset+video signal appears at the output of the CCD, S/H2 is driven into its signal acquisition mode by applying a logic "1" to pin 12 (S/H 2 COMMAND). S/H2 employs a current-summing architecture that subtracts the output of S/H1 (the offset) from the output of the CCD (offset+video) while acquiring only the difference signal (i.e., the valid video). A logic "0" subsequently applied to pin 12 drives S/H2 into its hold mode, and after a brief transient settling time, the valid video signal appears at pin 22 (V OUT). DATEL, Inc. 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com CDS-1402 14-Bit, Very Fast-Settling Correlated Double Sampling Circuit 06 Oct 2015 MDA_CDS-1402.B03 Page 4 of 9

S/H2 into sample (to acquire the offset + video signal). pulse(s) that transfers the next pixel charge onto the output capacitor. the sample mode until just before the reset pulse for the output capacitor. to be as long as that of S/H2. of time has little added benefi t. of the CDS-1402 at the same time the output is settling to its fi nal value. to fully acquire its new input signal.

2 COMMAND), and A/D CLOCK2 (pin 20) is its

bit, 5MHz sampling A/D, the ADS-944. Figure 2. CDS-1402 Typical Timing Diagram

1. Connect pin 8 (S/H2 SUMMING NODE) either directly to pin 7 (S/H1 ROUT)

or through a 100 Ohm potentiometer to pin 6 (S/H1 OUT).

1. Tie pins 3 (ANALOG INPUT 1) and 4 (ANALOG INPUT 2) to pin 5 (ANALOG
2. Adjust OFFSET ADJUST V1 (while S/H1 is in the hold mode) until pin 6 (S/
3. Adjust OFFSET ADJUST V2 (while S/H2 is in the hold mode) until pin 22 (V
4. To negate the effect of output droop on the offset-adjust process, each

mode) until pin 22 (V OUT) is 0V. (open) and tie pin 7 (S/H1 ROUT) to pin 8 (S/H2 SUMMING NODE). Figure 5. CDS-1402 Typical Connection Diagram

MECHANICAL DIMENSIONS INCHES (mm) 24-Pin DDIP Versions 0.200 MAX. (5.080) 0.235 MAX. (5.969) 0.600 ±0.010 (15.240) 0.80 MAX. (20.32) 0.100 TYP. (2.540) 0.100 (2.540) 0.018 ±0.002 (0.457) 0.100 (2.540) 0.040 (1.016) 1.31 MAX. (33.27) 11 2 1324 1.100 (27.940) 0.190 MAX. (4.826) 0.010 (0.254) +0.002 –0.001 SEATING PLANE 0.025 (0.635) Dimension Tolerances (unless otherwise indicated): 2 place decimal (.XX) ±0.010 (±0.254) 3 place decimal (.XXX) ±0.005 (±0.127) Lead Material: Kovar alloy Lead Finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating PIN 1 INDEX 0.80 MAX. (20.32) 0.015 (0.381) MAX. radius for any pin 1.31 MAX. (33.02) 0.100 TYP. (2.540) 0.100 (2.540) 0.210 MAX. (5.334) 0.040 (1.016) 0.020 TYP. (0.508) 0.020 (0.508) 24 13 121 PIN 1 INDEX 0.130 TYP. (3.302) Dimension Tolerances (unless otherwise indicated): 2 place decimal (.XX) ±0.010 (±0.254) 3 place decimal (.XXX) ±0.005 (±0.127) Lead Material: Kovar alloy Lead Finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating 0.060 TYP. (1.524) 0.010 TYP. (0.254) 24-Pin Surface Mount Versions DATEL, Inc. 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com CDS-1402 14-Bit, Very Fast-Settling Correlated Double Sampling Circuit 06 Oct 2015 MDA_CDS-1402.B03 Page 8 of 9

ORDERING INFORMATION

MODEL NUMBER OPERATING TEMP . RANGE PACKAGE TYPE ROHS ACCESSORIES CDS-1402MC 0 to +70°C TDIP NO HS-24 Heat Sink for all CDS-1402 models CDS-1402MM –55 to +125°C TDIP NO CDS-1402MC-C 0 to +70°C TDIP YES CDS-1402MM-C –55 to +125°C TDIP YES Receptacles for pc board mounting can be ordered through Amp Inc., part number 3-331272-8 (component lead socket), 24 required. For MIL-STD-883 products, or availability of surface mount packaging, contact DATEL. © 2015 DATEL, Inc. DATEL, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technica l information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the g ranting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifi cations are subject to change without notice. www.datel.com • e-mail: help@datel.com DATEL is a registered trademark of DATEL, Inc.

11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA

ITAR and ISO 9001/14001 REGISTERED CDS-1402 14-Bit, Very Fast-Settling Correlated Double Sampling Circuit 06 Oct 2015 MDA_CDS-1402.B03 Page 9 of 9