CDS-1401

CDS-1401 MURATA-PS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 8

Technical content

1 OFFSET ADJUST V1

2 OFFSET ADJUST I1

3 ANALOG INPUT 1

4 ANALOG INPUT 2

5 ANALOG GROUND

6 S/H1 OUT

7 S/H1 ROUT

8 S/H2 SUMMING NODE

9 OFFSET ADJUST V2

10 OFFSET ADJUST I2

11 S/H1 COMMAND

12 S/H2 COMMAND

23 ANALOG GROUND

22 V OUT

21 ANALOG GROUND

20 A/D CLOCK2

19 A/D CLOCK2

18 A/D CLOCK1

17 A/D CLOCK1

15 DIGIT AL GROUND

14 ANALOG GROUND

13 –15V ANALOG SUPPL Y

FEATURES

• •••• Use with 10 to 14-bit A/D converters
• •••• 1.25 Megapixels/second minimum throughput (14 bits)
• •••• ±10V input/output ranges, Gain = –1
• •••• Low noise, 200µVrms
• •••• Two independent S/H amplifiers
• •••• Gain matching between S/H's
• •••• Offset adjustments for each S/H
• •••• Four external A/D control lines
• •••• Small package, 24-pin ceramic DDIP GENERAL DESCRIPTION The CDS-1401 is an application-specific, correlated double sampling (CDS) circuit designed for electronic-imaging applications that employ CCD’s (charge coupled devices) as their photodetector. The CDS-1401 has been optimized for use in digital video applications that employ 10 to 14-bit A/D converters. The low-noise CDS-1401 can accurately determine each pixel’s true video signal level by sequentially sampling the pixel’s offset signal and its video signal and subtracting the two. The result is that the consequences of residual charge, charge injection and low-frequency “kTC” noise on the CCD’s output floating capacitor are effectively eliminated. The CDS-1401 can also be used as a dual sample-hold amplifier in a data acquisition system. The CDS-1401 contains two sample-hold amplifiers and appropriate support/control circuitry. Features include independent offset-adjust capability for each S/H, adjustment for matching gain between the two S/H’s, and four control PIN FUNCTION PIN FUNCTION INNOVATION and EX C ELL E N C E ® ®

Figure 1. CDS-1401 Functional Block Diagram

8 S/H2

18 A/D CLOCK 1

17 A/D CLOCK 1

19 A/D CLOCK 2

20 A/D CLOCK 2

® ® PARAMETERS MIN. TYP. MAX. UNITS Operating Temp. Range, Case CDS-1401MC 0 — +70 °C CDS-1401MM –55 — +125 °C Thermal Impedance θjc — 5 — °C/W θca — 22 — °C/W Storage Temperature Range –65 — +150 °C Package Type 24-pin, metal-sealed, ceramic DDIP Weight 0.42 ounces(12 grams) +25°C 0 to +70°C –55 to +125°C Input Voltage Range ±10 — — ±10 — — ±10 — — Volts Input Resistance — 1000 — — 1000 — — 1000 — Ohms Input Capacitance —71 5 —71 5 —71 5 p F DIGITAL INPUTS Logic Levels Logic Loading "1" — — +10 — — +10 — — +10 µA PERFORMANCE Sample Mode Offset Error - S/H1 — ±1 ±10 — ±2 ±10 — ±4 ±10 mV Pedestal - S/H1 — ±15 ±35 — ±15 ±35 — ±15 ±35 mV Sample Mode Offset Error - S/H2 — ±1 ±10 — ±2 ±10 — ±4 ±10 mV Pedestal - S/H2 — ±15 ±35 — ±15 ±35 — ±15 ±35 mV Sample Mode Offset Error - CDS — ±1 ±10 — ±2 ±10 — ±4 ±10 mV Differential Gain Error - CDS — ±0.25 ±1 — ±0.3 ±1 — ±0.35 ±1.5 % Pedestal - CDS — ±15 ±35 — ±15 ±35 — ±15 ±35 mV Pixel Rate (14-bit settling) ➁ 1.25 — — 1.25 — — 1.25 — — MHz Input Bandwidth, ±5V Small Signal (–20dB input) — 7 — — 7 — — 7 — MHz Large Signal (–0.5dB input) — 5 — — 5 — — 5 — MHz Aperture Delay Time —1 0——1 0——1 0—n s Aperture Uncertainty —5— —5— —5— p s r m s S/H Acquisition Time ➁ (to ±0.003%, 10V step) — 340 400 — 350 400 — 350 400 ns Hold Mode Settling Time (to ±0.15mV) — TBD — — TBD — — TBD — ns Noise — 200 — — 200 — — 200 — µVr ms Feedthrough Rejection —7 2——7 2——7 2—d B Overvoltage Recovery Time — 400 — — 400 — — 400 — ns S/H Saturation Voltage — ±12.5 — — ±12.5 — — ±12.5 — Volts Droop Rate — ±0.004 ±0.02 — ±0.4 ±2 — ±0.8 ±4 mV/µs ANALOG OUTPUTS ➂ Output Voltage Range ±10 — — ±10 — — ±10 — — Volts Output Impedance — 0.5 — — 0.5 — — 0.5 — Ohms DIGITAL OUTPUTS Logic Levels Logic Loading "0" — — +4 — — +4 — — +4 mA ABSOLUTE MAXIMUM RATINGS PARAMETERS LIMITS UNITS +15V Supply (Pin 24) 0 to +16 Volts –15V Supply (Pin 13) 0 to –16 Volts +5V Supply (Pin 16) 0 to +6 Volts Digital Inputs (Pins 11, 12) –0.3 to +V DD +0.3 Volts Analog Inputs (Pins 3, 4) ±12 Volts Lead Temp. (10 seconds) 300 °C ➀ Pins 3 and 4. ➁ See Figure 4 for relationship between input voltage, accuracy, and acquisition time. ➂ Pins 6 and 22. FUNCTIONAL SPECIFICATIONS (TA = +25°C, ±Vcc = ±15V , +VDD = +5V, pixel rate = 1.25MHz, and a minimum warmup time of two minutes unless otherwise noted.) PHYSICAL/ENVIRONMENTAL

® ® CDS-1401 +25°C 0 to +70°C –55 to +125°C Power Supply Ranges Power Supply Currents +15V Supply — +23 +27 — +23 +27 — +23 +27 mA Power Dissipation — 700 850 — 700 850 — 700 850 mW Power Supply Rejection — 100 — — 100 — — 100 — dB focal plane arrays, charge coupled devices, etc.) have unique output characteristics that call for specific analog-signal- processing (ASP) functions at their outputs. Charge coupled devices (CCD’s), in particular, display a number of unique characteristics. Among them is the fact that the “offset error” associated with each individual pixel (i.e., the apparent photonic content of that pixel after having had no light incident upon it) changes each and every time that particular pixel is accessed. Most of us think of an offset as a constant parameter that either can be compensated for (by performing an offset adjustment) or can be measured, recorded, and subtracted from subsequent readings to yield more accurate data. Contending with an offset that varies from reading to reading requires measuring and recording (or capturing and storing) the offset each and every time, so it can be subtracted from each subsequent data reading. The “double sampling” aspect of CDS refers to the operation of sampling and storing/recording a given pixel’s offset and then sampling the same pixel’s output an instant later (with both the offset and the video signal present) and subsequently subtracting the two values to yield what is referred to as the “valid video” output for that pixel. The “correlated” in CDS refers to the fact that the two samples must be taken close together in time because the offset is constantly varying. Reasons for this phenomena are discussed below. At the output of all CCD’s, transported pixel charge (electrons) is converted to a voltage by depositing the charge onto a capacitor (usually called the output or “floating” capacitor). The voltage that develops across this capacitor is obviously proportional to the amount of deposited charge (i.e., the number of electrons) according to ΔV = ΔQ/C. Once settled, the resulting capacitor voltage is buffered and brought to the CCD’s output pin as a signal whose amplitude is proportional to the total number of photons incident upon the relevant pixel. After the output signal has been recorded, the floating capacitor is discharged (“reset”, “clamped”, “dumped”) and made ready to accept charge from the next pixel. This is when the problems begin. (This is a somewhat oversimplified FUNCTIONAL DESCRIPTION Correlated Double Sampling All photodetector elements (photodiodes, photomultiplier tubes, GENERAL DESCRIPTION (continued) at the output of the CDS-1401 every 800ns. This correlates with the fact that an acquisition time of 400ns is required for each internal S/H amplifier (10V step setting to ±0.003%). The input and output of the CDS-1401 can swing up to ±10 Volts. The functionally complete CDS-1401 is packaged in a single, 24-pin, ceramic DDIP . It operates from ±15V and +5V supplies and consumes 700mW. Though the CDS-1401’s approach to CDS appears straightforward (see Description of Operation), the circuit actually exploits an elegant architecture whose tradeoffs enable it to offer wide-bandwidth, low-noise and high- throughput combinations unachievable until now. The CDS- 1401 is a generic type of circuit that can be used with almost any 10 to 14-bit A/D converter. However, DATEL does offer A/D converters that are optimized for use with the CDS-1401. TECHNICAL NOTES 1. To achieve specified performance, all power supply pins should be bypassed with 2.2µF tantalum capacitors in parallel with 0.1µF ceramic capacitors. All ANALOG GROUND (pins 5, 14, 21 and 23) and DIGITAL GROUND (pin 15) pins should be tied to a large analog ground plane beneath the package. 2. In the CDS configuration, to avoid saturation of the S/H amplifiers, the maximum analog inputs and conditions are as follows: ANALOG INPUT 1 < ±12V (ANALOG INPUT 1 – ANALOG INPUT 2) < ±12V 3. The combined video and reference/offset signal from the CCD array must be applied to S/H2, while the reference/ offset signal is applied to S/H1. 4. To use as a CDS circuit, tie pin 8 (S/H2 SUMMING NODE) to either pin 6 (S/H1 OUT), through a 200 Ohm potentiometer, or directly to pin 7 (S/H1 ROUT). In both cases, the CCD's output is tied to pins 3 (ANALOG INPUT 1) and 4 (ANALOG INPUT 2). As shown in Figure 5, the 200Ω potentiometer is for gain matching. 5. To use as a dual S/H, leave pin 7 (S/H1 ROUT) and pin 8 (S/H2 SUMMING NODE) floating. Pin 6 (S/H1 OUT) will be the output of S/H1 and pin 22 (V OUT) will be the output of S/H2. 6. See Figure 4 for acquisition time versus accuracy and input voltage step amplitude.

Figure 2. CDS-1401 Typical Timing Diagram switch is opened, charge/voltage is left on the floating cap. of a contributor than kTC noise. causing a voltage step normally called a “pedestal”. associated with the CCD’s output buffer amplifier. sample to sample in an inconsistent, unpredictable manner. what can be called the “sample-sample-subtract” technique. offset+video yielding the valid video signal. independently. They have separate input and output pins.

after the transient from the shunt switch has begun to decay. before the reset pulse for the output capacitor. In Figure 2, S/H's 1 and 2 both have the same acquisition time. package so they can be used to control other circuit functions. current and one for voltage. COMMAND). This is also called the sample or track mode. holding the pixel’s offset value. (S/H1 ROUT) to pin 8 (S/H2 SUMMING NODE). applying a logic “1” to pin 12 (S/H2 COMMAND). settling time, the valid video signal appears at pin 22 (V OUT). Figure 3. CDS-1401 in Front of ADS-CCD1201 at fCLK = 1MHz

1. Connect pin 8 (S/H2 SUMMING NODE) either directly to
2. Tie pins 3 (ANALOG INPUT 1) and 4 (ANALOG INPUT 2)
3. Adjust OFFSET ADJUST V1 or OFFSET ADJUST I1 (while

S/H1 is in the hold mode) until pin 6 (S/H1 OUT) equals 0V .

1. Adjust OFFSET ADJUST V2 or OFFSET ADJUST I2 (while

S/H2 is in the hold mode) until pin 22 (VOUT) equals 0V .

1. To negate the effect of output droop on the offset-adjust

zero immediately after going into the hold mode. when not being used for offset adjustment. Figure 5. CDS-1401 Typical Connection Diagram

® ® MECHANICAL DIMENSIONS INCHES (mm) 24-PIN DDIP 24-PIN SURFACE MOUNT 0.200 MAX. (5.080) 0.235 MAX. (5.969) 0.600 ±0.010 (15.240) 0.80 MAX. (20.32) 0.100 TYP. (2.540) 0.100 (2.540) 0.018 ±0.002 (0.457) 0.100 (2.540) 0.040 (1.016) 1.31 MAX. (33.27) 11 2 1324 1.100 (27.940) 0.190 MAX. (4.826) 0.010 (0.254) +0.002 –0.001 SEATING PLANE 0.025 (0.635) Dimension Tolerances (unless otherwise indicated): 2 place decimal (.XX) ±0.010 (±0.254) 3 place decimal (.XXX) ±0.005 (±0.127) Lead Material: Kovar alloy Lead Finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating 0.80 MAX. (20.32) 0.015 (0.381) MAX. radius for any pin 1.31 MAX. (33.02) 0.100 TYP. (2.540) 0.100 (2.540) 0.210 MAX. (5.334) 0.040 (1.016) 0.020 TYP. (0.508) 0.020 (0.508) 24 13 121 PIN 1 INDEX 0.130 TYP. (3.302) Dimension Tolerances (unless otherwise indicated): 2 place decimal (.XX) ±0.010 (±0.254) 3 place decimal (.XXX) ±0.005 (±0.127) Lead Material: Kovar alloy Lead Finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating 0.060 TYP. (1.524) 0.010 TYP. (0.254) /C174 /C174 INNOV A TION and EX CELLENCE DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 Tel: (508) 339-3000 / Fax: (508) 339-6356 For immediate assistance: (800) 233-2765 DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DA TEL logo is a registered DA TEL, Inc. trademark. DS-0315 10/96 DATEL (UK) LTD. Tadley, England Tel: (01256)-880444 DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 1-34-60-01-01 DATEL GmbH Munchen, Germany Tel: 89-544334-0 DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-354-2025 ISO 9001ISO 9001 /C82/C69/C71/C73/C83/C84/C69/C82/C69/C68 OPERATING ANALOG PACKAGE MODEL TEMP. RANGE INPUT TYPE CSD-1401MC 0 to +70°C ±10V DDIP CDS-1401MM –55 to +125°C ±10V DDIP

ORDERING INFORMATION

HS-24 Heat Sink for CDS-1401 DDIP models Receptacles for pc board mounting can be ordered through Amp Inc., part number 3-331272-8 (component lead socket), 24 required. For MIL-STD-883 products, or availability of surface mount packaging, contact DATEL.