CDP68HC68T1_06 INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- SPI (Serial Peri pheral Interface)
- Full Clock Features - Seconds, Minutes, Hours (12/24, AM/PM), Day of Week, Date, Month, Year (0-99), Automatic Leap Year
- 32 Word x 8-Bit RAM
- Seconds, Minutes, Hours Alarm
- Automatic Power Loss Detection
- Selectable Crystal or 50/60Hz Line Input
- Buffered Clock Output
- Battery Input Pin that Po wers Oscillator and also Connects to V DD Pin When Power Fails
- Three Independent Interrupt Modes -A l a r m - Periodic - Power-Down Sense
- Pb-Free Plus Anneal Available (RoHS Compliant) Pinouts CDP68HC68T1 (PDIP, SOIC) TOP VIEW CDP68HC68T1 (SOIC) TOP VIEW 1CLKOUT CPUR INT SCK MOSI MISO V SS CE VDD XTAL IN VBATT VSYS XTAL OUT LINE POR PSE 1CLK OUT CPUR INT NC SCK MOSI CE MISO VSS PSE VDD XTAL IN NC VBATT XTAL OUT VSYS NC NC LINE POR Data Sheet March 17, 2006
2 FN1547.7 March 17, 2006
Ordering Information
(°C) PACKAGE PKG DWG. # CDP68HC68T1E CDP68HC68T1E -40 to 85 16 Ld PDIP E16.3 CDP68HC68T1EZ (Note) CDP68HC68T1EZ -40 to 85 16 Ld PDIP** (Pb-free) E16.3 CDP68HC68T1M* 68HC68T1M -40 to 85 20 Ld SOIC M20.3 CDP68HC68T1MZ* (Note) 68HC68T1MZ -40 to 85 20 Ld SOIC (Pb-free) M20.3 CDP68HC68T1M2* HC68T1M2 -40 to 85 16 Ld SOIC M16.3 CDP68HC68T1M2Z* (Note) HC68T1M2Z -40 to 85 16 Ld SOIC (Pb-free) M16.3 *Add “96” suffix for taoe and reel. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing. applications. Pin number references throughout this specification refer to the 16 lead PDIP/SOIC. See pinouts for cross reference. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3 FN1547.7 March 17, 2006 Absolute Maximum Ratings Thermal Information Operating Conditions Temperature Range Thermal Resistance (Typical, Note 1) θJA (°C/W) (SOIC, Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing. applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Static Electrical Specifications At TA = -40°C to +85°C, VDD = VBATT = 5V ±5%, except as noted. PARAMETER CONDITIONS CDP68HC68T1 UNITSMIN (NOTE 2) TYP MAX Quiescent Device CurrentIDD -1 1 0 µA Output Voltage High LevelVOH IOH = -1.6mA, VDD = 4.5V 3.7 - - V Output Voltage Low LevelVOL IOL = 1.6mA, VDD = 4.5V - -0 . 4 Output Voltage High LevelVOH IOH ≤ 10µA, VDD = 4.5V 4.4 - - Output Voltage Low LevelVOL IOL ≤ 10µA, VDD = 4.5V - -0 . 1 Input Leakage CurrentIIN -- ±1 µA Three-State Output Leakage CurrentIOUT -- ±10 Operating Current (Note 3) (ID + IB) VDD = VB = 5V Crystal Operation 32kHz - 0.08 0.01 mA 1MHz - 0.5 0.6 2MHz - 0.7 0.84 4MHz - 1 1.2 Pin 14 External Clock (Squarewave) (Note 3) (ID + IB) VDD = VS = 5V 32kHz - 0.02 0.024 1MHz - 0.1 0.12 2MHz - 0.2 0.24 4MHz - 0.4 0.5 Standby Current (Note 3)I B VS = 3V Crystal Operation 32kHz - 20 25 µA 1MHz - 200 250 2MHz - 300 360 4MHz - 500 600 Operating Current (Note 3) V DD = 5V, VB = 3V Crystal Operation ID IB ID IS mA 32kHz - 25 15 30 20 1MHz - 0.08 0.15 0.1 0.18 2MHz - 0.15 0.25 0.18 0.3 4MHz - 0.3 0.4 0.36 0.5
4 FN1547.7 March 17, 2006 Standby Current (Note 3)IB VB = 2.2V Crystal Operation 32kHz - 10 12 µA Input Capacitance CIN VIN = 0, TA = 25°C - - 2 pF Maximum Rise and Fall Timestr, tf (Except XTAL Input and POR Pin 10) -- 2 µs Input Voltage (Line Input Pin Only, Power Sense Mode) 0 10 12 V VSYS > VBVT (For VB Not Internally Connected to VDD) -1 . 0 - V Power-On Reset (POR) Pulse Width 100 75 - ns NOTES: 2. Typical values are for TA = 25°C and nominal VDD. 3. Clock out (Pin 1) disabled, outputs open circuited. No serial access cycles. Static Electrical Specifications At TA = -40°C to +85°C, VDD = VBATT = 5V ±5%, except as noted. (Continued) PARAMETER CONDITIONS CDP68HC68T1 UNITSMIN (NOTE 2) TYP MAX
32 X 8
FIGURE 1. REAL TIME CLOCK FUNCTIONAL DIAGRAM
13 BYTES UNUSED
32 RAM LOCATIONS
FIGURE 2. ADDRESS MAP TABLE 1. CLOCK/CALENDAR AND ALARM DATA MODES
20 Seconds 0-59 00-59 18
21 Minutes 0-59 00-59 49
22 Hours
12 Hour Mode
24 Hour Mode
23 Day of the Week
24 Day of the Month
25 Month
26 Years 0-99 00-99 85
28 Alarm Seconds 0-59 00-59 18
29 Alarm Minutes 0-59 00-59 49
7 FN1547.7 March 17, 2006 Programmers Model - Clock Registers NAMEWRITE/READ REGISTERSHEX ADDRESS TENS 0-5 TENS 0-5 HR X PM/AM TENS 0-2 DB7 XX X X TENS 0-3 TENS 0-1 TENS 0-9 UNITS 0-9 UNITS 0-9 UNITS 0-9 UNITS 1-7 UNITS 0-9 UNITS 0-9 UNITS 0-9 7 6543 210 7 6543 210 WRITE ONLY REGISTERS TENS 0-5 TENS 0-5 UNITS 0-9 UNITS 0-9 UNITS 0-9PM/AM TENS 0-2XX 765 432 1 0 DB0 SECONDS (00-59) MINUTES (00-59) DB7, 1 = 12 HR., 0 = 24 HR. DB = 1 PM, 0 = AM HOURS (01-12 OR 00-23 DATE DAY OF MONTH MONTH (01-12) JAN = 1 DEC = 12 YEARS (00-99) CONTROL INTERRUPT ALARM SECONDS (00-59) ALARM MINUTES (00-59) ALARM HOURS (01-12 OR 00-23) PLUS AM/PM IN 12 HR. MODE PM = 1, AM = 0 READ ONLY REGISTERS STATUS 76 5 4 3 2 1 0 BIT HEX ADDRESS 00-1F RAM DATA BYTE 01-28 NOTE: X = Don’t care writes, X = 0 when read. X DAY OF WK (01-07) SUNDAY = 1 D7 D6 D5 D4 D3 D2 D1 D0
8 FN1547.7 March 17, 2006 Functional Description The SPI real-time clock consists of a clock/calendar and a 32 x 8 RAM. Communications is established via the SPI (Serial Peripheral Interface) bus. In addition to the clock/calendar data from seconds to years, and system flexibility provided by the 32-byte RAM, the clock features computer handshaking with an interrupt output and a separate squarewave clock output that can be one of 7 different frequencies. An alarm circuit is available that compares the alarm latches with the seconds, minutes and hours time counters and activates the interrupt output when they are equal. The clock is specifically designed to aid in power-down/up applications and offers several pins to aid the designer of battery backup systems. Mode Select The voltage level that is present at the VSYS input pin at the end of power-on-reset selects the device to be in the single supply or battery backup mode. Single-Supply Mode If VSYS is a logic high when power-on-reset is completed, CLK OUT, PSE and CPUR will be enabled and the device will be completely operational. CPUR will be placed low if the logic level at the VSYS pin goes low. If the output signals CLK OUT, PSE and CPUR are disabled due to a power- down instruction, VSYS brought to a logic low and then to a logic high will re-enable these outputs. An example of the single-supply mode is where only one supply is available and V DD, VBATT and VSYS are tied together to the supply. Battery Backup Mode If VSYS is a logic low at the end of power-on-reset, CLK OUT, PSE and CPUR will be disabled (CLK OUT, PSE and CPUR low). This condition will be held until VSYS rises to a threshold (about 1.0V) above VBATT. The outputs CLK OUT, PSE and CPUR will then be enabled and the device will be operational. If VSYS falls below a threshold above VBATT the outputs CLK OUT, PSE and CPUR will be disabled. An example of battery backup operation occurs if VSYS is tied to VDD and VDD is not connected to a supply when a battery is connected to the VBATT pin. (See Pin Functions, VBATT for Battery Backup Operation.) Clock/Calendar (See Figures 1 and 2) The clock/calendar portion of this device consists of a long string of counters that is toggled by a 1Hz input. The 1Hz input is generated by a prescaler driven by an on-board oscillator that utilizes one of four possible external crystals or that can be driven by an external clock source. The 1Hz trigger to the counters can also be supplied by a 50Hz or 60Hz input source that is connected to the LINE input pin. The time counters offer seconds, minutes and hours data in 12 hour or 24 hour format. An AM/PM indicator is available that once set, toggles every 12 hours. The calendar counters consist of day (day of week), date (day of month), month and years information. Data in the counters is in BCD format. The hours counter utilizes BCD for hour data plus bits for 12/24 hour and AM/PM. The 7 time counters are accessed serially at addresses 20H through 26H. (See Table 1). RAM The real-time clock also has a static 32 x 8 RAM that is located at addresses 00-1FH. Transmitting the address/control word with bit-5 low selects RAM access. Bits 0 through 4 select the RAM location. Alarm The alarm is set by accessing the three alarm latches and loading the required data. The alarm latches consist of seconds, minutes and hours registers. When their outputs equal the values in the seconds, minutes and hours time counters, an interrupt is generated. The interrupt output will go low if the alarm bit in the Interrupt Control Register is set high. The alarm interrupt bit in the Status Register is set when the interrupt occurs (see Pin Functions, INT Pin). To preclude a false interrupt when loading the time counters, the alarm interrupt bit should be set low in the Interrupt Control Register. This procedure is not required when the alarm time is set. Watchdog Function (See Figure 6) When bit 7 in the Interrupt Control Register is set high, the Clock’s CE (chip enable) pin must be toggled at a regular interval without a serial data transfer. If the CE is not toggled, the clock will supply a CPU reset pulse and bit 6 in the Status Register will be set. Typical service and reset times are listed below. Clock Out The value in the 3 least significant bits of the Clock Control Register selects one of seven possible output frequencies. (See Clock Control Register). This squarewave signal is available at the CLK OUT pin. When Power-Down operation is initiated, the output is set low. Control Registers and Status Registers The operation of the Real-Time Clock is controlled by the Clock Control and Interrupt Control Registers. Both registers are Read-Write Registers. Another register, the Status Register, is available to indicate the operating conditions. The Status Register is a Read only Register. Power Control Power control is composed of two operations, Power Sense and Power Down/Up. Two pins are involved in power sensing, the LINE input pin and the INT output pin. Two additional pins are utilized during power-down/up operation. They are the PSE (Power Supply Enable) output pin and VSYS input pin. 50Hz 60Hz XTAL MIN MAX MIN MAX MIN MAX Service Time - 10ms - 8.3ms - 7.8ms Reset Time 20 40ms 16.7 33.3ms 15.6 31.3ms
to “1”), the clock-output pin will be set low.
- Power-sense operation is selected (B5 = 1 in Interrupt
Control Register) and a power failure occurs.
- A previously set alarm time occurs. The alarm bit in the
- A previously selected periodic interrupt signal activates.
reset the power-down functions. See Serial Peripheral Interface (SPI) section in this data sheet. The negative power-supply pin that is connected to ground.
- V SYS rises above the VBATT voltage after VSYS was
placed low by a system failure.
- A power-on reset (if V SYS is a logic high).
down bit) in the Interrupt Control Register. is reset except for the first ti me up bit (B4), which is set. function enables the line input to sense a power failure. must be low to select XTAL operation. circuit. (The CDP68HC68T1 sets up for a 4MHz oscillator). FIGURE 6. POWER-UP FUNCTI ONAL DIAGRAM (INITIATED
determines the CDP68HC68T1’s operating mode. “XTAL IN” pin can be tied to VSS or VDD. The positive power-supply pin. low, the crystal input will generate the 1Hz time update. selected as the clock output at this time. Register must be read before re-enabling watchdog. and the serial interface will be disabled. “1” to re-enable power sense.
- All frequencies recommended oscill ator circuit. C1, C2 values
- R used for 32KHz operation only. 100K - 300K range as specified
FIGURE 7. OSCILLATOR CIRCUIT
for explanation of alarm delay. periodic output. (See Table 2). NOTE: All bits are reset by power-on reset. TABLE 2. PERIODIC INTERRUPT OUTPUT
0 Disable
98 H zX
13 Minute X X
14 Hour X X
15 Day X X
13 FN1547.7 March 17, 2006 WATCHDOG If this bit is set high, the watchdog circuit has detected a CPU failure. TEST MODE When this bit is set high, the device is in the TEST MODE. FIRST-TIME UP Power-on reset sets this bit high. This signifies that data in the RAM and Clock is not valid and should be initialized. INTERRUPT TRUE A high in this bit signifies that one of the three interrupts (Power Sense, Alarm, and Clock) is valid. POWER-SENSE INTERRUPT This bit set high signifies that the power-sense circuit has generated an interrupt. ALARM INTERRUPT When the seconds, minutes and hours time and alarm counter are equal, this bit will be set high. Status Register must be read before loading Interrupt Control Register for valid alarm indication after alarm activates. CLOCK INTERRUPT A periodic interrupt will set this bit high. All bits are reset by a power-on reset except the “FIRST- TIME UP” which is set. All bits except the power-sense bit are reset after a read of this register. Pin Signal Description SCK (Serial Clock Input, Note 11) This input causes serial data to be latched from the MOSI input and shifted out on the MISO output. MOSI (Master Out/Slave In, Note 11) Data bytes are shifted in at this pin, most significant bit (MSB) first. MISO (Master In/Slave Out) Data bytes are shifted out at this pin, most significant bit (MSB) first. CE (Chip Enable, Note 12) A positive chip-enable input. A low level at this input holds the serial interface logic in a reset state, and disables the output driver at the MISO pin. NOTES: 11. These inputs will retain their previous state if the line driving them goes into a High-Z state. 12. The CE input has as internal pull down device, if the input is in a low state before going to High Z, the input can be left in a High Z. STATUS REGISTER (Read Only) - Address 30H D7 D6 D5 D4 D3 D2 D1 D0
0 WATCHDOG TEST
CE SCK (Note 9) MOSI MISO DISABLE RESET L INPUT DISABLED INPUT DISABLED HIGH Z WRITE H CPOL = 1 CPOL = 0 DATA BIT LATCH HIGH Z READ H CPOL = 1 CPOL = 0 X NEXT DATA BIT SHIFTED OUT (Note 10) NOTES: 9. When interfacing to CDP68HC05 microcontroll ers, serial clock phase bit, CPHA, must be set = 1 in the microcomputer’s Control Register. 10. MISO remains at a high Z until 8-bits of data are ready to be shifted out during a READ. It remains at a high Z during the entire WRITE cycle.
17 FN1547.7 March 17, 2006 Dynamic Electrical Specifications Bus Timing VDD ±10%, VSS = 0VDC, TA = 40°C to 85°C IDENT. NO PARAMETER LIMITS (ALL TYPES) UNITS VDD = 3.3V V DD = 5V MIN MAX MIN MAX
1 Chip Enable Setup Timet EVCV 200 - 100 - ns
2 Chip Enable After Clock Hold Timet CVEX 250 - 125 - ns
3 Clock Width Hight WH 400 - 200 - ns
4 Clock Width Lowt WL 400 - 200 - ns
5 Data In to Clock Setup Timet DVCV 200 - 100 - ns
7 Clock to Data Propagation Delayt CVDV - 200 - 100 ns
8 Chip Disable to Output High Zt EXQZ - 200 - 100 ns
11 Output Rise Timet r - 200 - 100 ns
12 Output Fall Timet f - 200 - 100 ns
A Data in After Clock Hold Timet CVDX 200 - 100 - ns B Clock to Data Out Activet CVQX - 200 - 100 ns C Clock Recovery Timet REC 200 - 200 - ns
FIGURE 14. WRITE-CYCLE TIMING WAVEFORMS FIGURE 15. READ-CYCLE TIMING WAVEFORMS
5 A 5
NOTE: Example of a system in which power is alwa ys on. Clock circuit driven by line input frequency. FIGURE 16. POWER-ON ALWAYS SYSTEM DIAGRAM
always supplies power to the oscillator, keeping voltage frequency variation to a minimum. FIGURE 17. EXTERNALLY CONT ROLLED POWER SYSTEM DIAGRAM
- Set power sense operation by writing bit 5 high in the Interrupt Control Register.
- When an interrupt occurs, the CP U reads the Status Register to determine the interrupt source.
- Sensing a power failure, the CPU does th e necessary housekeeping to prepare for shutdown.
- The CPU reads the Status Register again after several milliseconds to determine validity of power failure.
- The CPU sets power-down bit 6 and disables all interrupts in the Interrupt Control Register when power down is verified.
This causes the CPU reset and clock out to be held low and disconnects the serial interface.
- When power returns and VSYS rises above VBATT, power down is terminated. The CPU reset is released and serial
communication is established.
FIGURE 18. EXAMPLE OF A SYSTEM WITH A BATTERY BACKUP
will enable the CLK OUT pin and set the PSE and CPUR high. alarm activates will disable alarm signal. FIGURE 19. AUTOMOTIVE SYSTEM DIAGRAM
22 FN1547.7 March 17, 2006 Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JE- DEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpendic- ular to datum . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N1 6 1 6 9 Rev. 0 12/93
23 FN1547.7 March 17, 2006 Small Outline Plastic Packages (SOIC) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45° C H 0.25(0.010) BM M α M16.3 (JEDEC MS-013-AA ISSUE C)
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.3977 0.4133 10.10 10.50 3 E 0.2914 0.2992 7.40 7.60 4 e 0.050 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N1 6 1 6 7 α 0° 8° 0° 8° - Rev. 1 6/05
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN1547.7 March 17, 2006 Small Outline Plastic Packages (SOIC) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM B S e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45° C H 0.25(0.010) BM M α M20.3 (JEDEC MS-013-AC ISSUE C)
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.014 0.019 0.35 0.49 9 C 0.0091 0.0125 0.23 0.32 - D 0.4961 0.5118 12.60 13.00 3 E 0.2914 0.2992 7.40 7.60 4 e 0.050 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N2 0 2 0 7 α 0° 8° 0° 8° - Rev. 2 6/05