CDP68HC68P1 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Fully Static Operation
  • Operating Voltage Range 3-6V
  • Compatible with Intersil/Motorola SPI Bus
  • 2 External Address Pins Tied to V DD or VSS to Allow Up to

4 Devices to Share the Same Chip Enable

  • Versatile Bit-Set and Bit-Clear Capability
  • Accepts Either SCK Clock Polarity - SCK Voltage Level is Latched When Chip Enable Goes Active
  • All Inputs are Schmitt-Trigger
  • 8-Bit I/O Port - Each Bit can be Individually Programmed as an Input or Output Via an 8-Bit Data Direction Register
  • Programmable On Board Comparator
  • Simultaneous Transfer of Compare Information to CPU During Read or Write - Separate Access Not Required Pinout CDP68HC68P1 (PDIP, SOIC) TOP VIEW

Ordering Information

TEMP. RANGE (oC) PACKAGE PKG. NO. CDP68HC68P1E -55 to 85 16 Ld PDIP E16.3 CDP68HC68P1M -55 to 85 16 Ld SOIC M16.15 ID0 MISO MOSI SCK CE VSS DO VDD D1ID1 FN1858.3 CDP68HC68P1 Data Sheet September 2003 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.

Absolute Maximum Ratings Thermal Information (Voltage Referenced to VSS Terminal) Power Dissipation Per Package (PD) TA = 60oC to 85oC (Package Type E) TA = 60oC to 85oC (Package Type M) (Note 1) Operating Conditions Temperature Range (TA) Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) TA = Full Package Temperature Range (All Package Types) Maximum Storage Temperature Range (TSTG) . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Abs olute Maximum Ratings” may cause permanent dam age to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Printed circuit board mount: 57mm x 57mm minimum ar ea x 1.6mm thick G10 epoxy glass, or equivalent. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Static Electrical Specifications TA = -40oC to 85oC, VDD = 3.3V ±10%, Unless Otherwise Specified. PARAMETER SYMBOL TEST CONDITIONS MIN (NOTE 3) TYP MAX UNITS Output Voltage V OH IOH = -0.4mA, VDD = 3V 2.7 - - V VOL IOL = 0.4mA, VDD = 3V - - 0.3 V Input Voltage D0 - D7 Positive Trigger Threshold VP 1.85 - 2.4 V Negative Trigger Threshold V N 0.85 - 1.35 V Hysteresis V IH 0.85 - 1.25 V Input Voltage ID0, ID1, MOSI, SCK, CE Positive Trigger Threshold VP 1.3 - 1.9 V Negative Trigger Threshold V N 0.8 - 1.2 V Hysteresis V IH 0.5 - 0.95 V Input Leakage Current I IN -- ±1µ A Standby Device Current I DDS -1 1 5 µ A Three-State Output Leakage Current I OUT -- ±10 µA Operating Device Current (Note 4) I OPER VIN = VIL, VIH -0 . 11 m A Input Capacitance C IN VIN = 0V, f = 1MHz, TA = 25oC- 4 6 p F NOTES: 3. Typical values are for T A = 25oC and nominal VDD. 4. Outputs open circuited; cycle time = Min. t CYCLE, duty = 100%. CDP68HC68P1

Static Electrical Specifications At TA = -40oC to 85oC, VDD = 5V ±10%, Unless Otherwise Specified. PARAMETER SYMBOL TEST CONDITIONS MIN (NOTE 5) TYP MAX UNITS Output Voltage V OH IOH = -1.6mA, VDD = 4.5V 3.7 - - V VOL IOL = 1.6mA, VDD = 4.5V - - 0.4 V VOH IOH ≤ 20µA, VDD = 4.5V 4.4 - - V VOL IOL ≤ 20µA, VDD = 4.5V - - 0.1 V Input Voltage D0 - D7 Positive Trigger Threshold VP 2.15 - 3.05 V Negative Trigger Threshold V N 1.35 - 2 V Hysteresis V IH 0.8 - 1.2 V Input Voltage ID0, ID1, MOSI, SCK, CE Positive Trigger Threshold VP 3.15 - 3.85 V Negative Trigger Threshold V N 1.7 - 2.25 V Hysteresis V IH 1.3 - 1.7 V Input Leakage Current I IN -- ±1µ A Standby Device Current I DDS - 1 15 µA Three-State Output Leakage Current I OUT -- ±10 µA Operating Device Current (Note 6) IOPER VIN = VIL, VIH -0 . 22 m A Input Capacitance C IN VIN = 0V, f = 1MHz, TA = 25oC- 4 6 p F NOTES: 5. Typical values are for TA = 25oC and nominal VDD. 6. Outputs open circuited; cycle time = Min, t CYCLE, duty = 100%. Dynamic Electrical Specifications - Bus Timing VDD ±10%, VSS = 0V DC, TA = -40oC to 85oC, CL = 200pF. See Figures 8 and 9. PARAMETER SYMBOL VDD = 3.3V V DD = 5V UNITSMIN MAX MIN MAX Chip Enable Set-Up Time t EVCV 200 - 100 - ns Chip Enable after Clock Hold Time t CVEX 250 - 125 - ns Clock Width High t WH 400 - 200 - ns Clock Width Low t WL 400 - 200 - ns Data In to Clock Set-Up Time t DVCV 200 - 100 - ns Data In after Clock Hold Time t CVDX 200 - 100 - ns Clock to Data Propagation Delay t CVDV - 200 - 100 ns Chip Disable to Output High Z t EXQZ - 200 - 100 ns Output Rise Time t r - 200 - 100 ns Output Fall Time t f - 200 - 100 ns Clock to Data Out Archive t CVQX - 200 - 100 ns Clock Recovery Time t REC 200 - 200 - ns CDP68HC68P1

devices sharing the same chip enable. sense one of four separate conditions. condition is satisfied. Otherwise, the flag is cleared to zero. change the interpretation of this data as shown in Table 2. register without having to write to bits not requiring change.

01 A l l m a t c h

1 1 At least one matchTABLE 2. 0 X Data following the control word will be written to the selected register. which are a 0 will cause that register flip-flop to be unchanged. are a 0 will cause that register flip-flop to be unchanged. TABLE 3. EXAMPLE FIGURE 6. CONTROL BYTE

Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JE- DEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be perpendic- ular to datum . 7. e B and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E16.3 (JEDEC MS-001-BB ISSUE D)

16 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N1 6 1 6 9 Rev. 0 12/93

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com CDP68HC68P1 Small Outline Plastic Packages (SOIC) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. In- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimen- sions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM B S e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45o C H µ 0.25(0.010) BM M α M16.15 (JEDEC MS-012-AC ISSUE C)

16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.053 0.069 1.35 1.75 - A1 0.004 0.010 0.10 0.25 - B 0.014 0.019 0.35 0.49 9 C 0.007 0.010 0.19 0.25 - D 0.386 0.394 9.80 10.00 3 E 0.150 0.157 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.228 0.244 5.80 6.20 - h 0.010 0.020 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N1 6 1 6 7 α 0o 8o 0o 8o - Rev. 1 02/02