CDP6872

CDP6872 INTERSIL | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 15

Technical content

Features

• Drives 2 CMOS Loads
• Only Requires an External Crystal for Operation

Applications

• Battery Powered Circuits
• Remote Metering
• Embedded Microprocessors
• Palm Top/Notebook PC January 1996 Pinout CDP6872 (PDIP, SOIC) TOP VIEW VDD OSC IN OSC OUT VSS ENABLE FREQ 2 FREQ 1 OUTPUT Typical Application Circuit 32.768kHz MICROPOWER CLOCK OSCILLATOR VDD CDP6872 32.768kHz CLOCK 32.768kHz CRYSTAL 0.1µf File Number 4069

Simplified Block Diagram FREQUENCY SELECTION TRUTH TABLE ENABLE FREQ 1 FREQ 2 SWITCH OUTPUT RANGE 1 1 1 S1a, b, c 10kHz - 100kHz 1 1 0 S2 100kHz - 1MHz 1 0 1 S3 1MHz - 5MHz 1 0 0 S4 5MHz - 10MHz+

0 X X X High Impedance

NOTE: 1. Logic input pull-up resistors are constant current source of 0.4µA.

1 OF 4

VDD - 1.4V VDD - 2.2V VDD - 3.0V VDD - 3.8V FREQ 1 FREQ 2 ENABLE VDD 15pF S1b S1c 15pF VDD R F VDD VRN VRN S1a VDD

4 VSS

N P VDD VRN P IN R F OUT OSCILLATOR (NOTE 1) (NOTE 1) (NOTE 1)

Specifications CDP6872 Absolute Maximum Ratings Operating Conditions oC (SOIC - Lead Tip Only) Thermal Information(Typical) Thermal Resistance (oC/W) θJA CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical SpecificationsVSS = GND, TA = +25oC, Unless Otherwise Specified PARAMETER VDD = 5V V DD = 3V UNITSMIN TYP MAX MIN TYP MAX VDD Supply Range (fOSC = 32kHz) 2 5 7 - - - V IDD Supply Current fOSC = 32kHz, EN = 0 Standby - 5.0 9.0 - - - µA fOSC = 32kHz, CL = 10pF (Note 1), EN = 1, Freq1 = 1, Freq2 = 1 - 5.2 10.2 - 3.6 6.1 µA fOSC = 32kHz, CL = 40pF, EN = 1, Freq1 = 1, Freq2 = 1 - 10 15 - 6.5 9 µA fOSC = 1MHz, CL = 10pF (Note 1), EN = 1, Freq1 = 0, Freq2 = 1 - 130 200 - 90 180 µA fOSC = 1MHz, CL = 40pF, EN = 1, Freq1 = 0, Freq2 = 1 - 270 350 - 180 270 µA VOH Output High Voltage (IOUT = -1mA) 4.0 4.9 - - 2.8 - V VOL Output Low Voltage (IOUT = 1mA) - 0.07 0.4 - 0.1 - V IOH Output High Current (VOUT ≥ 4V) - -10 -5 - - - mA IOL Output Low Current (VOUT ≤ 0.4V) 5.0 10.0 ---- m A Three-State Leakage Current (VOUT = 0V, 5V, TA = 25oC, -40oC ) - 0 . 1 ----n A (VOUT = 0V, 5V, TA = 85oC ) - 1 0 ----n A IIN Enable, Freq1, Freq2 Input Current (VIN = VSS to VDD ) - 0.4 1.0 - - - µA VIH Input High Voltage Enable, Freq1, Freq2 2.0 ----- V VIL Input Low Voltage Enable, Freq1, Freq2 - - 0.8 - - - V Enable Time (CL = 18pF, RL = 1kΩ ) - 8 0 0 ----n s Disable Time (CL = 18pF, RL = 1kΩ ) - 9 0 ----n s tR Output Rise Time (10% - 90%, fOSC = 32kHz, CL = 40pF) - 12 25 - 12 - ns tF Output Fall Time (10% - 90%, fOSC = 32kHz, CL = 40pF) - 12 25 - 14 - ns Duty Cycle (CL = 40pF) fOSC = 1MHz, Packaged Part Only (Note 4) 40 54 60 - - - % Duty Cycle (CL = 40pF) fOSC = 32kHz, (See Typical Curves) - 41 - - 44 - % Frequency Stability vs. Supply Voltage (fOSC = 32kHz, VDD = 5V, CL=10pF) - 1 ---- ppm/V Frequency Stability vs. Temperature (fOSC = 32kHz, VDD = 5V, CL=10pF) - 0.1 ---- ppm/oC Frequency Stability vs. Load (fOSC = 32kHz, VDD = 5V, CL=10pF) - 0.01 ---- ppm/pF NOTES: 1. Calculated using the equation IDD = IDD (No Load) + (VDD ) (fOSC )(CL) 2. Human body model. 3. This product is production tested at +25 oC only. 4. Duty cycle will vary with supply voltage, oscillation frequency, and parasitic capacitance on the crystal pins.

FIGURE 1. In production the CDP6872 is tested with a 32kHz and a 1MHz crystal. However for characterization purposes data was taken using a sinewave generator as the frequency determining element, as shown in Figure 1. The 1V P-P input is a smaller amplitude than what a typical crystal would gen- erate so the transitions are slower. In general the Generator data will show a “worst case” number for I DD , duty cycle, and rise/fall time. The Generator test method is useful for testing a variety of frequencies quickly and provides curves which can be used for understanding performance trends. Data for the CDP6872 using crystals has also been taken. This data has been overlaid onto the generator data to provide a refer- ence for comparison. Theory of Operation The CDP6872 is a Pierce Oscillator optimized for low power consumption, requiring no external components except for a bypass capacitor and a Parallel Mode Crystal. The Simpli- fied Block Diagram shows the Crystal attached to pins 2 and 3, the Oscillator input and output. The crystal drive circuitry is detailed showing the simple CMOS inverter stage and the P-channel device being used as biasing resistor R F. The inverter will operate mostly in its linear region increasing the amplitude of the oscillation until limited by its transconduc- tance and voltage rails, V DD and VRN . The inverter is self biasing using RF to center the oscillating waveform at the input threshold. Do not interfere with this bias function with external loads or excessive leakage on pin 2. Nominal value for R F is 17MΩ in the lowest frequency range to 7MΩ in the highest frequency range. The CDP6872 optimizes its power for 4 frequency ranges selected by digital inputs Freq1 and Freq2 as shown in the Block Diagram. Internal pull up resistors (constant current 0.4µA) on Enable, Freq1 and Freq2 allow the user simply to leave one or all digital inputs not connected for a corre- sponding “1” state. All digital inputs may be left open for 10kHz to 100kHz operation. A current source develops 4 selectable reference voltages through series resistors. The selected voltage, V RN , is buff- ered and used as the negative supply rail for the oscillator CDP6872 VOUT C L +5V 18pF 0.1µF 1000pF 50Ω ENABLE FREQ 2 FREQ 1 1VP-P CDP6872 section of the circuit. The use of a current source in the refer- ence string allows for wide supply variation with minimal effect on performance. The reduced operating voltage of the oscillator section reduces power consumption and limits transconductance and bandwidth to the frequency range selected. For frequencies at the edge of a range, the higher range may provide better performance. The OSC OUT waveform on pin 3 is squared up through a series of inverters to the output drive stage. The Enable function is implemented with a NAND gate in the inverter string, gating the signal to the level shifter and output stage. Also during Disable the output is set to a high impedance state useful for minimizing power during standby and when multiple oscillators are OR'd to a single node. Design Considerations The low power CMOS transistors are designed to consume power mostly during transitions. Keeping these transitions short requires a good decoupling capacitor as close as pos- sible to the supply pins 1 and 4. A ceramic 0.1µF is recom- mended. Additional supply decoupling on the circuit board with 1µF to 10µF will further reduce overshoot, ringing and power consumption. The CDP6872, when compared to a crystal and inverter alone, will speed clock transition times, reducing power consumption of all CMOS circuitry run from that clock. Power consumption may be further reduced by minimizing the capacitance on moving nodes. The majority of the power will be used in the output stage driving the load. Minimizing the load and parasitic capacitance on the output, pin 5, will play the major role in minimizing supply current. A secondary source of wasted supply current is parasitic or crystal load capacitance on pins 2 and 3. The CDP6872 is designed to work with most available crystals in its frequency range with no external components required. Two 15pF capacitors are internally switched onto crystal pins 2 and 3 to compensate the oscillator in the 10kHz to 100kHz frequency range. The supply current of the CDP6872 may be approximately calculated from the equation: I DD = IDD (Disabled) + VDD × FOSC × CL where: IDD = Total supply current VDD = Total voltage from VDD (pin1) to VSS (pin4) FOSC = Frequency of Oscillation C L = Output (pin5) load capacitance Example #1: V DD = 5V, FOSC = 100kHz, CL = 30pF IDD (Disabled) = 4.5µA (Figure 10) IDD = 4.5µA + (5V)(100kHz)(30pF) = 19.5µA Measured IDD = 20.3µA Example #2: V DD = 5V, FOSC = 5MHz, CL = 30pF IDD (Disabled) = 75µA (Figure 9) IDD = 75µA + (5V)(5MHz)(30pF) = 825µA Measured IDD = 809µA

DIE DIMENSIONS: 68 x 64 x 14± 1mils METALLIZATION: Type: Si - Al Thickness: 10k Å ± 1kÅ GLASSIVATION: Type: Nitride (Si3N 4) Over Silox (SiO2, 3% Phos) Silox Thickness: 7kÅ ± 1kÅ Nitride Thickness: 8kÅ ± 1kÅ DIE ATTACH: Material: Silver Epoxy - Plastic DIP and SOIC SUBSTRATE POTENTIAL: VSS Metallization Mask Layout CDP6872 (1) VDD CRYSTAL (2) CRYSTAL (3) VSS (4) OUTPUT (5) (6) FREQ 1 (7) FREQ 2 (8) ENABLE

NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protru- sions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be per- pendicular to datum . 7. e B and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). CL E eA C eB eC -B- INDEX 1 2 3 N/2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM B S eA -C- Dual-In-Line Plastic Packages (PDIP) E8.3(JEDEC MS-001-BA ISSUE D)

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.355 0.400 9.01 10.16 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N8 8 9 Rev. 0 12/93

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 CDP6872 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. In- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimen- sions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM B S e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45o C H 0.25(0.010) BM M α Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N8 8 7 α 0o 8o 0o 8o - Rev. 0 12/93 Spec Number