CDP1872C INTERSIL | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 6
Technical content
Features
- Parallel 8-Bit Input/Output Register with Buffered Out- puts
- High-Speed Data-In to Data-Out 85ns (Max) at VDD = 5V
- Flexible Applications In Microprocessor Systems as Buffers and Latches
- High Order Address-Latch Capability in CDP1800- Series Microprocessor Systems
- Output Sink Current = 5mA (Min) at VDD = 5V
- Three-State Output - CDP1872C and CDP1874C
Ordering Information
NUMBER TEMP. RANGE PACKAGE PKG. NO. CDP1872CE -40 oC to +85oC PDIP E22.4 CDP1874CE -40 oC to +85oC PDIP E22.4 CDP1875CE -40 oC to +85oC PDIP E22.4 March 1997 File Number 1255.2 CDP1874C INPUT PORT (PDIP) TOP VIEW DI0 DO0 DI1 D01 DI2 D02 D03 DI3 CLOCK VSS DI7 DI6 D06 DI5 D07 D05 DI4 D04 CLR CS2 CS1 VDD CDP1875C OUTPUT PORT (PDIP) TOP VIEW DI0 DO0 DI1 D01 DI2 D02 D03 DI3 CS3 VSS DI7 DI6 D06 DI5 D07 D05 DI4 D04 CLR CS2 CS1 VDD Pinouts CDP1872C INPUT PORT (PDIP) TOP VIEW DI0 DO0 DI1 D01 DI2 D02 D03 DI3 CLOCK VSS DI7 DI6 D06 DI5 D07 D05 DI4 D04 CLR CS2 CS1 VDD CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999
Absolute Maximum Ratings Thermal Information (Voltage referenced to VSS Terminal) Thermal Resistance (Typical) θJA (oC/W) Device Dissipation Per Output Transistor TA = Full Package Temperature Range Operating Temperature Range (TA) Lead Temperature (During Soldering) At distance 1/16± 1/32 In. (1.59± 0.79mm) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Recommended Operating Conditions At TA = -40 to +85oC. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: PARAMETER LIMITS ALL TYPES UNITS DC Operating-Voltage Range 4 to 6.5 V Input Voltage Range V SS to VDD V Static Electrical SpecificationsAt TA = -40 to +85oC, VDD ±5%, Unless Otherwise Specified. PARAMETER TEST CONDITIONS LIMITS ALL TYPES UNITS VO (V) VIN (V) VDD (V) MIN (NOTE 1) TYP MAX Quiescent Device Current I DD -0 , 55 - 2 55 0 µA Output Low Drive (Sink) Current IOL 0.4 0, 5 5 5 10 - mA Output High Drive (Source) Current IOH 4.6 0, 5 5 -4 -7 - mA Output Voltage Low-Level (Note 2) VOL - 0, 5 5 - 0 0.1 V Output Voltage High-Level (Note 2) VOH - 0, 5 5 4.9 5 - V Input Low Voltage V IL 0.5, 4.5 - 5 - - 1.5 V Input High Voltage V IH 0.5, 4.5 - 5 3.5 - - V Input Leakage Current I IN - 0, 5 5 - - ±1 µA Three-State Output Leakage Current (Note 3) IOUT 0, 5 0, 5 5 - - ±5 µA Input Capacitance C IN ---- 1 5 - p F Output Capacitance (Note 3) COUT ---- 1 5 - p F NOTES: 1. Typical values are for TA = +25oC and nominal VDD ±5%. 2. IOL = IOH = 1µA 3. For CDP1872C and CDP1874C only. CDP1872C, CDP1874C, CDP1875CCDP1872C, CDP1874C, CDP1875C
All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
1130 Brussels, Belgium
FIGURE 8. CDP1874C AND CDP1875C USED AS INPUT/OUTPUT BUFFERS