CDP1854A INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Two Operating Modes - Mode 0 - Functionally Compatible with Industry Types Such as the TR1602A and CDP6402 - Mode 1 - Interfaces Directly with CDP1800-Series Microprocessors without Additional Components
  • Full or Half Duplex Operation
  • Parity, Framing and Overrun Error Detection
  • Baud Rate - DC to 200K Bits/s at V
  • Fully Programmable with Externally Selectable Word Length (5-8 Bits), Parity Inhibit, Even/Odd Parity, and 1, 1-1/2, or 2 Stop Bits
  • False Start Bit Detection

Description

The CDP1854A and CDP1854AC are silicon-gate CMOS Universal Asynchronous Receiver/Transmitter (UART) cir- cuits. They are designed to provide the necessary formatting and control for interfacing between serial and parallel data. For example, these UARTs can be used to interface between a peripheral or terminal with serial I/O ports and the 8-bit CDP1800-series microprocessor parallel data bus system. The CDP1854A is capable of full duplex operation, i.e., simultaneous conversion of serial input data to parallel out- put data and parallel input data to serial output data. The CDP1854A UART can be programmed to operate in one of two modes by using the mode control input. When the input is high (MODE = 1), the CDP1854A is directly compati- ble with the CDP1800-series microprocessor system without additional interface circuitry. When the mode input is low (MODE = 0), the device is functionally compatible with indus- try standard UART’s such as the TR1602A and CDP6402. It is also pin compatible with these types, except that pin 2 is used for the mode control input. The CDP1854A and the CDP1854AC are functionally identi- cal. The CDP1854A has a recommended operating voltage range of 4V to 10.5V, and the CDP1854AC has a recom- mended operating voltage range of 4V to 6.5V.

Ordering Information

TEMP. RANGE 5V/200K BAUD 10V/400K BAUD PKG. NO. PDIP -40 oC to +85oC CDP1854ACE CDP1854AE E40.6 Burn-In CDP1854ACEX CDP1854AEX E40.6 PLCC -40 oC to +85oC CDP1854ACQ CDP1854AQ N44.65 SBDIP -40 oC to +85oC CDP1854ACD CDP1854AD D40.6 Burn-In CDP1854ACDX - D40.6 March 1997 CDP1854A, CDP1854AC Programmable Universal Asynchronous Receiver/Transmitter (UART) File Number 1193.2CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

40 LEAD SBDIP, PDIP (MODE 0)

40 LEAD SBDIP, PDIP (MODE 1)

44 LEAD PLCC (Q SUFFIX)

MODE (V SS ) VSS RRD R BUS 7 R BUS 6 R BUS 5 R BUS 4 R BUS 3 R BUS 2 R BUS 1 R BUS 0 PE FE OE SFD R CLOCK DAR DA SDI T CLOCK EPE WLS 1 WLS 2 SBS PI CRL T BUS 7 T BUS 6 T BUS 5 T BUS 4 T BUS 3 T BUS 2 T BUS 1 T BUS 0 SD0 TSRE THRL THRE MR VDD MODE (V DD ) VSS CS2 R BUS 7 R BUS 6 R BUS 5 R BUS 4 R BUS 3 R BUS 2 R BUS 1 R BUS 0 INT FE PE/OE RSEL R CLOCK TPB DA SDI T CLOCK CTS ES PS1 NC CS3 RD/ WR T BUS 7 T BUS 6 T BUS 5 T BUS 4 T BUS 3 T BUS 2 T BUS 1 T BUS 0 SD0 R TS CS1 THRE CLEAR NC = NO CONNECT 44 43 42 41 40 2827 123456 20 21 22 23 24 25 261918 R BUS 6 R BUS 5 R BUS 4 R BUS 3 R BUS 2 NC R BUS 1 R BUS 0 PE( INT) FE OE(PE/OE) PI (CS3) CRL(RD/ WR) T BUS 7 T BUS 6 T BUS 5 NC T BUS 4 T BUS 3 T BUS 2 T BUS 1 T BUS 0 R BUS 7 RRD (CS2) VSS MODE VDD NC T CLOCK EPE (CTS) WLS1 (ES) WLS2 (PSI) SBS (NC) SFD (RSEL) R CLOCK (TPB)DAR DA(DA) SDI NC MR( CLEAR) THRE( THRE) THRL(CS1) TSRE( R TS) SD0 NOTE: MODE 0(MODE 1) CDP1854A, CDP1854AC

FIGURE 1. MODE 1 BLOCK DIAGRAM (CDP1800-SERIES MICROPROCESSOR COMPATIBLE)

Absolute Maximum Ratings Thermal Information DC Supply-Voltage Range, (VDD ) (Voltages Referenced to VSS Terminal) DD + 0.5V Device Dissipation Per Output Transistor Operating-Temperature Range (TA) Thermal Resistance (Typical, Note 1)θJA (oC/W) θJC (oC/W) Maximum Junction Temperature oC Maximum Storage Temperature Range (TSTG ) . . .-65oC to +150oC Maximum Lead Temperature (Soldering 10s): NOTE: Printed circuit board mount: 57mm x 57mm minimum area x 1.6mm thick G10 epoxy glass, or equivalent. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Static Electrical Specificationsat TA = -40oC to +85oC, Unless Otherwise Noted PARAMETER CONDITIONS LIMITS UNITS VO (V) VIN (V) VDD (V) CDP1854A CDP1854AC MIN (NOTE 1) TYP MAX MIN (NOTE 1) TYP MAX Quiescent Device Current IDD - 0, 5 5 - 0.01 50 - 0.02 200 µA - 0, 10 10 - 1 200 - - - µA Output Low Drive (Sink) Current (Except pins 24 and 25) I OL 0.4 0, 5 5 1 2 - 1 2 - mA 0.5 0, 10 10 2 4 - - - - mA Output High Drive (Source) Current Output Low Drive (Sink) Current (Pins 24 and 25) I 0.5 0, 10 10 3.2 7 - - - - mA Output Voltage Low-Level (Note 2) VOL - 0, 5 5 - 0 0.1 - 0 0.1 V Output Voltage High-Level (Note 2) VOH - 0, 5 5 4.9 5 - 4.9 5 - V Input Low Voltage V IL 0.5, 4.5 - 5 - - 1.5 - - 1.5 V Input High Voltage V Input Current I CDP1854A, CDP1854AC

IOUT 0, 5 0, 5 5 - - ±1- - ±1 µA Operating Current (Note 3) IDD1 - 0, 5 5 - 1.5 - - 1.5 - mA Input Capacitance C IN - - - - 5 7.5 - 5 7.5 pF Output Capacitance C OUT - - - - 10 15 - 10 15 pF NOTES: 1. Typical values are for TA = 25oC. 2. IOL = IOH = 1µA. 3. Operating current is measured at 200kHz or VDD = 5V and 400kHz for VDD = 10V in a CDP1800-series microprocessor system, with open outputs. Operating ConditionsAt TA = Full Package-Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: PARAMETER CONDITIONS LIMITS UNITS VDD (V) CDP1854A CDP1854AC MIN MAX MIN MAX DC Operating Voltage Range - 4 10.5 4 6.5 V Input Voltage Range - V SS VDD VSS VDD V Baud Rate (Receive or Transmit) 5 - 200 - 200 K bits/s 10 - 400 - - K bits/s Static Electrical Specificationsat TA = -40oC to +85oC, Unless Otherwise Noted (Continued) PARAMETER CONDITIONS LIMITS UNITS VO (V) VIN (V) VDD (V) CDP1854A CDP1854AC MIN (NOTE 1) TYP MAX MIN (NOTE 1) TYP MAX CDP1854A, CDP1854AC

Functional Definitions for CDP1854A Terminals Mode 1 CDP1800-Series Microprocessor Compatible SIGNAL: FUNCTION VDD : Positive supply voltage. MODE SELECT (MODE): A high-level voltage at this input selects CDP1800-series microprocessor Mode operation. V SS : Ground CHIP SELECT 2 (CS2): A low-level voltage at this input together with CS1 and CS3 selects the CDP1854A UART. RECEIVER BUS (R BUS 7 - R BUS 0): Receiver parallel data outputs (may be externally connected to corresponding transmitter bus terminals). INTERR UPT (INT): A low-level voltage at this output indicates the presence of one or more of the interrupt conditions listed in Table 1. FRAMlNG ERROR (FE): A high-level voltage at this output indicates that the received character has no valid stop bit, i.e., the bit following the parity bit (if programmed) is not a high-level voltage. This output is updated each time a character is transferred to the Receiver Holding Register. PARITY ERROR or OVERRUN ERROR (PE/OE): A high-level voltage at this output indicates that either the PE or OE bit in the Status Register has been set (see Status Register Bit Assignment, Table 2). REGISTER SELECT (RSEL): This input is used to choose either the Control/Status Registers (high input) or the transmitter/receiver data registers (low input) according to the truth table in Table 3. RECEIVER CLOCK (RCLOCK): Clock input with a frequency 16 times the desired receiver shift rate. TPB: A positive input pulse used as a data load or reset strobe. DATA AVAILABLE (DA): A low-level voltage at this output indicates that an entire character has been received and transferred to the Receiver Holding Register. SERIAL DATA IN (SDl): Serial data received on this input line enters the Receiver Shift Register at a point determined by the character length. A high-level input voltage must be present when data is not being received. CLEAR ( CLEAR): A low-level voltage at this input resets the Interrupt Flip- Flop, Receiver Holding Register, Control Register, and Status Register, and sets SERIAL DATA OUT (SDO) high. TRANSMlTTER HOLDING REGISTER EMPTY ( THRE): A low-level voltage at this output indicates that the Transmitter Holding Register has transferred its contents to the Transmitter Shift Register and may be reloaded with a new character. CHIP SELECT 1 (CS1): A high-level voltage at this input together with CS2 and CS3 selects the UART. REQ UEST T O SEND (R TS): This output signal tells the peripheraI to get ready to receive data.CLEAR T O SEND ( CTS) is the response from the peripheral.RTS is set to a low-level voltage when data is latched in the Transmitter Holding Register or TR is set high, and is reset high when both the Transmitter Holding Register and Transmitter Shift Register are empty and TR is low. SERAL DATA OUTPUT (SDO): The contents of the Transmitter Shift Register [start bit, data bits, parity bit, and stop bit(s)] are serially shifted out on this output. When no character is being transmitted, a high level is maintained. Start of transmission is defined as the transition of the start bit from a high-level to a low-level output voltage. TRANSMlTTER BUS (T BUS 0 - T BUS 7): Transmitter parallel data input. These may be externally connected to corresponding Receiver bus terminals. RD/ WR: A low-level voltage at this input gates data from the transmitter bus to the Transmitter Holding Register or the Control Regis- ter as chosen by register select. A high-level voltage gates data from the Receiver Holding Register or the Status Regis- ter, as chosen by register select, to the receiver bus. CHIP SELECT 3 (CS3): With high-level voltage at this input together with CS1 and CS2 selects the UART. PERIPHERAL ST ATUS INTERR UPT (PSI): A high-to-low transition on this input line sets a bit in the Status Register and causes an INTERRUPT (INT = low). EXTERNAL ST ATUS (ES): A low-level voltage at this input sets a bit in the Status Register. CDP1854A, CDP1854AC

serial data out is inhibited. TABLE 1. INTERRUPT SET AND RESET CONDITIONS

  1. Interrupts will occur only after the IE bit in the Control Register (see Table 4) has been set.
  2. THRE will cause an interrupt only after the TR bit in the Control Register (see Table 4) has been set.

TABLE 2. STATUS REGISTER BIT ASSIGNMENT † Polarity reversed at output terminal. Holding Register. This signal is also available at Term. 19 but with its polarity reversed. transferred to the Receiver Holding Register. This signal OR’ed with PE is output at Term. 15. OR’ed with OE is output at Term. 15. Register. This signal is also available at Term. 14. output (Term. 13) is also asserted (lNT = Iow) when this bit is set. ed serial transmission of a full character including stop bit(s). It remains set until the start of transmission of the next character. output (Term. 22) low and causes an INTERRUPT (lNT = low), if TR is high.

  • CS3 = 1) and the Control Register is designated (RSEL = H, RD/WR = L). The CDP1854A also has a Status Register which can be read onto the Receiver Bus (R BUS 0 - R BUS 7) in order to determine the status of the UART. Some of these status bits are also available at separate terminals as indicated in Table 2. Transmitter Operation Before beginning to transmit, the TRANSMlT REQUEST (TR) bit in the Control Register (see bit assignment, Table 4) is set. Loading the Control Register with TR = 1 (bit 7 = high) inhibits changing the other control bits. Therefore two loads are required: one to format the UART, the second to set TR. When TR has been set, a TRANSMlTTER HOLDING REG- ISTER EMPTY ( THRE) interrupt will occur, signalling the microprocessor that the Transmitter Holding Register is empty and may be loaded. Setting TR also causes assertion of a low-level on the REQUEST TO SEND ( RTS) output to the peripheral. It is not necessary to set TR for proper opera- tion for the UART. If desired, it can be used to enable THRE interrupts and to generate theRTS signal. The Transmitter Holding Register is loaded from the bus by TPB during exe- cution of an output instruction. The CDP1854A is selected by CS1 • CS2 • CS3 = 1, and the Holding Register is selected by RSEL = L and RD/WR = L. When the CLEAR TO SEND (CTS) input, which can be connected to a periph- eral device output, goes low, the Transmitter Shift Register will be loaded from the Transmitter Holding Register and data transmission will begin. IfCTS is always low, the Trans- mitter Shift Register will be loaded on the first high-to-low edge of the clock which occurs at least 1/2 clock period after the trailing edge of TPB and transmission of a start bit will occur 1/2 clock period later (see Figure 3). Parity (if pro- grammed) and stop bit(s) will be transmitted following the last data bit. If the word length selected is less than 8 bits, the most significant unused bits in the transmitter shift regis- ter will not be transmitted. One transmitter clock period after the Transmitter Shift Reg- ister is loaded from the Transmitter Holding Register, the THRE signal will go low and an interrupt will occur (INT goes low). The next character to be transmitted can then be loaded into the Transmitter Holding Register for transmission with its start bit immediately following the last stop bit of the previous character. This cycle can be repeated until the last character is transmitted, at which time a final THRE• TSRE interrupt will occur. This interrupt signals the microprocessor that TR can be turned off. This is done by reloading the orig- inal control byte in the Control Register with the TR bit 0, thus terminating the REQ UEST T O SEND (RTS) signal. SERIAL DATA OUT (SDO) can be held low by setting the BREAK bit in the Control Register (see Table 4). SDO is held low until the BREAK bit is reset. Receiver Operation The receive operation begins when a start bit is detected at the SERlAL DATA IN (SDl) input. After detection of the first high-to-low transition on the SDl line, a valid start bit is verified by checking for a low-level input 7-1/2 receiver clock periods later. When a valid start bit has been verified, the fol- lowing data bits, parity bit (if programmed) and stop bit(s) are shifted into the Receiver Shift Register by clock pulse 7-1/2

TABLE 3. REGISTER SELECTION SUMMARY FIGURE 2. RECOMMENDED CDP1800-SERIES CONNECTION,

microprocessor responds by executing an input instruction. character which is received from the peripheral. Status Register (see Table 2). TABLE 4. CONTROL REGISTER BIT ASSIGNMENT inhibited the stop bit(s) will immediately follow the last data bit on transmission, and EPE is ignored. 2 STOP BIT SELECT (SBS): See table below. 3 WORD LENGTH SELECT 1 (WLS1): See table below. 4 WORD LENGTH SELECT 2 (WLS2): See table below.

5 INTERRUPT ENABLE (lE): When set high

transitions by transmitting a word consisting of all zeros). interrupt. (When loading the Control Register from the bus, this (TR) bit inhibits changing of other control flip-flops).

  1. Typical values for TA = 25oC and nominal voltages.
  2. Maximum limits of minimum characteristics are the values above which all devices function.
  3. The holding register is loaded on the trailing edge of TPB.
  4. The Transmitter Shift Register is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + t

the trailing edge of TPB and transmission of a start bit occurs 1/2 clock period + tCD later.

  1. Write is the overlap of TPB, CS1, and CS3 = 1 andCS3, RD/WR = 0.

FIGURE 3. TRANSMITTER TIMING DIAGRAM - MODE 1

Dynamic Electrical SpecificationsTA = -40oC to +85oC, VDD ±5%, tR , tF = 20ns, VIH = 0.7 VDD , VIL = 0.3 VDD , CL = 100pF , (See Figure 4) PARAMETER VDD (V) LIMITS UNITS CDP1854A CDP1854AC (NOTE 1) TYP (NOTE 2) MAX (NOTE 1) TYP (NOTE 2) MAX RECEIVER TIMING - MODE 1 Minimum Clock Period t CC 5 250 310 250 310 ns 10 125 155 - - ns Minimum Pulse Width Clock Low Level t CL 5 100 125 100 125 ns 10 75 100 - - ns Clock High Level t CH 5 100 125 100 125 ns 10 75 100 - - ns TPB t TT 5 100 150 100 150 ns 10 50 75 - - ns Minimum Setup Time Data Start Bit to Clock t DC 5 100 150 100 150 ns 10 50 75 - - ns Propagation Delay Time TPB toDATA AVAILABLE t TDA 5 220 325 220 325 ns 10 110 175 - - ns Clock toDATA AVAILABLE t CDA 5 220 325 220 325 ns 10 110 175 - - ns Clock to Overrun Error t COE 5 210 300 210 300 ns 10 105 150 - - ns Clock to Parity Error t CPE 5 240 375 240 375 ns 10 120 175 - - ns Clock to Framing Error t CFE 5 200 300 200 300 ns 10 100 150 - - ns NOTES: 1. Typical values for TA = 25oC and nominal voltages. 2. Maximum limits of minimum characteristics are the values above which all devices function. CDP1854A, CDP1854AC

Dynamic Electrical SpecificationsTA = -40oC to +85oC, VDD ±5%, tR , tF = 20ns, VIH = 0.7 VDD , VIL = 0.3 VDD , CL = 100pF , (See Figure 5) PARAMETER VDD (V) LIMITS UNITS CDP1854A CDP1854AC (NOTE 1) TYP (NOTE 2) MAX (NOTE 1) TYP (NOTE 2) MAX CPU INTERFACE - WRITE TIMING - MODE 1 Minimum Pulse Width TPB t TT 5 100 150 100 150 ns 10 50 75 - - ns Minimum Setup Time RSEL to Write t RSW 5 5 07 55 07 5n s 10 25 40 - - ns Data to Write t DW 5 -30 0 -30 0 ns 10 -15 0 - - ns Minimum Hold Time RSEL after Write t WRS 5 5 07 55 07 5n s 10 25 40 - - ns Data after Write t WD 5 75 125 75 125 ns 10 40 60 - - ns NOTES: 1. Typical values for TA = 25oC and nominal voltages. 2. Maximum limits of minimum characteristics are the values above which all devices function. Dynamic Electrical SpecificationsTA = -40oC to +85oC, VDD ±5%, tR , tF = 20ns, VIH = 0.7 VDD , VIL = 0.3 VDD , CL = 100pF , (See Figure 6) PARAMETER VDD (V) LIMITS UNITS CDP1854A CDP1854AC MIN (NOTE 1) TYP (NOTE 2) MAX MIN (NOTE 1) TYP (NOTE 2) MAX CPU INTERFACE - READ TIMING - MODE 1 Minimum Pulse Width TPB t TT 5 - 100 150 - 100 150 ns 10 - 50 75 - - - ns Minimum Setup Time RSEL to TPB t RST 5 - 50 75 - 50 75 ns 10 - 25 40 - - - ns Minimum Hold Time RSEL after TPB t TRS 5 - 50 75 - 50 75 ns 10 - 25 40 - - - ns Read to Data Access Time t RDDA 5 - 200 300 - 200 300 ns 10 - 100 150 - - - ns Read to Data Valid Time t RDV 5 - 200 300 - 200 300 ns 10 - 100 150 - - - RESEL to Data Valid Time t RSDV 5 - 150 225 - 150 225 ns 10 - 75 125 - - - ns Hold Time Data after Read t RDH 5 50 150 - 50 150 - ns 1 0 2 5 7 5 ---- n s NOTES: 1. Typical values for TA = 25oC and nominal voltages. 2. Maximum limits of minimum characteristics are the values above which all devices function. CDP1854A, CDP1854AC

  1. Read is the overlap of CS1, CS3, RD/WR = 1 andCS2 = 0.

FIGURE 6. MODE 1 CPU INTERFACE (READ) TIMING DIAGRAM FIGURE 7. MODE 0 BLOCK DIAGRAM (INDUSTRY STANDARD COMPATIBLE)

20 SDI

Functional Definitions for CDP1854A Terminals Standard Mode 0 SIGNAL: FUNCTION VDD : Positive supply voltage. MODE SELECT (MODE): A low-level voltage at this input selects Standard Mode 0 Operation. V SS : Ground. RECEIVER REGISTER DISCONNECT (RRD): A high-level voltage applied to this input disconnects the Receiver Holding Register from the Receiver Bus. RECEIVER BUS (R BUS 7 - R BUS 0): Receiver parallel data outputs. PARITY ERROR (PE): A high-level voltage at this output indicates that the received parity does not compare to that programmed by the EVEN PARITY ENABLE (EPE) control. This output is updated each time a character is transferred to the Receiver Holding Reg- ister. PE lines from a number of arrays can be bused together since an output disconnect capability is provided by the STATUS FLAG DISCONNECT (SFD) line. FRAMING ERROR (FE): A high-level voltage at this output indicates that the received character has no valid stop bit, i.e., the bit following the parity bit (if programmed) is not a high-level voltage. This output is updated each time a character is transferred to the Receiver Holding Register. FE lines from a number of arrays can be bused together since an output disconnect capability is pro- vided by the STATUS FLAG DISCONNECT (SFD) line. OVERRUN ERROR (OE): A high-level voltage at this output indicates that the DATA AVAILABLE (DA) flag was not reset before the next charac- ter was transferred to the Receiver Holding Register. OE lines from a number of arrays can be bused together since an output disconnect capability is provided by the STATUS FLAG DISCONNECT (SFD) line. STATUS FLAG DISCONNECT (SFD): A high-level voltage applied to this input disables the three- state output drivers for PE, FE, OE, DA, and THRE, allowing these status outputs to be bus connected. RECEIVER CLOCK (RCLOCK): Clock input with a frequency 16 times the desired receiver shift rate. DATA AVAILABLE RESET ( DAR): A low-level voltage applied to this input resets the DA flip- flop. DATA AVAILABLE (DA): A high-level voltage at this output indicates that an entire character has been received and transferred to the Receiver Holding Register. SERIAL DATA IN (SDl): Serial data received at this input enters the receiver shift register at a point determined by the character length. A high-level voltage must be present when data is not being received. MASTER RESET (MR): A high-level voltage at this input resets the Receiver Holding Register, Control Register, and Status Register, and sets the serial data output high. TRANSMlTTER HOLDING REGISTER EMPTY (THRE): A high-level voltage at this output indicates that the Transmit- ter Holding Register has transferred its contents to the Transmitter Shift Register and may be reloaded with a new character. TRANSMlTTER HOLDING REGISTER LO AD (THRL): A low-level voltage applied to this input enters the character on the bus into the Transmitter Holding Register. Data is latched on the trailing edge of this signal. TRANSMlTTER SHIFT REGISTER EMPTY (TSRE): A high-level voltage at this output indicates that the Transmit- ter Shift Register has completed serial transmission of a full character including stop bit(s). It remains at this level until the start of transmission of the next character. SERIAL DATA OUTPUT (SDO): The contents of the Transmitter Shift Register (start bit, data bits, parity bit, and stop bit(s)) are serially shifted out on this output. When no character is being transmitted, a high-level is maintained. Start of transmission is defined as the transition of the start bit from a high-level to a low-level output voltage. TRANSMlTTER BUS (T BUS 0 - T BUS 7): Transmitter parallel data inputs. CONTROL REGISTER LOAD (CRL): A high-level voltage at this input loads the Control Register with the control bits (PI, EPE, SBS, WLS1, WLS2). This line may be strobed or hardwired to a high-level input voltage. PARITY INHIBIT (PI): A high-level voltage at this input inhibits the parity generation and verification circuits and will clamp the PE output low. If parity is inhibited the stop bit(s) will immediately follow the last data bit on transmission. STOP BIT SELECT (SBS): This input selects the number of stop bits to be transmitted after the parity bit. A high-level selects two stop bits, a low- level selects one stop bit. Selection of two stop bits with five data bits programmed selects 1.5 stop bits. CDP1854A, CDP1854AC

low-level input selects odd parity. transmitter and/or receiver operation. fCLOCK) and will be 16/f CLOCK. Receiver Shift Register at clock pulse 7-1/2 in each bit time. timing diagram is shown in Figure 11. FIGURE 8. MODE 0 CONNECTION DIAGRAM

  1. Typical values for TA = 25oC and nominal voltages.
  2. Maximum limits of minimum characteristics are the values above which all devices function.

FIGURE 9. MODE 0 INTERFACE TIMING DIAGRAM

Dynamic Electrical SpecificationsTA = -40oC to +85oC, VDD ±5%, tR , tF = 20ns, VIH = 0.7 VDD , VIL = 0.3 VDD , CL = 100pF , (See Figure 10) PARAMETER VDD (V) LIMITS UNITS CDP1854A CDP1854AC (NOTE 1) TYP (NOTE 2) MAX (NOTE 1) TYP (NOTE 2) MAX TRANSMITTER TIMING - MODE 0 Minimum Clock Period t CC 5 250 310 250 310 ns 10 125 155 - - ns Minimum Pulse Width Clock Low Level t CL 5 100 125 100 125 ns 10 75 100 - - ns Clock High Level t CH 5 100 125 100 125 ns 10 75 100 - - ns THRL t THTH 5 100 150 100 150 ns 10 50 75 - - ns Minimum Setup Time THRL to Clock t THC 5 175 275 175 275 ns 10 90 150 - - ns Data toTHRL t DT 5 2 05 02 05 0n s 10 0 40 - - ns Minimum Hold Time Data afterTHRL t TD 5 80 120 80 120 ns 10 40 60 - - ns Propagation Delay Time Clock to Data Start Bit t CD 5 300 450 300 450 ns 10 150 225 - - ns Clock to THRE t CT 5 200 300 200 300 ns 10 100 150 - - ns THRL to THRE t TTHR 5 200 300 200 300 ns 10 100 150 - - ns Clock to TSRE t TTS 5 200 300 200 300 ns 10 100 150 - - ns NOTES: 1. Typical values for TA = 25oC and nominal voltages. 2. Maximum limits of minimum characteristics are the values above which all devices function. CDP1854A, CDP1854AC

Dynamic Electrical SpecificationsTA = -40oC to +85oC, VDD ±5%, tR , tF = 20ns, VIH = 0.7 VDD , VIL = 0.3 VDD , CL = 100pF , (See Figure 11) PARAMETER VDD (V) LIMITS UNITS CDP1854A CDP1854AC (NOTE 1) TYP (NOTE 2) MAX (NOTE 1) TYP (NOTE 2) MAX RECEIVER TIMING - MODE 0 Minimum Clock Period t CC 5 250 310 250 310 ns 10 125 155 - - ns Minimum Pulse Width Clock Low Level t CL 5 100 125 100 125 ns 10 75 100 - - ns Clock High Level t CH 5 100 125 100 125 ns 10 75 100 - - ns DATA AVAILABLE RESET t DD 5 5 07 55 07 5n s 10 25 40 - - ns Minimum Setup Time Data Start Bit to Clock t DC 5 100 150 100 150 ns 10 50 75 - - ns Propagation Delay Time DATA AVAILABLE RESET to Data Available tDDA 5 150 225 150 225 ns 10 75 125 - - ns Clock to Data Valid t CDV 5 225 325 225 325 ns 10 110 175 - - ns Clock to Data Available t CDA 5 225 325 225 325 ns 10 110 175 - - ns Clock to Overrun Error t COE 5 210 300 210 300 ns 10 100 150 - - ns Clock to Parity Error t CPE 5 240 375 240 375 ns 10 120 175 - - ns Clock to Framing Error t CFE 5 200 300 200 300 ns 10 100 150 - - ns NOTES: 1. Typical values for TA = 25oC and nominal voltages. 2. Maximum limits of minimum characteristics are the values above which all devices function. CDP1854A, CDP1854AC

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 CDP1854A, CDP1854AC