CDP18523 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Static Silicon-Gate CMOS Circuitry  Parallel 8-Bit Data Register and Buffer  Handshaking Via Service Request Flip-Flop  Low Quiescent and Operating Power  Interfaces Directly with CDP1800-Series Microproces- sors  Single Voltage Supply  Full Military Temperature Range (-55 oC to +125oC) Pinout CDP1852/3, CDP1852C/3 (SBDIP) TOP VIEW

Description

The CDP1852/3 and CDP1852C/3 are parallel, 8-bit, mode- programmable input/output ports. They are compatible and will interface directly with CDP1800-Series microprocessors. They are also useful as 8-bit address latches when used with the CDP1800 multiplexed address bus and as I/O ports in general-purpose applications. The mode control is used to program the device as an input port (mode = 0) or as an output port (mode = 1). The SR /SR output can be used as a signal to indicate when data is ready to be transferred. In the input mode, a peripheral device can strobe data into the CDP1852/3, and micropro- cessor can read that data by device selection. In the output mode, a microprocessor strobes data into the CDP1852/3, and handshaking is established with a peripheral device when the CDP1852/3 is deselected. In the input mode, data at the data-in terminals (DI0-DI7) is strobed into the port’s 8-bit register by a high (1) level on the clock line. The negative high-to-low transition of the clock latches the data in the register and sets the service request output low (SR/SR = 0). When CS1/CS1 and CS2 are high (CS1/CS1 and CS2 = 1), the three-state output drivers are enabled and data in the 8-bit register appear at the data-out terminals (DO0-DO7). When either CS1/CS1 or CS2 goes low (CS1/CS1 or CS2 = 0), the data-out terminals are tristated and the service request output returns high (SR/SR =1). In the output mode, the output drivers are enabled at all times. Data at the data-in terminals (DI0-DI7) is strobed into the 8-bit register when CS1/CS1 is low (CS1/CS1 = 0) and CS2 and the clock are high (1), and are present at the data- out terminals (DO0-DO7). The negative high-to-low transi- tion of the clock latches the data in the register. The SR /SR output goes high (SR/SR = 1) when the device is deselected (CS1/CS1 = 1 or CS2 = 0) and returns low (SR/SR = 0) on the following trailing edge of the clock. A CLEAR control is provided for resetting the port’s register (DO0-DO7 = 0) and service request flip-flop (input mode: SR /SR = 1 and output mode: SR/SR = 0). The CDP1852/3 is functionally identical to the CDP1852C/3. The CDP1852/3 has a recommended operating voltage range of 4V to 10.5V, and the CDP1852C/3 has a recom- mended operating voltage range of 4V to 6.5V. The CDP1852/3 and CDP1852C/3 are supplied in 24-lead, dual-in-line side-brazed ceramic packages (D suffix).

Ordering Information

TEMP. RANGE 5V 10V PKG. NO SBDIP -55 oC to +125oC CDP1852CD3 CDP1852D3 D24.6 CSI/CSI MODE DI0 DO0 DI1 DO1 DI2 DO2 DI3 DO3 CLOCK VSS VDD DI7 DO7 DI6 DO6 DO5 DO4 CLEAR CS2 SR /SR DI5 DI4 March 1997 File Number 1694.2 CDP1852/3, CDP1852C/3 High-Reliability Byte-Wide Input/Output Port CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143| Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved

FIGURE 2. CDP1852/3 LOGIC DIAGRAM

23 SR/SR

Absolute Maximum Ratings Thermal Information DC Supply Voltage Range, (VDD ): (All Voltages Referenced to VSS Terminal) DD +0.5V Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) Device Dissipation Per Output Transistor TA = Full Package Temperature Range Operating Temperature Range (TA) Lead Temperature (During Soldering): At distance 1/16 ± 1/32 in (1.59 ± 0.79mm) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Recommended Operating Conditions TA = Full-Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges. PARAMETER LIMITS UNITS CPP1852/3 CDP1852C/3 MIN MAX MIN MAX DC Operating Voltage Range 4 10.5 4 6.5 V Input Voltage Range V SS VDD VSS VDD V Static Electrical SpecificationsVIN = 0 or VDD , Except as Noted PARAMETER SYMBOL TEST CONDITIONS LIMITS UNITS -55oC, +25oC+ 1 2 5 oC MIN MAX MIN MAX Quiescent Device Current (Note 1) IDD VDD = 5V - 10 - 100 µA VDD = 10V - 20 - 300 µA Output Low Drive (Sink) Current I OL VDD = 5V, VO = 0.4V 2.6 - 1.9 - mA VDD = 10V, VO = 0.5V 6.1 - 4.1 - mA Output High Drive (Source) Current IOH VDD = 5V, VO = 4.6V -1.8 - -1.3 - mA Output Voltage Low Level V OL VDD = 5V, IOL = 0µA - 0.1 - 0.2 V VDD = 10V, IOL = 0µA - 0.1 - 0.2 V Output Voltage High Level V OH VDD = 5V, IOL = 0µA 4.9 - 4.8 - V VDD = 10V, IOL = 0µA 9.9 - 9.8 - V Input Low Voltage V IL VDD = 5V, VO = 0.2, 4.8V - 1.5 - 1.5 V VDD = 10V, VO = 0.2, 9.8V - 3 - 3 V Input High Voltage V IH VDD = 5V, VO = 0.2, 4.8V 3.5 - 3.5 - V VDD = 10V, VO = 0.2, 9.8V 7 - 7 - V Input Leakage Low I IL VDD = 5V, VIN = 0V - -1 - -5 µA VDD = 10V, VIN = 0V - -1 - -5 µA Input Leakage High I IH VDD = 5V, VIN = 5 V -1-5 µA VDD = 10V, VIN = 1 0 V -1-5 µA CDP1852/3, CDP1852C/3

Three-State Output Leakage Low I OZL VDD = 5V, VO = 0V - -1 - -5 µA VDD = 10V, VO = 0V - -1 - -5 µA Three-State Output Leakage High IOZH VDD = 5V, VO = 5 V -1-5 µA VDD = 10V, VO = 1 0 V -1-5 µA Input Capacitance C IN Note 2 - 10 - 10 pF Output Capacitance C OUT Note 2 - 15 - 15 pF NOTES: 1. The CDP1852C/3 meets all 5V static electrical specifications of the CDP1852/3 except +125oC quiescent device current for which the limit is IDD = 300µA. 2. Input and output capacitance are guaranteed but not tested. Static Electrical SpecificationsVIN = 0 or VDD , Except as Noted (Continued) PARAMETER SYMBOL TEST CONDITIONS LIMITS UNITS -55oC, +25oC+ 1 2 5 oC MIN MAX MIN MAX VDD VDD VSS VSS ALL RESISTORS 47k Ω (±20%) TYPE NO. V DD TEMPERATURE TIME CDP1852/3 11V +125 oC 160 Hrs. Min. CDP1852C/3 7V +125 oC 160 Hrs. Min. Dynamic Electrical SpecificationsMode = 0 Input Port, See Figure 3, Input tr, tf ≤ 15ns; CL = 50pF PARAMETER SYMBOL VDD VOLTS LIMITS (NOTE 1) UNITS -55oC, +25oC +125 oC (NOTE 1) MIN MAX (NOTE 1) MIN MAX Select Duration t SW 5 250 - 360 - ns 10 150 - 180 - ns Clock Pulse Width t WW 5 150 - 200 - ns 10 90 - 110 - ns Clear Pulse Width t CLR 5 110 - 160 - ns 10 50 - 80 - ns Data-In to Clock Fall Setup Time t DS 5 -10 - -10 - ns 10 -5 - -5 - ns CDP1852/3, CDP1852C/3

  1. Time required by a device to allow for the indicated function.
  2. CS1 • CS2 is the overlap of CS1 = 1 and CS2 = 1.

011 D a t a L a t c h

FIGURE 3. MODE = 0 INPUT PORT TIMING WAVEFORMS AND TRUTH TABLES

Dynamic Electrical SpecificationMode = 1 Output Port, See Figure 4, Input tr, tf ≤ 15ns; CL = 50pF PARAMETER SYMBOL VDD VOLTS LIMITS (NOTE 1) UNITS -55oC, +25oC+ 1 2 5 oC (NOTE 1) MIN MAX (NOTE 1) MIN MAX Clock Pulse Width t CLK 5 170 - 260 - ns 10 90 - 130 - ns Write Width Duration t WW 5 200 - 260 - ns 10 110 - 130 - ns Clear Pulse Width t CLR 5 110 - 135 - ns 10 60 - 75 - ns Data-In to Clock Fall Setup Time t DS 5 -10 - -10 - ns 10 -5 - -5 - ns Data Hold from Write Termination t DH 5 130 - 170 - ns 10 70 - 90 - ns Select-After Clock-Fall Hold Time t SH 50 - 0 - n s 10 0 - 0 - ns Propagation Delay Times: Clear to Data t RDO 5 - 215 - 290 ns 10 - 140 - 190 ns Write to Data Out t WDO 5 - 250 - 350 ns 10 - 130 - 190 ns Data In to Data Out t DDO 5 - 150 - 200 ns 10 - 80 - 100 ns Clear to SR t RSR 5 - 175 - 240 ns 10 - 120 - 160 ns Clock to SR t CSR 5 - 170 - 240 ns 10 - 90 - 120 ns Deselect to SR t SSR 5 - 170 - 240 ns 10 - 90 - 120 ns NOTE: 1. Time required by a device to allow for the indicated function. CDP1852/3, CDP1852C/3

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

  1. CS1 • CS2 is the overlap of the CS1 = 0 and CS2 = 1.
  2. Write is the overlap of CS1 • CS2 and clock.

0 X 1 Data Latch

FIGURE 4. MODE = 1 OUTPUT PORT TIMING WAVEFORMS AND TRUTH TABLES