CDP1824 INTERSIL | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 6

Technical content

Features

  • Fast Access Time
  • No Precharge or Clock Required

Description

The CDP1824 and CDP1824C are 32-word x 8-bit fully static CMOS random-access memories for use in CDP-1800 series microprocessor systems. These parts are compatible with the CDP1802 microprocessor and will interface directly without additional components. The CDP1824 is fully decoded and does not require a pre- charge or clocking signal for proper operation. It has common input and output and is operated from a single voltage supply. The MRD signal (output disable control) enables the three-state output drivers, and overrides the MWR signal. ACS input is provided for memory expansion. The CDP1824C is functionally identical to the CDP1824. The CDP1824 has an operating range of 4V to 10.5V, and the CDP1824C has an operating voltage range of 4V to 6.5V. The CDP1824 and CDP1824C are supplied in 18 lead hermetic dual-in-line ceramic packages (D suffix), and in 18 lead dual-in-line plastic packages (E suffix). Pinout CDP1824, CDP1824C (PDIP, SBDIP) TOP VIEW

Ordering Information

5V 10V PACKAGE TEMPERATURE RANGE PKG. NO. CDP1824CE CDP1824E PDIP -40 oC to +85oC E18.3 CDP1824CEX CDP1824EX Burn-In E18.3 CDP1824CD CDP1824D SBDIP -40 oC to +85oC D18.3

1 VDD

V SS OPERATIONAL MODES FUNCTION CS MRD MWR DATA PINS STATUS READ 0 0 X Output: High/Low Dependent on Data WRITE 0 1 0 Input: Output Disabled Not Selected

1 X X Output Disabled:

Standby 0 1 1 Output Disabled: High-Impedance State Logic 1 = High Logic 0 = Low X = Don’t Care March 1997 CDP1824, CDP1824C 32-Word x 8-Bit Static RAM File Number 1103.2CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

Absolute Maximum Ratings Thermal Information DC Supply Voltage Range, (VDD ) (All Voltages Referenced to VSS Terminal) DD +0.5V Operating Temperature Range (TA) Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) Lead Temperature (During Soldering) At distance 1/16±1/32 In. (1.59 ± 0.79mm) Recommended Operating Conditions At TA = Full Package Temperature Range.For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: PARAMETER CONDITION LIMITS UNITSVDD (V) CDP1824D CDP1824CD MIN MAX MIN MAX Supply Voltage Range - 4 10.5 4 6.5 V Recommended Input Voltage Range - V SS VDD VSS VDD V Input Signal Rise or Fall Time (Note 1) 5 - 5 - 5 µs tR , tF 10 - 2 - - µs NOTE: 1. Input signal rise or fall times longer than these maxima can cause loss of stored data in either the selected or deselected mode. Static Electrical SpecificationsAt TA = -40oC to +85oC, Except as Noted: PARAMETER SYMBOL CONDITIONS LIMITS UNITS VO (V) VIN (V) VDD (V) CDP1824 CDP1824C MIN (NOTE 1) TYP MAX MIN (NOTE 1) TYP MAX Quiescent Device Current IDD - - 5 - 25 50 - 100 200 µA - - 10 - 250 500 - - - µA Output Low (Sink) Current Output High (Source) Current Output Voltage Low-Level VOL - 0, 5 5 - 0 0.1 - 0 0.1 V Output Voltage High-Level VOH - 0, 5 5 4.9 5 - 4.9 5 - V Input Low Voltage V IL 0.5, 4.5 - 5 - - 1.5 - - 1.5 V Input High Voltage V IH 0.5, 9.5 - 5 3.5 - - 3.5 - - V Input Leakage Current I IN Any Input Operating Current (Note 2) IDD1 - 0, 5 5 - 4 8 - 4 8 mA - 0, 10 10 - 8 16 - - - mA CDP1824, CDP1824C

  1. Typical values are for TA = +25oC and nominal VDD .
  2. Outputs open circuited; Cycle time = 1µs.
  3. Time required by a limit device to allow for the indicated function.
  4. Time required by a typical device to allow for the indicated function. Typical values are for T
  5. Minimum timing for valid data output longer times will initiate an earlier, but invalid output.

FIGURE 1. READ CYCLE TIMING DIAGRAMS

FIGURE 4. FUNCTIONAL DIAGRAM FIGURE 5. CDP1824 (128 X 8) MINIMUM SYSTEM (128 X 8)

32 X 8-BIT

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 CDP1824, CDP1824C