CDP18243 INTERSIL | Alldatasheet
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Technical content
Features
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Description
The CDP1824/3 and CDP1824C/3 types are high-reliability CMOS 32-word x 8-bit fully static random-access memories for use in CDP1800-series microprocessor systems. These parts are compatible with the CDP1802 microprocessor and will interface directly without additional components. The CDP1824/3 is fully decoded and does not require a pre- charge or clocking signal for proper operation. It has com- mon input and output and is operated from a single voltage supply. The MRD signal (output disable control) enables the three-state output drivers, and overrides the MWR signal. A CS input is provided for memory expansion. The CDP1824C/3 is functionally identical to the CDP1824/3. The CDP1824/3 has a recommended operating voltage range of 4V to 10.5V, and the CDP1824C/3 has an operating voltage range of 4V to 6.5V.
Ordering Information
AGE TEMP. RANGE PKG. NO. CDP1824CD3 CDP1824D3 SBDIP -55 oC to +125oC D18.3 Pinout CDP1824/3, CDP1824C/3 (SBDIP) TOP VIEW Functional Diagram
1 VDD
V SS MA4 MA3 MA2 MA1 MA0 MWR CS VDD = 18 VSS = 9 BUS BUS BUS BUS BUS BUS BUS BUS MRD 6 7 8 1 01 11 21 31 4 ADDRESS DECODER
32 X 8-BIT
FUNCTION CS MRD MWR DATA PINS STATUS READ 0 0 X Output: High/Low Dependent on Data WRITE 0 1 0 Input: Output Disabled Not Selected 1 X X Output Disabled: High-Impedance State Standby 0 1 1 Output Disabled: High-Impedance State Logic 1 = High Logic 0 = Low X = Don’t Care March 1997 CDP1824/3, CDP1824C/3 High-Reliability CMOS 32-Word x 8-Bit Static Random-Access Memory File Number 1717.2CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001. All Rights Reserved
Absolute Maximum Ratings Thermal Information DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W) Device Dissipation Per Output Transistor TA = Full Package Temperature Range Operating Temperature Range (TA) Lead Temperature (During Soldering) At distance 1/16± 1/32 In. (1.59 ± 0.79mm) Recommended Operating Conditions TA = Full Package-Temperature Range. For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges: PARAMETER LIMITS UNITS CDP1824/3 CDP1824C/3 MIN MAX MIN MAX DC Operating Voltage Range 4 10.5 4 6.5 V Input Voltage Range V SS VDD VSS VDD V Static Electrical Specifications PARAMETER SYMBOL CONDITIONS LIMITS UNITS VO (V) VIN (V) VDD (V) -55oC, +25oC+ 1 2 5 oC MIN MAX MIN MAX Quiescent Device Current (Note 1) IDD -0 , 5 5 - 5 0 -5 0 0 µA - 0, 10 10 - 500 - 1000 µA Output Voltage Low-Level (Note 2) VOL - 0, 5 5 - 0.1 - 0.2 V - 10 - 0.1 - 0.2 V Output Voltage High-Level (Note 2) VOH - 0, 5 5 4.9 - 4.8 - V Input Low Voltage V IL 0.5, 4.5 - 5 - 1.5 - 1.5 V Input High Voltage V IH 0.5, 4.5 - 5 3.5 - 3.5 - V 1, 9 - 10 7 - 7 - V Output Low Drive (Sink) Current IOL 0.4 0, 5 5 4 - 1.5 - mA 0.5 0, 10 10 4 - 2.9 - mA Output High Drive (Source) Current IOH 4.6 0, 5 5 - -1 - -0.75 mA Input Current I IN Any Input 0, 10 10 - ±1 - ±5 µA Three-State Output Leakage Current IOUT 0, 5 0, 5 5 - ±2 - ±5 µA 0, 10 0, 10 10 - ±2 - ±5 µA Input Capacitance C IN (Note 2) - 10 - 10 pF Output Capacitance C OUT (Note 2) - 15 - 15 pF NOTES: 1. The CDP1824C/3 meets all 5V Static Electrical Characteristics of the CDP1824/3 except Quiescent Device Current for which the limits are IDD = 200µA at +25oC/-55oC; IDD = 1000µA at +125oC. 2. Guaranteed, but not tested. CDP1824/3, CDP1824C/3
- Minimum timing for valid data output longer times will initiate an earlier, but invalid output.
FIGURE 1. READ CYCLE TIMING DIAGRAM
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- Time required by a device to allow for the indicated function.
FIGURE 2. WRITE CYCLE TIMING DIAGRAM
FIGURE 3. LOW V DD DATA RETENTION WAVEFORMS AND TIMING DIAGRAM