CDP1822_1 INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- Low Operating Current
- Industry Standard Pinout
- Two Chip-Select Inputs-Simple Memory Expansion
- Memory Retention for Standby Battery Voltage of 2V Minimum
- Output-Disable for Common I/O Systems
- Three-State Data Output for Bus-Oriented Systems
- Separate Data Inputs and Outputs
Description
The CDP1822 and CDP1822C are 256-word by 4-bit static random-access memories designed for use in memory sys- tems where high speed, low operating current, and simplicity in use are desirable. The CDP1822 features high speed and a wide operating voltage range. Both types have separate data inputs and outputs and utilize single power supplies of 4V to 6.5V for the CDP1822C and 4V to 10.5V for the CDP1822. Two Chip-Select inputs are provided to simplify system expansion. An Output Disable control provides Wire-OR capability and is also useful in common Input/Output sys- tems. The Output Disable input allows these RAMs to be used in common data Input/Output systems by forcing the output into a high-impedance state during a write operation independent of the Chip-Select input condition. The output assumes a high-impedance state when the Output Disable is at high level or when the chip is deselected by CS1 and/or CS2. The high noise immunity of the CMOS technology is pre- served in this design. For TTL interfacing at 5V operation, excellent system noise margin is preserved by using an external pull-up resistor at each input. Pinout CDP1822, CDP1822C (PDIP, SBDIP) TOP VIEW
Ordering Information
5V 10V PACKAGE TEMP. RANGE PKG. NO. CDP1822CE CDP1822E PDIP -40 oC to +85oC E22.4 CDP1822CEX CDP1822EX Burn-In E22.4 CDP1822CD CDP1822D SBDIP -40 oC to +85oC D22.4A CDP1822CDX - Burn-In D22.4A DI1 VSS DO1 DI2 CS1 O. D. CS2 R/W DO4 DI4 DO3 DI3 DO2 A3 V DD OPERATIONAL MODES MODE INPUTS OUTPUT CHIP SELECT (CS1) CHIP SELECT (CS2) OUTPUT DISABLE (OD) READ/ WRITE (R/W) Read 0 1 0 1 Read Write 0 1 0 0 Data In Write 0 1 1 0 High Imped- ance Standby 1 X X X High Imped- ance Standby X 0 X X High Imped- ance Output Disable XX 1X H i g h Imped- ance NOTE: Logic 1 = High, Logic 0 = Low, X = Don’t Care. March 1997 CDP1822, CDP1822C 256-Word x 4-Bit LSI Static RAM File Number 1074.2 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001. All Rights Reserved
Absolute Maximum Ratings Thermal Information DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) Maximum Operating Temperature Range (T Maximum Junction Temperature Recommended Operating Conditions At TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: PARAMETER SYMBOL LIMITS UNITS CDP1822 CDP1822C MIN MAX MIN MAX DC Operating Voltage Range 4 10.5 4 6.5 V Input Voltage Range V SS VDD VSS VDD V Static Electrical Specifications At TA = -40oC to +85oC, Except as Noted PARAMETER SYMBOL CONDITIONS LIMITS UNITS VO (V) VIN (V) VDD (V) CDP1822 CDP1822C MIN (NOTE TYP MAX MIN (NOTE 1) TYP MAX Quiescent Device Current IDD -0 , 55 - - 5 0 0 - - 5 0 0 µA - 0, 10 10 - - 1000 - - - µA Output Low (Sink) Current IOL 0.4 0, 5 5 2 4 - 2 4 - mA 0.5 0, 10 10 4.5 9 - - - - mA Output High (Source) Current IOH 4.6 0, 5 5 -1 -2 - -1 -2 - mA Output Voltage Low-Level VOL - 0, 5 5 - 0 0.1 - 0 0.1 V Output Voltage High-Level VOH -0 , 554 . 9 5 -4 . 95 - V Input Low Voltage V IL 0.5, 4.5 - 5 - - 1.5 - - 1.5 V Input High Voltage V Input Leakage Current I CDP1822, CDP1822C
(Note 2) IDD1 -0 , 55 - 4 8 - 4 8 m A - 0, 10 10 - 8 16 - - - mA Three-State Output Leakage Current IOUT 0, 5 0, 5 5 - - ±5- - ±5 µA Input Capacitance C IN ----5 7 . 5 -5 7 . 5 p F Output Capacitance C OUT ---- 1 0 1 5 - 1 0 1 5 p F NOTES: 1. Typical values are for T A = +25oC and nominal VDD. 2. Outputs open circuited; Cycle time = 1 µs. Dynamic Electrical Specifications At TA + -40 to +85oC, VDD ±5%, Input tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100 pF PARAMETER TEST CONDITIONS LIMITS UNITS VDD (V) CD1822 CDP1822C (NOTE MIN (NOTE 2) TYP MAX (NOTE 1) MIN (NOTE 2) TYP MAX Read Cycle Times (Figure 1) Read Cycle t RC 54 5 0 - - 4 5 0 - - n s Access from Address t AA 5 - 250 450 - 250 450 ns 10 - 150 250 - - - ns Output Valid from Chip-Select 1t DOA1 5 - 250 450 - 250 450 ns 10 - 150 250 - - - ns Output Valid from Chip-Select 2 t DOA2 5 - 250 450 - 250 450 ns 10 - 150 250 - - - ns Output Valid from Output Disable t DOA3 5 - - 200 - - 200 ns Output Hold from Chip-Select 1t DOH1 52 0 - - 2 0 - - n s 10 20 - - - - - ns Output Hold from Chip-Select 2 t DOH2 52 0 - - 2 0 - - n s 10 20 - - - - - ns Output Hold from Output Disable t DOH3 52 0 - - 2 0 - - n s 10 20 - - - - - ns Static Electrical Specifications At TA = -40oC to +85oC, Except as Noted (Continued) PARAMETER SYMBOL CONDITIONS LIMITS UNITS VO (V) VIN (V) VDD (V) CDP1822 CDP1822C MIN (NOTE TYP MAX MIN (NOTE 1) TYP MAX CDP1822, CDP1822C
- Time required by a limit device to allow for indicated function.
FIGURE 1. READ CYCLE TIMING WAVEFORMS
Input Data Setup Time t DS 5 250 - - 250 - - ns Data Hold t DH 5 5 0 - -5 0 - -n s 10 40 - - - - - ns Chip-Select 1 Setup t CS1S 5 200 - - 200 - - ns Chip-Select 2 Setup t CS2S 5 200 - - 200 - - ns Chip-Select 1 Hold t CS1H 50 - - 0 - - n s 10 0 - - 0 - - ns Chip-Select 2 Hold t CS2H 50 - - 0 - - n s 10 0 - - 0 - - ns Output Disable Set-Up t ODS 5 200 - - 200 - - ns NOTES: 1. Time required by a limit device to allow for indicated function. 2. Typical values are for T A = 25oC and nominal VDD. Dynamic Electrical Specifications At TA + -40 to +85oC, VDD ±5%, Input tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100 pF. (Continued) PARAMETER TEST CONDITIONS LIMITS UNITS CD1822 CDP1822C VDD (V) (NOTE MIN (NOTE 2) TYP MAX (NOTE 1) MIN (NOTE 2) TYP MAX CDP1822, CDP1822C
NOTE: t ODS is required for common I/O operation only. For separate I/O operations, output disable is don’t care. FIGURE 2. WRITE CYCLE TIME WAVEFORMS
Data Retention Specifications At TA = -40 to +85oC, see Figure 3. NOTE: Typical values are for T A = 25oC and nominal VDD. FIGURE 3. LOW V DD DATA RETENTION TIME WAVEFORMS FIGURE 4. MEMORY CELL CONFIGURATION
0.95 VDD
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19 CONTROL
22 VDD
FIGURE 5. FUNCTIONAL BLOCK DIAGRAM FOR CDP1822 AND CDP1822C
FIGURE 6. LOGIC DIAGRAM OF CONTROLS FOR CDP1822 AND CDP1822C