CDP1821C INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Static CMOS Silicon-On-Sapphire Circuitry CD4000- Series Compatible
  • Compatible with CDP1800-Series Microprocessors at Maximum Speed
  • Single Voltage Supply
  • No Precharge or External Clocks Required
  • Low Quiescent and Operating Power
  • Separate Data Inputs and Outputs DD
  • Memory Retention for Standby Battery Voltage Down to 2V at +25oC
  • Latch-Up-Free Transient-Radiation Tolerance

Description

The CDP1821C/3 is a 1024-word x 1-bit CMOS silicon-on-sap- phire (SOS), fully static, random-access memory designed for use in CDP1800 microprocessor systems. This device has a recommended operating voltage range of 4V to 6.5V. The output state of the CDP1821C/3 is a function of the input address and chip-select states only. Valid data will appear at the output in one access time following the latest address change to a selected chip. After valid data appears, the address may be changed immediately. It is not neces- sary to clock the chip-select input or any other input terminal for fully static operation; therefore the chip-select input may be used as an additional address input. When the device is in an unselected state ( CS = 1), the internal write circuitry and output sense amplifier are disabled. This feature allows the three-state data outputs from many arrays to be OR-tied to a common bus for easy memory expansion. Pinout CDP1821C/3 (SBDIP) TOP VIEW

Ordering Information

PACKAGE TEMP. RANGE PART NUMBER PKG. NO. SBDIP -55 oC to +125oC CDP1821CD3 D16.3 CS V SS DO VDD RD/WR DI File Number 2983.1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

COL. 0 COL. 31 COL. 0 COL. 31 CS • R/W • A4 CS • R/W • A4 CS R/W DI DI ROW DECODER ROW DECODER VDD VSS DO OPERATIONAL MODES MODE INPUTS OUTPUT READ/WRITE R/W CHIP-SELECT CS DATA OUTPUT DO Standby X 1 High Impedance Write 0 0 High Impedance Read 1 0 Contents of Addressed Call X = Don’t Care Logic 1 = High Logic 0 = Low CDP1821C/3

Absolute Maximum Ratings Thermal Information DC Supply Voltage Range, (VDD ) Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) Maximum Operating Temperature Range (TA) . . . .-55oC to +125oC Maximum Storage Temperature Range (TSTG ) . . .-65oC to +150oC Recommended Operating Conditions TA = Full Package-Temperature Range. For maximum reliability, nominal operating con- ditions should be selected so that operation is always within the following ranges: PARAMETER CDP1821CD/3 UNITSMIN MAX DC Operating Voltage Range 4 6.5 V Input Voltage Range V SS VDD V Static Electrical SpecificationsVDD = 5V ±5% PARAMETER SYMBOL CONDITIONS -55oC, +25oC +125 oC UNITSMIN MAX MIN MAX Quiescent Device Current (Note 1) I DD VIN = 0V or VDD - 260 - 1000 µA Output Low Drive (Sink) Current (Note 1) IOL VOUT = 0.4V 2.7 - 1.6 - mA Output High Drive (Source) Current (Note 1) IOH VOUT = VDD -0.4V -1.3 - -0.8 - mA Output Voltage Low-Level V OL - - 0.1 - 0.5 V Output Voltage High-Level V OH -V DD -0.1 - V DD -0.5 - V Input Low Voltage V IL - - 0.3 V DD - 0.3 V DD V Input High Voltage V IH - 0.7 V DD - 0.7 V DD -V Input Current (Note 1) I IN VIN = 0V or VDD - 2.6 - 10 µA Three-State Output Leakage Current (Note 1) IOUT VIN = 0V or VDD - 2.6 - 10 µA Operating Current (Note 2) I DD1 - - 5 - 10 mA Input Capacitance C IN - - 7.5 - 7.5 pF Output Capacitance C OUT - - 15 - 15 pF NOTES: 1. Limits designate 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing 2. Measured with 1µs read-cycle time and outputs floating. CDP1821C/3

  1. 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing.
  2. Chip-Select (CS) permitted to change from high to low level or remain low on a selected device.
  3. Chip-Select (CS) permitted to change from low to high level or remain low.
  4. Read/Write (R/W) must be at a high level during all address transitions.
  5. Data-Out (DO) is a high impedance within t

DIS ns after the falling edge of R/W or the rising edge ofCS. FIGURE 1. READ CYCLE TIMING DIAGRAM

  1. 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing.
  2. Chip-Select (CS) permitted to change from high to low level or remain low on a selected device.
  3. Chip-Select (CS) permitted to change from low to high level or remain low.

FIGURE 2. WRITE CYCLE TIMING DIAGRAM

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

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TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 CDP1821C/3