CDP1805AC INTERSIL | Alldatasheet

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Technical content

Features

  • Instruction Time of 3.2µs, -40oC to +85oC  123 Instructions - Upwards Software Compatible With CDP1802  BCD Arithmetic Instructions  Low-Power IDLE Mode  Pin Compatible With CDP1802 Except for Terminal 16  64K-Byte Memory Address Capability  64 Bytes of On-Chip RAM  16 x 16 Matrix of On-Board Registers  On-Chip Crystal or RC Controlled Oscillator  8-Bit Counter/Timer

Description

The CDP1805AC and CDP1806AC are functional and per- formance enhancements of the CDP1802 CMOS 8-bit regis- ter-oriented microprocessor series and are designed for use in general-purpose applications. The CDP1805AC hardware enhancements include a 64- byte RAM and an 8-bit presettable down counter. The Counter/Timer which generates an internal interrupt request, can be programmed for use in timebase, event-counting, and pulse-duration measurement applications. The Counter/Timer underflow output can also be directed to the Q output terminal. The CDP1806AC hardware enhance- ments are identical to the CDP1805AC, except the CDP1806AC contains no on-chip RAM. The CDP1805AC and CDP1806AC software enhancements include 32 more instructions than the CDP1802. The 32 new software instructions add subroutine call and return capabil- ity, enhanced data transfer manipulation, Counter/Timer con- trol, improved interrupt handling, single-instruction loop counting, and BCD arithmetic. Upwards software and hardware compatibility is maintained when substituting a CDP1805AC or CDP1806AC for other CDP1800-series microprocessors. Pinout is identical except for the replacement of V CC with ME on the CDP1805AC and the replacement of VCC with VDD on the CDP1806AC. n † CDP1805AC Only

Ordering Information

CDP1805AC CDP1806AC TEMPERATURE RANGE PACKAGE PKG. NO. CDP1805ACE CDP1806ACE -40 oC to +85oC Plastic DIP E40.6 - CDP1806ACEX Burn-In CDP1805ACQ CDP1806ACQ -40 oC to +85oC PLCC N44.65 CDP1805ACD CDP1806ACD -40 oC to +85oC SBDIP D40.6 CDP1805ACDX - Burn-In March 1997 CDP1805AC, CDP1806AC CMOS 8-Bit Microprocessor with On-Chip RAM† and Counter/Timer File Number 1370.2CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143| Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved

FIGURE 1. TYPICAL CDP1805AC, CDP1806AC SMALL MICROPROCESSOR SYSTEM

32 BYTE RAM

FIGURE 2. BLOCK DIAGRAM FOR CDP1805AC AND CDP1806AC

Absolute Maximum Ratings Thermal Information DC Supply Voltage Range, (VDD ) Thermal Resistance (Typical, Note 2)θJA (oC/W) θJC (oC/W) Device Dissipation Per Output Transistor Operating Temperature Range (TA) Lead Temperature (During Soldering) At Distance 1/16 ±1/32in (1.59 ± 0.79mm) from case for Printed Circuit Board Mount: 57mm x 57mm Minimum Area x 1.6mm Thick G10 Epoxy Glass, or Equivalent. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Recommended Operating Conditions TA = Full-Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges. PARAMETER TEST CONDITIONS VDD (V) CDP1805ACD, CDP1805ACE CDP1806ACD, CDP1806ACE UNITSMIN MAX DC Operating Voltage Range - 4 6.5 V Input Voltage Range - V SS VDD V Minimum Instruction Time (Note 1) (fCL = 5MHz) 53 . 2 - µs Maximum DMA Transfer Rate 5 - 0.625 Mbyte/s Maximum Clock Input Frequency, Load Capacitance (CL) = 50pF 5D C 5 M H z Maximum External Counter/Timer Clock Input Frequency to EF1, EF2 5D C 2 M H z NOTES: 1. Equals 2 machine cycles - one Fetch and one Execute operation for all instructions except Long Branch, Long Skip, NOP, and “68” family instructions, which are more than two cycles. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Static Electrical Specificationsat TA = -40oC to +85oC, VDD ±5%, Except as Noted PARAMETER VO (V) VIN (V) VDD (V) CDP1805ACD, CDP1805ACE CDP1806ACD, CDP1806ACE UNITSMIN (NOTE 3) TYP MAX Quiescent Device Current, IDD - 0, 5 5 - 50 200 µA Output Low Drive (Sink) Current, (Except XTAL), IOL 0.4 0, 5 5 1.6 4 - mA XTAL Output, IOL 0.4 5 5 0.2 0.4 - mA Output High Drive (Source) Current (Except XTAL, IOH 4.6 0, 5 5 -1.6 -4 - mA XTAL , IOH 4.6 0 5 -0.1 -0.2 - mA Output Voltage Low Level, VOL -0 , 55 - 0 0 . 1 V Output Voltage High Level, VOH -0 , 55 4 . 9 5 - V CDP1805AC, CDP1806AC

Input Low Voltage (BUS0 - BUS7, ME), VIL 0.5, 4.5 - 5 - - 1.5 V Input High Voltage (BUS0 - BUS7, ME), VIH 0.5, 4.5 - 5 3.5 - - V Schmitt Trigger Input Voltage (Except BUS0 - BUS7, ME) Input Leakage Current, IIN -0 , 55 - ±0.1 ±5 µA Three-State Output Leakage Current, IOUT 0, 5 0, 5 5 - ±0.2 ±5 µA Input Capacitance, CIN --- - 5 7 . 5 p F Output Capacitance, COUT --- - 1 0 1 5 p F Total Power Dissipation (Note 4) Run - - 5 - 35 50 mW Idle “00” at M (0000) - - 5 - 12 18 mW Minimum Data Retention Voltage, VDR VDD = VDR -2 2 . 4 V Data Retention Current, IDR VDD = 2.4 - 25 100 µA NOTES: 3. Typical values are for TA = +25oC and nominal VDD . 4. External clock: f = 5MHz, tR , tF = 10ns; CL = 50pF. Dynamic Electrical Specificationsat TA = -40o to +85oC; CL = 50pF; Input tR , tF = 10ns; Input Pulse Levels = 0.1V to V DD -0.1V; VDD = 5V, ±5%. PARAMETER CDP1805AC CDP1806AC UNITS (NOTE 5) TYP MAX Propagation Delay Times Clock to TPA, TPB, tPLH , tPHL 150 275 ns Clock-to-Memory High-Address Byte, tPLH , tPHL 325 550 ns Clock-to-Memory Low-Address Byte, tPLH , tPHL 275 450 ns Clock to MRD, tPLH , tPHL 200 325 ns Clock to MWR, tPLH , tPHL (See Note 5) 150 275 ns Clock to (CPU DATA to BUS), tPLH , tPHL 375 625 ns Clock to State Code, tPLH , tPHL 225 400 ns Clock to Q, tPLH , tPHL 250 425 ns Clock to N, tPLH , tPHL 250 425 ns Clock to Internal RAM Data to BUS, tPLH , tPHL 420 650 ns Static Electrical Specificationsat TA = -40oC to +85oC, VDD ±5%, Except as Noted (Continued) PARAMETER VO (V) VIN (V) VDD (V) CDP1805ACD, CDP1805ACE CDP1806ACD, CDP1806ACE UNITSMIN (NOTE 3) TYP MAX CDP1805AC, CDP1806AC

Minimum Set-Up And Hold Times (Note 2) Data Bus Input Set-Up, tSU -100 0 ns Data Bus Input Hold, tH 125 225 ns DMA Set-Up, tSU -75 0 ns DMA Hold, tH 100 175 ns ME Set-Up, tSU 125 320 ns ME Hold, tH 05 0 n s Interrupt Set-Up, tSU -100 0 ns Interrupt Hold, tH 100 175 ns WAIT Set-Up, tSU 20 50 ns EF1-4 Set-Up, tSU -125 0 ns EF1 -4 Hold, tH 175 300 ns Minimum Pulse Width Times (Note 6) CLEAR Pulse Width, tWL 100 175 ns CLOCK Pulse Width, tW 75 100 ns NOTES: 5. Typical values are for TA = 25o C and nominal VDD . 6. Maximum limits of minimum characteristics are the values above which all devices function. Timing Specificationsas a function of T (T = 1/fCLOCK ) at TA = -40 to +85oC, VDD = 5V, ±15% PARAMETER CDP1805AC, CDP1806AC UNITSTYP (NOTE 7) MAX High-Order Memory-Address Byte Set-Up to TPA Time, t SU 2T-275 2T -175 ns MRD to TPA Time, t SU T/2 -100 T/2 -75 ns High-Order Memory-Address Byte Hold after TPA Time, tH T/2 +75 T/2 +100 ns Low-Order Memory-Address Byte Hold after WR Time, tH T +180 T +240 ns CPU Data to Bus Hold after WR Time, tH T +110 T +150 ns Required Memory Access Time, tACC Address to Data 4.5T -440 4.5T -330 ns NOTE: 7. Typical values are for TA = +25oC and nominal VDD . Dynamic Electrical Specificationsat TA = -40o to +85oC; CL = 50pF; Input tR , tF = 10ns; Input Pulse Levels = 0.1V to V DD -0.1V; VDD = 5V, ±5%. (Continued) PARAMETER CDP1805AC CDP1806AC UNITS (NOTE 5) TYP MAX CDP1805AC, CDP1806AC

† This Timing Diagram is used to show signal relationships only, and does not represent any specific machine cycle. † All measurements are referenced to 50% point of the wave forms. † Shaded areas indicate “don’t care” or undefined state. Multiple transitions may occur during this period. † For the run (RAM only) mode only. †† For the run (RAM/ROM) mode only. FIGURE 5. TIMING WAVEFORMS

Enhanced CDP1805AC and CDP1806AC Operation Timing Timing for the CDP1805AC and CDP1806AC is the same as the CDP1802 microprocessor series, with the following exceptions:  4.5 Clock Cycles Are Provided for Memory Access Instead of 5.  Q Changes 1/2 Clock Cycle Earlier During the SEQ and REQ Instructions.  Flag Lines (EF1-EF4) Are Sampled at the End of the S0 Cycle Instead of at the Beginning of the S1 Cycle.  Pause Can Only Occur on the Low-To-High Transition of Either TPA or TPB, Instead of any Negative Clock Transi- tion. Special Features Schmitt triggers are provided on all inputs, except ME and BUS 0-BUS 7, for maximum immunity from noise and slow signal transitions. A Schmitt Trigger in the oscillator section allows operation with an RC or crystal. The CDP1802 Series LOAD mode is not retained. This mode (WAIT , CLEAR = 0) is not allowed on the CDP1805AC and CDP1806AC. A low power mode is provided, which is initiated via the IDLE instruction. In this mode all external signals, except the oscil- lator, are stopped on the low-to-high transition of TPB. All outputs remain in their previous states, MRD is set to a logic “1”, and the data bus floats. The IDLE mode is exited by a DMA or INT condition. The INT includes both external inter- rupts and interrupts generated by the Counter/Timer. The only restrictions are that the Timer mode, which uses the TPA ÷ 32 clock source, and the underflow condition of the Pulse Width Measurement modes are not available to exit the IDLE mode. Signal Descriptions Bus 0 to Bus 7 (Data Bus) 8-Bit bidirectional DATA BUS lines. These lines are used for transferring data between the memory, the microprocessor, and I/O devices. N0 to N2 (I/O) Lines Activated by an I/O instruction to signal the I/O control logic of a data transfer between memory and I/O interface. These lines can be used to issue command codes or device selec- tion codes to the I/O devices. The N-bits are low at all times except when an I/O instruction is being executed. During this time their state is the same as the corresponding bits in the N Register. The direction of data flow is defined in the I/O instruction by bit N3 (internally) and is indicated by the level of the MRD Signal: MRD = VDD : Input data from I/O to CPU and memory. MRD = VSS : Output data from Memory to I/O. EF1 to EF4 (4 Flags) These inputs enable the I/O controllers to transfer status information to the processor. The levels can be tested by the conditional branch instructions. They can be used in con- junction with the INTERRUPT request line to establish inter- rupt priorities. The flag(s) are sampled at the end of every S0 cycle. EF1 and EF2 are also used for event counting and pulse width measurement in conjunction with the Counter/Timer. INTERRUPT , DMA-IN, DMA-OUT (3 I/O Requests) DMA-lN and DMA-OUT are sampled during TPB every S1, S2, and S3 cycle. INTERRUPT is sampled during TPB every S1 and S2 cycle. Interrupt Action - X and P are stored in T after executing current instruction; designator X is set to 2; designator P is set to 1; interrupt enable (MIE) is reset to 0 (inhibit); and instruction execution is resumed. The interrupt action requires one machine cycle (S3). DMA Action - Finish executing current instruction; R(0) points to memory area for data transfer; data is loaded into or read out of memory; and R(0) is incremented. NOTE: In the event of concurrent DMA and INTERRUPT requests, DMA-IN has priority followed by DMA-OUT and then INTERRUPT. (The interrupt request is not internally latched and must be held true after DMA). SC0, SC1, (2 State Code Lines) These outputs indicate that the CPU is: 1) fetching an instruction, or 2) executing an instruction, or 3) processing a DMA request, or 4) acknowledging an interrupt request. The levels of state code are tabulated below. All states are valid at TPA. TPA, TPB (2 Timing Pulses) Positive pulses that occurrence in each machine cycle (TPB follows TPA). They are used by I/O controllers to interpret codes and to time interaction with the data bus. The trailing edge of TPA is used by the memory system to latch the high- order byte of the multiplexed 16-bit memory address. STATE TYPE STATE CODE LINES SC1 SC0 S0 (Fetch) L L S1 (Execute) L H S2 (DMA) H L S3 (Interrupt) H H NOTE: H = V DD , L = VSS. CDP1805AC, CDP1806AC

MA0 to MA7 (8 Memory Address Lines) In each cycle, the higher-order byte of a 16-bit memory address appears on the memory address lines MA0-7 first. Those bits required by the memory system can be strobed into external address latches by timing pulse TPA. The low- order byte of the 16-bit address appears on the address lines 1/2 clock after the termination of TPA. MWR (Write Pulse) A negative pulse appearing in a memory-write cycle, after the address lines have stabilized. MRD (Read Level) A low level on MRD indicates a memory read cycle. It can be used to control three-state outputs from the addressed mem- ory and to indicate the direction of data transfer during an I/O instruction. Q Single bit output from the CPU which can be set or reset, under program control. During SEQ and REQ instruction execution, Q is set or reset between the trailing edge of TPA and the leading edge of TPB. The Q line can also be con- trolled by the Counter/Timer underflow via the Enable Toggle Q instruction. The Enable Toggle Q command connects the Q-line flip-flop to the output of the counter, such that each time the counter decrements from 01 to its next value, the Q line changes state. This command is cleared by a LOAD COUNTER (LDC) instruction with the Counter/Timer stopped, a CPU reset, or a BRANCH COUNTER INTERRUPT (BCl) instruc- tion with the counter interrupt flip-flop set. Clock Input for externally generated single-phase clock. The maxi- mum clock frequency is 5MHz at V DD = 5V. The clock is counted down internally to 8 clock pulses per machine cycle. XTAL Connection to be used with clock input terminal, for an exter- nal crystal, if the on-chip oscillator is utilized. WAIT , CLEAR (2 Control Lines) Provide four control modes as listed in the following truth table: ME (Memory Enable CDP1805AC Only) This active low input is used to select or deselect the internal RAM. It must be active prior to clock 70 for an internal RAM access to take place. Internal RAM data will appear on the data bus during the time that ME is active (after clock 31). Thus, if this data is to be latched into an external device (i.e., during an OUTPUT instruction or DMA OUT cycle), ME should be wide enough to provide enough time for valid data to be latched. The internal RAM is automatically deselected after clock 71. ME is ineffective when MRD  MWR = 1. The internal RAM is not internally mask-decoded. Decoding of the starting address is performed externally, and may reside in any 64-byte block of memory. VDD (CDP1806AC Only) This input replaces the ME signal of the CDP1805AC and must be connected to the positive power supply. VDD , VSS , (Power Levels) VSS is the most negative supply voltage terminal and is nor- mally connected to ground. VDD is the positive supply volt- age terminal. All outputs swing from VSS to VDD . The recommended input voltage swing is from VSS to VDD . Architecture Figure 2 shows a block diagram of the CDP1805AC and CDP1806AC. The principal feature of this system is a regis- ter array (R) consisting of sixteen 16-bit scratchpad regis- ters. Individual registers in the array (R) are designated (selected) by a 4-bit binary code from one of the 4-bit regis- ters labeled N, P , and X. The contents of any register can be directed to any one of the following paths: 1. The external memory (multiplexed, higher-order byte first on to 8 memory address lines). 2. The D register (either of the two bytes can be gated to D). 3. The increment/decrement circuit where it is increased or decreased by one and stored back in the selected 16-bit register. 4. To any other 16-bit scratch pad register in the array. The four paths, depending on the nature of the instruction, may operate independently or in various combinations in the same machine cycle. Most instructions consist of two 8-clock-pulse machine cycles. The first cycle is the fetch cycle, and the second, and more if necessary, are execute cycles. During the fetch cycle the four bits in the P designator select one of the 16 registers R(P) as the current program counter. The selected register R(P) contains the address of the memory location from which the instruction is to be fetched. When the instruction is read out from the memory, the higher order 4 bits of the instruction byte are loaded into the register and the lower order 4 bits into the N register. The content of the program counter is automatically incremented by one so that R(P) is now “pointing” to the next byte in the memory. CLEAR WAIT MODE L L Not Allowed L H Reset H L Pause HH R u n CDP1805AC, CDP1806AC

The X designator selects one of the 16 registers R(X) to “point” to the memory for an operand (or data) in certain ALU or I/O operations. The N designator can perform the following five functions depending on the type of instruction fetched: 1. Designate one of the 16 registers in R to be acted upon during register operations. 2. Indicate to the I/O devices a command code or device- selection code for peripherals. 3. Indicate the specific operation to be executed during the ALU instructions, types of tests to be performed during the Branch instructions, or the specific operation required in a class of miscellaneous instructions. 4. Indicate the value to be loaded into P to designate a new register to be used as the program counter R(P). 5. Indicate the value to be loaded into X to designate a new register to be used as data pointer R(X). The registers in R can be assigned by a programmer in three different ways as program counters, as data pointers, or as scratchpad locations (data registers) to hold two bytes of data. Program Counters Any register can be the main program counter; the address of the selected register is held in the P designator. Other reg- isters in R can be used as subroutine program counters. By a single instruction the contents of the P register can be changed to effect a “call” to subroutine. When interrupts are being serviced, register R(1) is used as the program counter for the user's interrupt servicing routine. After reset, and dur- ing a DMA operation, R(0) is used as the program counter. At all other times the register designated as program counter is at the discretion of the user. Data Pointers The registers in R may be used as data pointers to indicate a location in memory. The register designated by X (i.e., R(X)) points to memory for the following instructions (see Table 1): 1. ALU operations. 2. Output instructions. 3. Input instructions. 4. Register to memory transfer. 5. Memory to register transfer. 6. Interrupt and subroutine handling. The register designated by N (i.e., R(N)) points to memory for the “load D from memory” instructions ON and 4N and the “Store D” instruction 5N. The register designated by P (i.e., the program counter) is used as the data pointer for ALU instructions F8-FD, FF, 7C, 7D, 7F, and the RLDl instruction 68CN. During these instruction executions, the operation is referred to as “data immediate”. Another important use of R as a data pointer supports the built-in Direct-Memory-Access (DMA) function. When a DMA-ln or DMA-Out request is received, one machine cycle is “stolen”. This operation occurs at the end of the execute machine cycle in the current instruction. Register R(0) is always used as the data pointer during the DMA operation. The data is read from (DMA-Out) or written into (DMA-ln) the memory location pointed to by the R(0) register. At the end of the transfer, R(0) is incremented by one so that the pro- cessor is ready to act upon the next DMA byte transfer request. This feature in the CDP1805AC and CDP1806AC architecture saves a substantial amount of logic when fast exchanges of blocks of data are required, such as with mag- netic discs or during CRT-display-refresh cycles. Data Registers When registers in R are used to store bytes of data, instruc- tions are provided which allow D to receive from or write into either the higher-order- or lower-order-byte portions of the register designated by N. By this mechanism (together with loading by data immediate) program pointer and data pointer designations are initialized. Also, this technique allows scratchpad registers in R to be used to hold general data. By employing increment or decrement instructions, such regis- ters may be used as loop counters. The new RLDl, RLXA, RSXD, and RNX instructions also allow loading, storing, and exchanging the full 16-Bit contents of the R registers without affecting the D register. The new DBNZ instruction allows decrementing and branching-on-not-zero of any 16-Bit R register also without affecting the D register. The Q Flip-Flop An internal flip-flop, Q, can be set or reset by instruction and can be sensed by conditional branch instructions. It can also be driven by the underflow output of the counter/timer The output of Q is also available as a microprocessor output. REGISTER SUMMARY D 8 Bits Data Register (Accumulator) DF 1-Bit Data Flag (ALU Carry) B 8 Bits Auxiliary Holding Register R 16 Bits 1 of 16 Scratch and Registers P 4 Bits Designates which Register is Program Counter X 4 Bits Designates which Register is Data Pointer N 4 Bits Holds Low-Order Instr. Digit I 4 Bits Holds High-Order Instr. Digit T 8 Bits Holds old X, P after Interrupt (X is high nibble) Q 1-Bit Output Flip-Flop CNTR 8-Bits Counter/Timer CH 8 Bits Holds Counter Jam Value MIE 1-Bit Master Interrupt Enable ClE 1-Bit Counter Interrupt Enable XlE 1-Bit External Interrupt Enable ClL 1-Bit Counter Interrupt Latch CDP1805AC, CDP1806AC

Register R(1) is always used as the program counter when- ever interrupt servicing is initialized. When an interrupt request occurs and the interrupt is allowed by the program (again, nothing takes place until the completion of the cur- rent instruction), the contents of the X and P registers are stored in the temporary Register T, and X and P are set to new values; hex digit 2 in X and hex digit 1 in P . Master Inter- rupt Enable is automatically deactivated to inhibit further interrupts. The user’s interrupt routine is now in control; the contents of T may be saved by means of a single SAV instruction (78) in the memory location pointed to by R(X) or the contents of T, D, and DF may be saved using a single DSAV instruction (6876). At the conclusion of the interrupt, the user's routine may restore the pre-interrupted value of X and P with either a RET instruction (70) which permits fur- ther interrupts, or a DlS instruction (71), which disables fur- ther interrupts. Interrupt Generation and Arbitration (See Figure 6) Interrupt requests can be generated from the following sources: 1. Externally through the interrupt input (request not latched). 2. Internally due to Counter/Timer response (request is latched). a. On the transition from count (01)16 to its next value (counter underflow). b. On the transition of EF1 in pulse measurement mode 1. c. On the transition of EF2 in pulse measurement mode 2. For an interrupt to be serviced by the CPU, the appropriate Interrupt Enable flip-flops must be set. Thus, the External Interrupt Enable flip-flop must be set to service an external interrupt request, and the Counter Interrupt Enable flip-flop must be set to service an internal Counter/Timer interrupt request. In addition, the Master interrupt Enable flip-flop (as used in the CDP1802) must be set to service either type of request. All 3 flip-flops are initially enabled with the applica- tion of a hardware reset, and, can be selectively enabled or disabled with software: ClE, ClD instructions for the ClE flip- flop; XlE, XlD instructions for the XIE flip-flop; RET, DIS instructions for the MIE flip flop. Short branch instructions on Counter Interrupt (BCI) and External Interrupt (BXl) can be placed in the user's interrupt service routine to provide a means of identifying and priori- tizing the interrupt source. Note, however, that since the External Interrupt request is not latched, it must remain active until the short branch is executed if this priority arbitra- tion scheme is used. Interrupt requests can also be polled if automatic interrupt service is not desired (MlE = 0). With the Counter Interrupt and External Interrupt short branch instructions, the branch will be taken if an interrupt request is pending, regardless of the state of any of the 3 Interrupt Enable flip-flops. The latched counter interrupt request signal will be reset when the branch is taken, when the CPU is reset, or with a LDC instruction with the Counter stopped. Note, that exiting a counter-initiated interrupt routine without resetting the counter-interrupt latch will result in immediately reentering the interrupt routine. Counter/Timer and Controls (See Figure 7) This logic consists of a presettable 8-Bit down-counter (Mod- ulo N type), and a conditional divide-by-32 prescaler. After counting down to (01) 16the counter returns to its initial value at the next count and sets the Counter Interrupt Latch. It will continue decrementing on subsequent counts. If the counter is preset to (00)16 full 256 counts will occur. During a Load Counter instruction (LDC) if the counter was stopped with a STPC Instruction, the counter and its holding register (CH) are loaded with the value in the D Register and any previous counter interrupt is cleared. If the LDC is exe- cuted when the counter is running, the contents of the D Register are loaded into the holding register (CH) only and any previous counter interrupt is not cleared. (LDC RESETS the Counter Interrupt Latch only when the Counter is stopped). After counting down to (01) 16 the next count will load the new initial value into the counter, set the Counter Interrupt Latch, and operation will continue. CDP1805AC, CDP1806AC

  1. Event Counter 1: Input to counter is connected to the EF1
  2. Event Counter 2: Input to counter is connected to the EF2
  3. Timer: Input to counter is from the divide by 32 prescaler

Timer mode, system RESET, or stopped by a STPC.

  1. Pulse Duration Measurement 1: Input to counter con-
  2. Pulse Duration Measurement 2: Operation is identical to

not exclude testing these flags for branch instructions. mode has been cleared by a Stop Counter instruction. stopped, system Reset, or a BCl with Cl = 1. can SET or RESET Q while the Counter is running. FIGURE 6. INTERRUPT LOGIC CONTROL DIAGRAM

mately 1/RC (see Figure 10). FIGURE 7. TIMER/COUNTER DIAGRAM †Pin numbers refer to 40 pin DIP. FIGURE 8. TYPICAL 5MHz CRYSTAL OSCILLATOR †Pin numbers refer to 40 pin DIP. FIGURE 9. RC NETWORK FOR OSCILLATOR FIGURE 10. NOMINAL COMPONEN T VALUES AS A FUNCTION

11 M 10 100 1K 10K 100K

counter mode is cleared, and ETQ is disabled. X, P, RO ← 0 (X, P , and RO are cleared). as to preclude interrupts until ready for them. remain at their previous state (see Figure 12). ate Setup and Hold times must be met. requires DMA, INTERRUPT or RESET to resume execution. cycle or fetch (S0) from location 0000 in memory. (see Figure 8 and Figure 9). FIGURE 11. RESET/RUN DIAGRAM

bit (LSB) to the most significant bit (MSB) starting with 0. loaded into D, and R(N) is incremented by 1. TABLE 1. INSTRUCTION SUMMARY (SEE NOTES)

5 RLXA 686N

5 RSXD 68AN

5 DBNZ 682N R(N) - 1 → R(N); IF R(N) NOT 0,

4 RNX 68BN

4 DACI 687C M(R(P)) + D + DF → DF, D;

2 SDBI 7D M(R(P)) - D - (NOT DF) → DF, D;

4 DSMI 68FF D - M(R(P)) → DF, D;

2 SMB 77 D - M(R(X)) - (NOT DF) → DF, D

4 DSMB 6877 D - M(R(X)) - (NOT DF) → DF, D;

2 SMBI 7F D - M(R(P)) - (NOT DF) → DF, D;

TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued)

4 DSBI 687F D - M(R(P)) - (NOT DF) → DF, D

3 BCI 683E

TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued)

TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued)

3 SCM1 6805 EF1

3 SCM2 6803 EF2 → CNTR CLOCK

TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued)

  1. Previous contents of T register are destroyed during instruction execution.
  2. This instruction is associated with more than one mnemonic. Each mnemonic is individually listed.
  3. ETQ cleared by LDC with the Counter/Timer stopped, reset of CPU, or BCl  (Cl = 1).
  4. Cl = Counter Interrupt, Xl = External Interrupt.
  5. An IDLE instruction initiates an S1 cycle. All external signals, except the oscillator, are stopped on the low-to-high transition of TPB. All

ClE or XlE must be enabled).

  1. Long-Branch, Long-Skip and No Op instructions require three cycles to complete (1 fetch + 2 execute).

current program counter, respectively. This operation effects a branch to any memory location. cuted. This operation is taken for the case of unconditional no branch (NLBR). TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued)

  1. The short-branch instructions are two or three bytes long. The first byte specifies the condition to be tested, and the second specifies the branching address, except for the branches on interrupt. For those, the first two bytes specify the condition to be tested and the third byte specifies the branching address. The short branch instruction can: a. Branch unconditionally b. Test for D = 0 or D ≠ 0 c. Test for DF = 0 or DF = 1 d. Test for Q = 0 or Q = 1 e. Test the status (1 or 0) of the four EF flags f. Effect an unconditional no branch g. Test for counter or external interrupts (BCI, BXI) If the tested condition is met, then branching takes place; the branching address byte is loaded into the low-order byte position of the current program counter. This effects a branch within the current 256-byte page of the memory, i.e., the page which holds the branching address. If the tested condition is not met, the branching address byte is skipped over, and the next instruction in sequence is fetched and executed. This same action is taken in the case of unconditional no branch (NBR). 17. The skip instructions are one byte long. There is one Unconditional Short-Skip (SKP) and eight Long-Skip instructions. The Unconditional Short-Skip instruction takes 2 cycles to complete (1 fetch + 1 execute). Its action is to skip over the byte following it. Then the next instruction in sequence is fetched and executed. This SKP instruction is identical to the unconditional No-Branch Instruc- tion (NBR) except that the skipped-over byte is not considered part of the program. The Long-Skip instructions take three cycles to complete (1 fetch + 2 execute). They can: a. Skip unconditionally b. Test for D = 0 or D ≠ 0 c. Test for DF = 0 or DF = 1 d. Test for Q = 0 or Q = 1 e. Test for MIE = 1 If the tested condition is met, then Long Skip takes place; the current program counter is incremented twice. Thus, two bytes are skipped over and the next instruction in sequence is fetched and executed. If the tested condition is not met, then no action is taken. Execution is continued by fetching the next instruction in sequence. 18. Instruction 6800 through 68FF take a minimum of 3 machine cycles and up to a maximum of 10 machine cycles. In all cases, the first two cycles are fetches and subsequent cycles are executes. The first byte (68) of these two-byte op codes is used to generate the second fetch, the second byte is then interpreted differently than the same code without the 68 prefix. DMA and INT requests are not serviced until the end of the last execute cycle. 19. Arithmetic Operations: The arithmetic and shift operations are the only instructions that can alter the content of DF. The syntax ‘(NOT DF)’ denotes the subtrac- tion of the borrow. Binary Operations: After an ADD instruction DF = 1 denotes a carry has occurred. Result is greater than FF 16. DF = 0 denotes a carry has not occurred. After a SUBTRACT instruction DF = 1 denotes no borrow. D is a true positive number. DF = 0 denotes a borrow. D is in two's complement form. Binary Coded Decimal Operations: After a BCD ADD instruction DF = 1 denotes a carry has occurred. Result is greater than 9910. DF = 0 denotes a carry has not occurred. After a BCD SUBTRACT instruction DF = 1 denotes no borrow. D is a true positive decimal number. Example 99 D -88 M(R(X))

11 D DF = 1

DF = 0 denotes a borrow. D is in ten's complement form. Example 88 D -99 M(R(X))

89 D DF = 0

89 is the ten's complement of 11, which is the correct answer (with a minus value denoted by DF = 0). CDP1805AC, CDP1806AC

TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES

00 UNDE-

TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued)

TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued)

TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued)

  1. Data bus floats for first 2-1/2 clocks of the nine clock initialization cycle; all zeros for remainder of cycle.

TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued)

N 0123456789AB C D EF 0I D L L D N 1I N C

2 D E C

3 BR BQ BZ BDF B1 B2 B3 B4 SKP BNQ BNZ BNF BN1 BN2 BN3 BN4

4 L D A

6I R X O U T † INP

7 RET DIS LDXA STXD ADC SDB SHRC SMB SAV MARK REQ SEQ ADCI SDBI SHLC SMBI

8 G L O

9 G H I

C LBR LBQ LBZ LBDF NOP LSNQ LSNZ LSNF LSKP LBNQ LBNZ LBNF LSIE LSQ LSZ LSDF DS E P ES E X F LDX OR AND XOR ADD SD SHR SM LDI ORI ANI XRI ADI SDI SHL SMI ‘68’ LINKED OPCODES (DOUBLE FETCH)

0 STPC DTC SPM2 SCM2 SPM1 SCM1 LDC STM GEC ETQ XIE XID CIE CID - -

7---- D A D C - D S A V D S M B ---- D A C I -- D S B I 8S C A L 9S R E T AR S X D B RNX CR L D I F ---- D A D D -- D S M ---- D A D I -- D S M I †‘68’ is used as a linking OPCODE for the double fetch instructions. CDP1805AC, CDP1806AC

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