CDP1802AC3 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

For Use In Aerospace, Military, and Critical Industrial Equipment

  • Minimum Instruction Fetch -Execute Time of 4.5µs (Maximum Clock Frequency of 3.6MHz) at VDD =5 V , TA = +25°C
  • Operation Over the Full Military
  • Any Combination of Standard RAM and ROM Up to 65,536 Bytes
  • 8-Bit Parallel Organization With Bi-directional Data Bus and Multiplexed Address Bus
  • 16x16 Matrix of Registers for Use as Multiple Program Counters, Data Pointers, or Data Registers
  • On-Chip DMA, Interrupt, and Flag Inputs DD
  • Pb-Free (RoHS compliant)

Ordering Information

TEMP. RANGE (°C) CLOCK FREQUENCY AT 5V PACKAGE PKG DWG. # CDP1802ACD3 CDP1802ACD3 -55 to +125 Up to 3.2MHz 40 Ld SBDIP D40.6 NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. FN1441.3Data Sheet October 17, 2008 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

32 BYTE RAM

FIGURE 1. TYPICAL CDP1802A/3 SMALL MICROPROCESSOR SYSTEM

3 FN1441.3 October 17, 2008 CPU Block Diagram MUX MA7 MA5 MA3 MA1 MA0MA2MA4MA6 MEMORY ADDRESS LINES I/O FLAGS ALU B D DF INCR/ DECR A R(0).1 R(0).0 R(1).0R(1).1 R(2).1 R(2).0 R(9).0 R(A).0R(A).1 R(9).1 R(E).1 R(F).1 R(F).0 R(E).0 REGISTER ARRAY 8-BIT BIDIRECTIONAL DATA BUS LATCH AND DECODE R XTP I N N1 I/O COMMANDS BUS 0 BUS 1 BUS 2 BUS 3 BUS 4 BUS 5 BUS 6 BUS 7 TO INSTRUCTION DECODE CONTROL AND TIMING LOGIC CLOCK LOGIC I/O REQUESTS CONTROL EF1 EF3 EF2 EF4 DMA OUT DMA IN INT CLEAR WAIT CLOCK XTAL SCO SCI Q LOGIC TPA TPB MWR MRD SYSTEM STATE CODES TIMING CDP1802AC/3CDP1802AC/3

4 FN1441.3 October 17, 2008 Absolute Maximum Ratings Thermal Information DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W) Device Dissipation Per Output Transistor Operating Temperature Range (TA) Lead Temperature (During Soldering) At distance 1/16 ± 1/32 In. (1.59 ±0.79mm) http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Recommended Operating Conditions TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER MIN MAX UNITS DC Operating Voltage Range 4 6.5 V Input Voltage Range V SS VDD V Maximum Clock Input Rise or Fall Time - 1 µs Performance Specifications Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER VDD (V) -55°C TO +25°C +125°C UNITS Minimum Instruction Time (Note 3) 5 4.5 5.9 µs Maximum DMA Transfer Rate 5 450 340 Kbytes/s Maximum Clock Input Frequency, Load Capacitance (C L) = 50pF, fCL 5 DC-3.6 DC-2.7 MHz NOTE: 3. Equals 2 machine cycles - one Fetch and one Execute operation for all instructions except Long Branch and Long Skip, which require 3 machine cycles - one Fetch and two Execute operations. Static Electrical Specifications All Limits are 100% Tested. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER CONDITIONS -55°C, +25°C +125°C UNITS VOUT (V) VIN, (V) VCC, VDD (V) (Note 4) MIN MAX MIN MAX Quiescent Device Current, IDD - - 5 - 100 - 250 µA Output Low Drive (Sink) Current (Except XTAL), IOL 0.4 0, 5 5 1.20 - 0.90 - mA XTAL 0.4 5 5 185 - 140 - µA Output High Drive (Source) Current (Except XTAL), IOH 4.6 0, 5 5 - -0.30 - -0.20 mA XTAL 4.6 0 5 - -135 - -100 µA Output Voltage Low-Level, VOL - 0, 5 5 - 0.1 - 0.2 V CDP1802AC/3CDP1802AC/3

5 FN1441.3 October 17, 2008 Output Voltage High-Level, VOH - 0, 5 5 4.9 - 4.8 - V Input Low Voltage, VIL 0.5, 4.5 - 5 - 1.5 - 1.5 V Input High Voltage, VIH 0.5, 4.5 - 5 3.5 - 3.5 - V Input Leakage Current, IIN Any Input Three-State Output Leakage Current, IOUT 0, 5 0, 5 5 - ±1 - ±5 µA NOTE: 4. 5V level characteristics apply to Part No. CDP1802AC/3, and 5V and 10V level characteristics apply to part No. CDP1802A/3. Timing Specifications As a Function of T (T = 1/fCLOCK), CL = 50 pF. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER VDD (V) LIMITS (Note 5) UNITS-55°C, +25°C +125°C High-Order Memory-Address Byte Setup to TPA Time, t SU 5 2T-450 2T-580 ns High-Order Memory-Address Byte Hold After TPA Time, tH 5 T/2 +0 T/2 +0 ns Low-Order Memory-Address Byte Hold After WR Time, tH 5T - 3 0 T - 4 0 n s CPU Data to Bus Hold After WR Time, tH 5 T-170 T-250 ns Required Memory Access Time Address to Data, tACC 5 5T-300 5T-400 ns NOTE: 5. These limits are not directly tested. Implicit Specifications (Note 6) TA = -55°C to +25°C. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER SYMBOL VDD (V) TYPICAL VALUES UNITS Typical Total Power Dissipation Idle “00” at M(0000), CL = 50pF f = 2MHz - 5 4 mW Effective Input Capacitance any Input - C IN -5 p F Effective Three-State Terminal Capacitance Data Bus - - - 7.5 pF Minimum Data Retention Voltage - V DR -2 . 4 V Data Retention Current - I DR 2.4 10 µA NOTE: 6. These specifications are not tested. Ty pical values are provided for guidance only. Static Electrical Specifications All Limits are 100% Tested. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER CONDITIONS -55°C, +25°C +125°C UNITS VOUT (V) VIN, (V) VCC, VDD (V) (Note 4) MIN MAX MIN MAX CDP1802AC/3CDP1802AC/3

6 FN1441.3 October 17, 2008 Dynamic Electrical Specifications CL = 50pF, Timing Measurement at 0.5 VDD Point. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETERS VDD (V) UNITSMIN MAX MIN MAX PROGAGATION DELAY TIMES, tPLH, tPHL Clock to TPA, TPB 5 - 275 - 370 ns Clock-to-Memory High Address Byte, tPLH, tPHL 5 - 725 - 950 ns Clock-to-Memory Low Address Byte Valid, tPLH, tPHL 5 - 340 - 425 ns Clock to MRD, tPLH, tPHL 5 - 340 - 425 ns Clock to MWR, tPLH, tPHL 5 - 275 - 370 ns Clock to (CPU DATA to BUS) Valid, tPLH, tPHL 5 - 430 - 550 ns Clock to State Code, tPLH, tPHL 5 - 440 - 550 ns Clock to Q, tPLH, tPHL 5 - 375 - 475 ns Clock to N (0 to 2), tPLH, tPHL 5 - 400 - 525 ns INTERFACE TIMING REQUIREMENTS (Note 7) Data Bus Input Setup, tSU 51 0 - 1 0 - n s Data Bus Input Hold, tH 5 175 - 230 - ns DMA Setup, tSU 51 0 - 1 0 - n s DMA Hold, tH 5 200 - 270 - ns Interrupt Setup, tSU 51 0 - 1 0 - n s Interrupt Hold, tH 5 175 - 230 - ns WAIT Setup, tSU 53 0 - 3 0 - n s EF1-4 Setup, tSU 52 0 - 2 0 - n s EF1-4 Hold, tH 5 100 - 135 - ns REQUIRED PULSE WIDTH TIMES CLEAR Pulse Width, tWL 5 150 - 200 - ns CLOCK Pulse Width, tWL 5 140 - 185 - ns NOTE: 7. Minimum input setup and hold times required by Part CDP1802AC/3. CDP1802AC/3CDP1802AC/3

FIGURE 1. BASIC DC TIMING WAVEFORM, ONE INSTRUCTION CYCLE

  1. This timing diagram is us ed to show signal relationships only and does not represent any specific machine cycle.
  2. All measurements are referenced to 50% point of the waveforms.
  3. Shaded areas indicate “Don’t Care” or undefined state. Multiple transitions may occur during this period.

FIGURE 2. TIMING WAVEFORM

the program must routinely test the status of these flag(s). The flag(s) are sampled at the beginning of every S1 cycle. or read out of memory; and increment R(0). DMA-lN has priority followed by DMA-OUT and then Interrupt.

  1. Processing a DMA request,
  2. acknowledging an interrupt request. The levels of state

code are tabulated in Table 1. All states are valid at TPA. suppressed in IDLE when the CPU is in the load mode. address appears on the memory address lines MA0-7 first. address bits would permit a memory system of 64k bytes. the address lines have stabilized. additional information see Table 4. and the leading edge of TPB. TABLE 1. LEVELS OF STATE CODE

) in parallel with a resistance (10MΩ typ). recommended input voltage swing is VSS to VCC.

  1. The external memory (multiplexed, higher-order byte

first, on to 8 memory address lines).

  1. The D register (either of the two bytes can be gated to D).
  2. The increment/decrement circuit where it is increased or
  3. Designate one of the 16 registers in R to be acted upon
  4. Indicate to the I/O devices a command code or device

selection code for peripherals.

  1. Indicate the specific operation to be executed during the

class of miscellaneous instructions (70 - 73 and 78 - 7B).

  1. Indicate the value to be loaded into P to designate a new

register to be used as the program counter R(P).

  1. Indicate the value to be loaded into X to designate a new

register to be used as data pointer R(X). scratchpad locations (data registers) to hold two bytes of data. registers in R can be used as subroutine program counters. program counter is at the discretion of the user. points to memory for the following instructions (see Table 4).

  1. Output instructions 61 through 67
  2. Input instructions 69 through 6F
  3. Certain miscellaneous instructions - 70 - 73, 78, 60, F0

executions, the operation is referred to as “data immediate”. TABLE 2. TRUTH TABLE

always used as the data pointer during the DMA operation. such registers may be used as loop counters. of Q is also available as a microprocessor output. permit further interrupts or can be disabled to prevent them. operation does not force execution of the next instruction. TABLE 3. CONTROL MODES

TABLE 4. INSTRUCTION SUMMARY (See Notes 11 through 16)

TABLE 4. INSTRUCTION SUMMARY (See Notes 11 through 16) (Continued)

TABLE 4. INSTRUCTION SUMMARY (See Notes 11 through 16) (Continued)

  1. The arithmetic operations and the shift instructions are the only instructions that can alter the DF.

The syntax “-(not DF)” denotes the subtraction of the borrow.

  1. This instruction is associated with more than one mnemonic. Each mnemonic is individually listed.
  2. An idle instruction initiates a repeati ng S1 cycle. The processor will continue to idle until an I/O request (INTERRUPT
  3. Long-Branch, Long-Skip and No Op instructions require three cycles to complete (1 fetch + 2 execute).

rent program counter, respectively. This operation effects a branch to any memory location. If the tested condition is not met, the branching address bytes are skipped over, and the next instruction in sequence is fetched and executed. This operation is taken for the case of unconditional no branch (NLBR).

  1. The short-branch instructions are two by tes long. The first byte specifies the condition to be tested, and the second specifies the branching

same action is taken in the case of unconditional no branch (NBR).

  1. The skip instructions are one byte long. There is one Un conditional Short-Skip (SKP) and eight Long-Skip instructions.

except that the skipped-over byte is not considered part of the program. The Long-Skip instructions take three cycles to complete (1 fetch + 2 execute). by fetching the next instruction in sequence. TABLE 4. INSTRUCTION SUMMARY (See Notes 11 through 16) (Continued)

TABLE 5. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES

9 INP 1 BUS → MRX, D Data from

70 RET MRX → (X, P); RX + 1 → RX;

1 DlS MRX → (X, P); RX + 1 → RX;

TABLE 5. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued)

network for electrostatic protection during handling. the absolute maximum rating. signals should never be greater than VDD nor less than VSS. VSS, whichever is appropriate. devices by exceeding the maximum device dissipation.

9 ORl MRP OR D → D; RP + 1 → RP

  1. lE = 1, TPA, TPB suppressed, state = S1.
  2. BUS = 0 for entire cycle.
  3. Wait for DMA or INTERRUPT.
  4. Suppress TPA, wait for DMA.
  5. IN REQUEST has priority over OUT REQUEST.
  6. See “Timing Waveforms” beginning on page 7 and Figures 3 through 12 for “Machine Cyle Timing Waveforms beginning on page 9.

TABLE 5. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued)

FIGURE 22. BIAS/STATIC BURN-IN CIRCUIT

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN1441.3 October 17, 2008 CDP1802AC/3 Ceramic Dual-In-Line Metal Seal Packages (SBDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead di mensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE S S -D--A- -C- eA -B- aaa CA - BM DS Sccc CA - BM DS S D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 M A D40.6 MIL-STD-1835 CDIP2-T40 (D-5, CONFIGURATION C)

40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE

A - 0.225 - 5.72 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 2.096 - 53.24 4 E 0.510 0.620 12.95 15.75 4 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC - eA/2 0.300 BSC 7.62 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.070 0.38 1.78 5 S1 0.005 - 0.13 - 6 S2 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2 N4 0 4 0 8 Rev. 0 4/94