CDP1802A_1 INTERSIL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 28
Technical content
Features
- Maximum Input Clock Maximum Frequency Options At VDD = 5V Maximum Input Clock Maximum Frequency Options At VDD = 10V Minimum Instruction Fetch-Execute Times At VDD = 5V Any Combination of Standard RAM and ROM Up to 65,536 Bytes 8 -Bit Parallel Organization With Bidirectional Data Bus and Multiplexed Address Bus 16 x 16 Matrix of Registers for Use as Multiple Program Counters, Data Pointers, or Data Registers O n -Chip DMA, Interrupt, and Flag Inputs Programmable Single-Bit Output Port 91 Easy-to-Use Instructions
Description
The CDP1802 family of CMOS microprocessors are 8-bit register oriented central processing units (CPUs) designed for use as general purpose computing or control elements in a wide range of stored program systems or products. The CDP1802 types include all of the circuits required for fetching, interpreting, and executing instructions which have been stored in standard types of memories. Extensive input/output (I/O) control features are also provided to facili- tate system design. The 1800 series architecture is designed with emphasis on the total microcomputer system as an integral entity so that systems having maximum flexibility and minimum cost can be realized. The 1800 series CPU also provides a synchro- nous interface to memories and external controllers for I/O devices, and minimizes the cost of interface controllers. Fur- ther, the I/O interface is capable of supporting devices oper- ating in polled, interrupt driven, or direct memory access modes. The CDP1802A and CDP1802AC have a maximum input clock frequency of 3.2MHz at V DD = 5V. The CDP1802A and CDP1802AC are functionally identical. They differ in that the CDP1802A has a recommended operating voltage range of 4V to 10.5V, and the CDP1802AC a recommended operat- ing voltage range of 4V to 6.5V. The CDP1802BC is a higher speed version of the CDP1802AC, having a maximum input clock frequency of 5.0MHz at V DD = 5V, and a recommended operating voltage range of 4V to 6.5V.
Ordering Information
TEMPERATURE RANGE PACKAGE PKG. NO.5V - 3.2MHz 5V - 5MHz CDP1802ACE CDP1802BCE -40 oC to +85oC PDIP E40.6 CDP1802ACEX CDP1802B CEX Burn-In E40.6 CDP1802ACQ CDP1802BCQ -40 oC to +85oC PLCC N44.65 CDP1802ACD - -40 oC to +85oC SBDIP D40.6 CDP1802ACDX CDP1802BCDX Burn-In D40.6 March 1997 File Number 1305.2 CDP1802A, CDP1802AC, CDP1802BC CMOS 8-Bit Microprocessors CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143| Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved
40 LEAD PDIP (PACKAGE SUFFIX E)
40 LEAD SBDIP (PACKAGE SUFFIX D)
44 LEAD PLCC
FIGURE 1. TYPICAL CDP1802 SMALL MICROPROCESSOR SYSTEM
32 BYTE RAM
FIGURE 2. MUX M A 7M A 5M A 3M A 1 MA0MA2MA4MA6 MEMORY ADDRESS LINES I/O FLAGS ALU B D DF INCR/ DECR A R(0).1 R(0).0 R(1).0R(1).1 R(2).1 R(2).0 R(9).0 R(A).0R(A).1 R(9).1 R(E).1 R(F).1 R(F).0 R(E).0 REGISTER ARRAY 8-BIT BIDIRECTIONAL DATA BUS LATCH AND DECODE R XTP IN N1 I/O COMMANDS BUS 0 BUS 1 BUS 2 BUS 3 BUS 4 BUS 5 BUS 6 BUS 7 TO INSTRUCTION DECODE CONTROL AND TIMING LOGIC CLOCK LOGIC I/O REQUESTS CONTROL EF1 EF3 EF2 EF4 DMA OUT DMA IN INT CLEAR WAIT CLOCK XTAL SCO SCI Q LOGIC TPA TPB MWR MRD SYSTEM STATE CODES TIMING CDP1802A, CDP1802AC, CDP1802BC
Absolute Maximum Ratings Thermal Information DC Supply Voltage Range, (VDD ) (All Voltages Referenced to VSS Terminal) DD +0.5V Thermal Resistance (Typical, Note 4)θJA (oC/W) θJC (oC/W) Device Dissipation Per Output Transistor Operating Temperature Range (TA) Lead Temperature (During Soldering) At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Recommended Operating ConditionsTA = -40oC to +85oC. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: PARAMETER TEST CONDITIONS CDP1802A CDP1802AC CDP1802BC UNITS (NOTE 2) VCC (V) VDD (V) MIN MAX MIN MAX MIN MAX DC Operating Voltage Range - - 4 10.5 4 6.5 4 6.5 V Input Voltage Range - - V SS VDD VSS VDD VSS VDD V Maximum Clock Input Rise or Fall Time 4 to 6.5 4 to 6.5 - - - 1 - 1 µs 4 to 10.5 4 to 10.5 - 1 - - - - µs Minimum Instruction Time (Note 3) 5 5 5-5- 3 . 2 - µs 5 1 0 4----- µs Maximum DMA Transfer Rate 5 5 - 400 - 400 - 667 KBytes/s 5 1 0 - 5 0 0 ---- Maximum Clock Input Frequency, fCL , Load Capacitance (CL) = 50pF 5 5 DC 3.2 DC 3.2 DC 5 MHz 5 1 0 D C 4----M H z 10 10 DC 6.4 - - - - MHz NOTES: 1. Printed circuit board mount: 57mm x 57mm minimum area x 1.6mm thick G10 epoxy glass, or equivalent. 2. VCC must never exceed VDD . 3. Equals 2 machine cycles - one Fetch and one Execute operation for all instructions except Long Branch and Long Skip, which require 3 machine cycles - one Fetch and two Execute operations. 4. θJA is measured with component mounted on an evaluation board in free air. CDP1802A, CDP1802AC, CDP1802BC
Static Electrical Specificationsat TA = -40oC to +85oC, Except as Noted PARAMETER SYMBOL TEST CONDITIONS CDP1802A CDP1802AC, CDP1802BC UNITS VOUT (V) VIN (V) VCC , VDD (V) MIN (NOTE 1) TYP MAX MIN (NOTE 1) TYP MAX Quiescent Device Current I DD - - 5 - 0.1 50 - 1 200 µA Output Low Drive (Sink) (Except XTAL) 0.5 0, 10 10 2.2 4.4 - - - - mA XTAL 0.4 5 5 170 350 - 170 350 - µA Output High Drive (Source) (Except XTAL) 9.5 0, 10 10 -0.55 -1.1 - - - - mA XTAL 4.6 0 5 -125 -250 - -125 -250 - µA Output Voltage - 0, 5 5 - 0 0.1 - 0 0.1 V Low Level V OL - 0, 10 10 - 0 0.1 - - - V Output Voltage - 0, 5 5 4.9 5 - 4.9 5 - V High Level V OH - 0, 10 10 9.9 10 - - - - V Input Low Voltage V IL 0.5, 4.5 - 5 - - 1.5 - - 1.5 V Input High Voltage V CLEAR Input Voltage V H - - 5 0.4 0.5 - 0.4 0.5 - V Schmitt Hysteresis - - 5, 10 0.3 0.4 - - - - V Input Leakage Current I IN Any Input Three-State Output Leakage IOUT 0, 5 0, 5 5 - ±10-4 ±1- ±10-4 ±1 µA Current 0, 10 0, 10 10 - ±10-4 ±1 --- µA Operating Current CDP1802A, AC at f = 3.2MHz IDDI (Note 2) --5 - 24 -24 m A CDP1802BC at f = 5.0MHz --5 - - - -36 m A Minimum Data Retention Voltage VDR VDD = VDR -2 2 . 4 - 2 2 . 4 V Data Retention Current I DR VDD = 2.4V - 0.05 - - 0.5 - µA CDP1802A, CDP1802AC, CDP1802BC
Input Capacitance C IN - 5 7.5 - 5 7.5 pF Output Capacitance C OUT - 10 15 - 10 15 pF NOTES: 1. Typical values are for TA = +25oC and nominal VDD . 2. Idle “00” at M(0000), CL = 50pF. Dynamic Electrical SpecificationsTA = -40oC to +85oC, CL = 50pF, VDD ±5%, Except as Noted PARAMETER SYMBOL TEST CONDITIONS CDP1802A, CDP1802AC CDP1802BC UNITSVCC (V) VDD (V) (NOTE 1) TYP MAX (NOTE 1) TYP MAX PROPAGATION DELAY TIMES Clock to TPA, TPB t PLH , tPHL 5 5 200 300 200 300 ns 5 10 150 250 - - ns 10 10 100 150 - - ns Clock-to-Memory High-Address Byte t PLH , tPHL 5 5 600 850 475 525 ns 5 10 400 600 - - ns 10 10 300 400 - - ns Clock-to-Memory Low-Address Byte Valid t PLH , tPHL 5 5 250 350 175 250 ns 5 10 150 250 - - ns 10 10 100 150 - - ns Clock to MRD tPHL 5 5 200 300 175 275 ns 5 10 150 250 - - ns 10 10 100 150 - - ns Clock to MRD tPLH 5 5 200 350 175 275 ns 5 10 150 290 - - ns 10 10 100 175 - - ns Clock to MWR tPLH , tPHL 5 5 200 300 175 225 ns 5 10 150 250 - - ns 10 10 100 150 - - ns Clock to (CPU DATA to BUS) Valid t PLH , tPHL 5 5 300 450 250 375 ns 5 10 250 350 - - ns 10 10 100 200 - - ns Static Electrical Specificationsat TA = -40oC to +85oC, Except as Noted (Continued) PARAMETER SYMBOL TEST CONDITIONS CDP1802A CDP1802AC, CDP1802BC UNITS VOUT (V) VIN (V) VCC , VDD (V) MIN (NOTE 1) TYP MAX MIN (NOTE 1) TYP MAX CDP1802A, CDP1802AC, CDP1802BC
Clock to State Code t PLH , tPHL 5 5 300 450 250 400 ns 5 10 250 350 - - ns 10 10 150 250 - - ns Clock to Q t PLH , tPHL 5 5 250 400 200 300 ns 5 10 150 250 - - ns 10 10 100 150 - - ns Clock to N (0 - 2) t PLH , tPHL 5 5 300 550 275 350 ns 5 10 200 350 - - ns 10 10 150 250 - - ns MINIMUM SET UP AND HOLD TIMES Data Bus Input Set Up t SU 5 5 - 2 02 5- 2 0 0n s 5 10 0 50 - - ns 10 10 -10 40 - - ns Data Bus Input Hold t H (Note 2) 5 5 150 200 125 150 ns 5 10 100 125 - - ns 10 10 75 100 - - ns DMA Set Up t SU 5 5 03 003 0 n s 5 10 0 20 - - ns 10 10 0 10 - - ns DMA Hold t H (Note 2) 5 5 150 250 100 150 ns 5 10 100 200 - - ns 10 10 75 125 - - ns Interrupt Set Up t SU 5 5 -75 0 -75 0 ns 51 0- 5 0 0 - - n s 10 10 -25 0 - - ns Interrupt Hold t H (Note 2) 5 5 100 150 75 125 ns 5 10 75 100 - - ns 10 10 50 75 - - ns WAIT Set Up t SU 5 5 10 50 20 40 ns 5 10 -10 15 - - ns 10 10 0 25 - - ns Dynamic Electrical SpecificationsTA = -40oC to +85oC, CL = 50pF, VDD ±5%, Except as Noted (Continued) PARAMETER SYMBOL TEST CONDITIONS CDP1802A, CDP1802AC CDP1802BC UNITSVCC (V) VDD (V) (NOTE 1) TYP MAX (NOTE 1) TYP MAX CDP1802A, CDP1802AC, CDP1802BC
EF1-4 Set Up t SU 5 5 - 3 02 0- 3 0 0n s 5 10 -20 30 - - ns 10 10 -10 40 - - ns EF1-4 Hold t H (Note 2) 5 5 150 200 100 150 ns 5 10 100 150 - - ns 10 10 75 100 - - ns Minimum Pulse Width Times CLEAR Pulse Width t WL (Note 2) 5 5 150 300 100 150 ns 5 10 100 200 - - ns 10 10 75 150 - - ns CLOCK Pulse Width t WL 5 5 125 150 90 100 ns 5 10 100 125 - - ns 10 10 60 75 - - ns NOTES: 1. Typical values are for T A = +25oC and nominal VDD . 2. Maximum limits of minimum characteristics are the values above which all devices function. Timing Specificationsas a function of T(T = 1/fCLOCK ) at TA = -40 to +85oC, Except as Noted PARAMETERS SYMBOL TEST CONDITIONS CDP1802A, CDP1802AC CDP1802BC UNITSVCC (V) V DD (V) MIN (NOTE 1) TYP MIN (NOTE 1) TYP High-Order Memory-Address Byte Set Up to TPA Time tSU 5 5 2T-550 2T-400 2T-325 2T-275 ns 5 10 2T-350 2T250 - - ns 10 10 2T-250 2T-200 - - ns High-Order Memory-Address Byte Hold After TPA Time tH 5 5 t/2-25 T/2-15 T/2-25 T/2-15 ns 5 10 T/2-35 T/2-25 - - ns Low-Order Memory-Address Byte Hold After WR Time tH 5 5 T-30 T+0 T-30 T+0 ns 51 0 T - 2 0 T + 0 - - n s 10 10 T-10 T+0 - - ns CPU Data to Bus Hold After WR Time tH 5 5 T-200 T-150 T-175 T-125 ns 5 10 T-150 T-100 - - ns 10 10 T-100 T-50 - - ns Dynamic Electrical SpecificationsTA = -40oC to +85oC, CL = 50pF, VDD ±5%, Except as Noted (Continued) PARAMETER SYMBOL TEST CONDITIONS CDP1802A, CDP1802AC CDP1802BC UNITSVCC (V) VDD (V) (NOTE 1) TYP MAX (NOTE 1) TYP MAX CDP1802A, CDP1802AC, CDP1802BC
FIGURE 3. BASIC DC TIMING WAVEFORM, ONE INSTRUCTION CYCLE
- This timing diagram is used to show signal relationships only and does not represent any specific machine cycle.
- All measurements are referenced to 50% point of the waveforms.
- Shaded areas indicate “Don’t Care” or undefined state. Multiple transitions may occur during this period.
FIGURE 4. TIMING WAVEFORM
INTERRUPT , DMA-lN, DMA-OUT (3 I/O Requests) These inputs are sampled by the CPU during the interval between the leading edge of TPB and the leading edge of TPA. Interrupt Action - X and P are stored in T after executing current instruction; designator X is set to 2; designator P is set to 1; interrupt enable is reset to 0 (inhibit); and instruction execution is resumed. The interrupt action requires one machine cycle (S3). DMA Action - Finish executing current instruction; R(0) points to memory area for data transfer; data is loaded into or read out of memory; and increment R(0). NOTE: In the event of concurrent DMA and Interrupt requests, DMA-lN has priority followed by DMA-OUT and then Interrupt. SC0, SC1, (2 State Code Lines) These outputs indicate that the CPU is: 1) fetching an instruction, or 2) executing an instruction, or 3) processing a DMA request, or 4) acknowledging an interrupt request. The levels of state code are tabulated below. All states are valid at TPA. H = V CC , L = VSS . TPA, TPB (2 Timing Pulses) Positive pulses that occur once in each machine cycle (TPB follows TPA). They are used by I/O controllers to interpret codes and to time interaction with the data bus. The trailing edge of TPA is used by the memory system to latch the higher-order byte of the 16-bit memory address. TPA is sup- pressed in IDLE when the CPU is in the load mode. MA0 to MA7 (8 Memory Address Lines) In each cycle, the higher-order byte of a 16-bit CPU memory address appears on the memory address lines MA0-7 first. Those bits required by the memory system can be strobed into external address latches by timing pulse TPA. The low order byte of the 16-bit address appears on the address lines after the termination of TPA. Latching of all 8 higher-order address bits would permit a memory system of 64K bytes. MWR (Write Pulse) A negative pulse appearing in a memory-write cycle, after the address lines have stabilized. MRD (Read Level) A low level on MRD indicates a memory read cycle. It can be used to control three-state outputs from the addressed mem- ory which may have a common data input and output bus. If a memory does not have a three-state high-impedance output, MRD is useful for driving memory/bus separator gates. It is also used to indicate the direction of data transfer during an I/O instruction. For additional information see Table 1. Q Single bit output from the CPU which can be set or reset under program control. During SEQ or REQ instruction exe- cution, Q is set or reset between the trailing edge of TPA and the leading edge of TPB. CLOCK Input for externally generated single-phase clock. The clock is counted down internally to 8 clock pulses per machine cycle. XTAL Connection to be used with clock input terminal, for an exter- nal crystal, if the on-chip oscillator is utilized. The crystal is connected between terminals 1 and 39 (CLOCK and XTAL) in parallel with a resistance (10MΩ typ). Frequency trimming capacitors may be required at terminals 1 and 39. For addi- tional information, see Application Note AN6565. WAIT , CLEAR (2 Control Lines) Provide four control modes as listed in the following truth table: VDD , VSS , VCC (Power Levels) The internal voltage supply VDD is isolated from the Input/Output voltage supply VCC so that the processor may operate at maximum speed while interfacing with peripheral devices operating at lower voltage. VCC must be less than or equal to VDD . All outputs swing from VSS to VCC . The recom- mended input voltage swing is VSS to VCC . Architecture The CPU block diagram is shown in Figure 2. The principal feature of this system is a register array (R) consisting of six- teen 16-bit scratchpad registers. Individual registers in the array (R) are designated (selected) by a 4-bit binary code from one of the 4-bit registers labeled N, P and X. The con- tents of any register can be directed to any one of the follow- ing three paths: 1. The external memory (multiplexed, higher-order byte first, on to 8 memory address lines). 2. The D register (either of the two bytes can be gated to D). 3. The increment/decrement circuit where it is increased or decreased by one and stored back in the selected 16-bit register. STATE TYPE STATE CODE LINES SC1 SC0 S0 (Fetch) L L S1 (Execute) L H S2 (DMA) H L S3 (Interrupt) H H CLEAR WAIT MODE LL L O A D LH R E S E T HL P A U S E H H RUN CDP1802A, CDP1802AC, CDP1802BC
The three paths, depending on the nature of the instruction, may operate independently or in various combinations in the same machine cycle. With two exceptions, CPU instruction consists of two 8- clock-pulse machine cycles. The first cycle is the fetch cycle, and the second - and third if necessary - are execute cycles. During the fetch cycle the four bits in the P designator select one of the 16 registers R(P) as the current program counter. The selected register R(P) contains the address of the mem- ory location from which the instruction is to be fetched. When the instruction is read out from the memory, the higher order 4 bits of the instruction byte are loaded into the register and the lower order 4 bits into the N register. The content of the program counter is automatically incremented by one so that R(P) is now “pointing” to the next byte in the memory. The X designator selects one of the 16 registers R(X) to “point” to the memory for an operand (or data) in certain ALU or I/O operations. The N designator can perform the following five functions depending on the type of instruction fetched: 1. Designate one of the 16 registers in R to be acted upon during register operations. 2. Indicate to the I/O devices a command code or device selection code for peripherals. 3. Indicate the specific operation to be executed during the ALU instructions, types of test to be performed during the Branch instruction, or the specific operation required in a class of miscellaneous instructions (70 - 73 and 78 - 7B). 4. Indicate the value to be loaded into P to designate a new register to be used as the program counter R(P). 5. Indicate the value to be loaded into X to designate a new register to be used as data pointer R(X). The registers in R can be assigned by a programmer in three different ways: as program counters, as data pointers, or as scratchpad locations (data registers) to hold two bytes of data. Program Counters Any register can be the main program counter; the address of the selected register is held in the P designator. Other reg- isters in R can be used as subroutine program counters. By single instruction the contents of the P register can be changed to effect a “call” to a subroutine. When interrupts are being serviced, register R(1) is used as the program counter for the user's interrupt servicing routine. After reset, and during a DMA operation, R(0) is used as the program counter. At all other times the register designated as pro- gram counter is at the discretion of the user. Data Pointers The registers in R may be used as data pointers to indicate a location in memory. The register designated by X (i.e., R(X)) points to memory for the following instructions (see Table 1). 1. ALU operations F1 - F5, F7, 74, 75, 77 2. Output instructions 61 through 67 3. Input instructions 69 through 6F 4. Certain miscellaneous instructions - 70 - 73, 78, 60, F0 The register designated by N (i.e., R(N)) points to memory for the “load D from memory” instructions 0N and 4N and the “Store D” instruction 5N. The register designated by P (i.e., the program counter) is used as the data pointer for ALU instructions F8 - FD, FF, 7C, 7D, 7F. During these instruction executions, the operation is referred to as “data immediate”. Another important use of R as a data pointer supports the built-in Direct-Memory-Access (DMA) function. When a DMA-ln or DMA-Out request is received, one machine cycle is “stolen”. This operation occurs at the end of the execute machine cycle in the current instruction. Register R(0) is always used as the data pointer during the DMA operation. The data is read from (DMA-Out) or written into (DMA-ln) the memory location pointed to by the R(0) register. At the end of the transfer, R(0) is incremented by one so that the pro- cessor is ready to act upon the next DMA byte transfer request. This feature in the 1800-series architecture saves a substantial amount of logic when fast exchanges of blocks of data are required, such as with magnetic discs or during CRT-display-refresh cycles. Data Registers When registers in R are used to store bytes of data, four instructions are provided which allow D to receive from or write into either the higher-order or lower-order byte portions of the register designated by N. By this mechanism (together with loading by data immediate) program pointer and data pointer designations are initialized. Also, this technique allows scratchpad registers in R to be used to hold general data. By employing increment or decrement instructions, such registers may be used as loop counters. The Q Flip-Flop An internal flip-flop, Q, can be set or reset by instruction and can be sensed by conditional branch instructions. The output of Q is also available as a microprocessor output. CDP1802A, CDP1802AC, CDP1802BC
rupted value of X and P with a single instruction (70 or 71). ther interrupts or can be disabled to prevent them. tion does not force execution of the next instruction. ues to operate, but subsequent clock transitions are ignored. response to a DMA request and S3 is the interrupt response. Address lines during all machine states. mal notation is used to refer to the 4-bit binary codes. (LSB) to the most significant bit (MSB) starting with 0. FIGURE 24. RESET DIAGRAM
loaded into D, and R(N) is incremented by 1. FIGURE 25. STATE TRANSITION DIAGRAM TABLE 1. INSTRUCTION SUMMARY (SEE NOTES)
TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued)
TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued)
TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued)
- The arithmetic operations and the shift instructions are the only instructions that can alter the DF.
The syntax “-(not DF)” denotes the subtraction of the borrow.
- This instruction is associated with more than one mnemonic. Each mnemonic is individually listed.
- An idle instruction initiates a repeating S1 cycle. The processor will continue to idle until an I/O request (INTERRUPT
activated. When the request is acknowledged, the idle cycle is terminated and the I/O request is serviced, and then normal operation is resumed.
- Long-Branch, Long-Skip and No Op instructions require three cycles to complete (1 fetch + 2 execute).
current program counter, respectively. This operation effects a branch to any memory location. cuted. This operation is taken for the case of unconditional no branch (NLBR).
- The short-branch instructions are two bytes long. The first byte specifies the condition to be tested, and the second specifies the branching address.
and executed. This same action is taken in the case of unconditional no branch (NBR).
- The skip instructions are one byte long. There is one Unconditional Short-Skip (SKP) and eight Long-Skip instructions.
The Unconditional Short-Skip instruction takes 2 cycles to complete (1 fetch + 1 execute). Its action is to skip over the byte following it. tion (NBR) except that the skipped-over byte is not considered part of the program. The Long-Skip instructions take three cycles to complete (1 fetch + 2 execute). is continued by fetching the next instruction in sequence. TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued)
TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES
9 INP 1 BUS → MRX, D Data from
1 DlS MRX → (X, P); RX + 1 → RX;
TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. work for electrostatic protection during handling. DD - VSS to exceed the absolute maximum rating. when the power supply is off. to either VDD or VSS , whichever is appropriate.
- lE = 1, TPA, TPB suppressed, state = S1.
- BUS = 0 for entire cycle.
- Wait for DMA or INTERRUPT.
- Suppress TPA, wait for DMA.
- IN REQUEST has priority over OUT REQUEST.
- See Timing Waveforms, Figure 5 through Figure 14 for machine cycles.
TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued)