CDP1020

CDP1020 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

Fully Compliant with Device Bay Speciﬁcation 0.90 and ACPI Speciﬁcation 1.0
Industry Standard SMBus/I2C Interface
Controls for Two Device Bays
Onboard Level Shifting for Direct Drive of N-Channel MOSFET V ID Switches
Integrated Pull-up Resistors on 1394PRx, USBPRx, SECUREx, and REMREQx Inputs
RC Type Oscillator - Low Cost and Low Power Consumption
Operational Voltage from 3.3 to 5.5V
“5V Tolerant” Inputs at all Operating Voltages
Write-Once BIOS/External Conﬁguration
Removal Request Input for Each Bay
Security Lock Input for Each Bay
High Current Device Bay LED Indicator Drivers With Separate High-Side Power Input
Conﬁgurable Level/Pulse Bay Solenoid Drivers
Programmable Insertion Time Out Delay
HCMOS Technology; 28 Lead Plastic SOIC Pinout CDP1020 (SOIC) TOP VIEW

Ordering Information

TEMP. RANGE (oC) PACKAGE PKG. NO. CDP1020 0 to 85 28 Ld SOIC M28.3 LEDA1 REMREQ1 VDD LEDA0 LEDG0 SFTLOCK1 PWREN0VGATE LEDG1USBPR1 1394PR1 RESET ALR T SCK SDA USBPR0 1394PR0 SFTLOCK0 PWREN1 SECURE1 SECURE0 REMREQ0 VLED AD0 AD1 TEST (VDD ) VSS CLK Data Sheet April 1999 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

PIN NUMBER PIN NAME IN/OUT PIN DESCRIPTION

1 RESET IN Device Bay Controller Master Reset Schmitt Input

2 TEST - Test pin used by manufacturer only. Must be externally connected to V DD 3 1394PR0 IN Bay 0 1394 Presence Input with Active Pull-up

4 USBPR0 IN Bay 0 USB Presence Input with Active Pull-up

5 REMREQ0 IN Bay 0 Remove Request Input with Active Pull-up

6 SECURE0 IN Bay 0 Security Input with Active Pull-up

7 1394PR1 IN Bay 1 1394 Presence Input with Active Pull-up

8 USBPR1 IN Bay 1 USB Presence Input with Active Pull-up

9 REMREQ1 IN Bay 1 Remove Request Input with Active Pull-up

10 SECURE1 IN Bay 1 Security Input with Active Pull-up

11 SDA IN/OUT SMBus/I 2C Data Schmitt Input/Open-Drain Output

12 SCK IN/OUT SMBus/I 2C Clock Schmitt Input/Open-Drain Output

13 ALRT OUT SMBus Alert Open-Drain Output

14 V GATE - Power Supply Input for PWREN0/PWREN1 Drivers

15 PWREN0 OUT Bay 0 Power Enable 12V NMOS Gate Drive Output

16 PWREN1 OUT Bay 1 Power Enable 12V NMOS Gate Drive Output

17 SFTLOCK0 OUT Bay 0 Software Controlled Lock Mechanism Driver

18 SFTLOCK1 OUT Bay 1 Software Controlled Lock Mechanism Driver

19 LEDG0 OUT Bay 0 Status Indicator (Green LED) Driver

20 LEDA0 OUT Bay 0 Status Indicator (Amber LED) Driver

21 LEDG1 OUT Bay 1 Status Indicator (Green LED) Driver

22 LEDA1 OUT Bay 1 Status Indicator (Amber LED) Driver

LED - Power Supply Input for LED Driver (LEDAx, LEDGx)

24 V DD - Power Supply Input (Power)

25 V SS - Power Supply Return (Ground or GND)

26 CLK IN External Clock Schmitt Input (for RC oscillator)

27 AD0 IN SMBus/I

2C Address Configuration Bit 0

28 AD1 IN SMBus/I 2C Address Configuration Bit 1

BSTR0 - $10 BCER0 - $14 DEVICE BAY 1 CONTROLLER BSTR1 - $18 BCER1 - $1C VENDOR - $00 REVISION - $04 SUBSYS VENDOR - $08 SUBSYS REV- $0A DBCCR - $0C I2C/SMBus INTERFACE DEVICE BAY CONTROLLER LOGIC RESET CLKOSCILLATOR CIRCUITRY AD0 AD1 SFR - $FC VLED TIMER/ 1394PR1 USBPR1 REMREQ1 LEDA1 LEDG1 PWREN1 SFTLOCK1 SECURE1 LEVEL DEBOUNCE LEVEL SHIFT VGATE DEVICE BAY 0 CONTROLLER VLED TIMER/ 1394PR0 USBPR0 REMREQ0 LEDA0 LEDG0 PWREN0 SFTLOCK0 SECURE0 LEVEL DEBOUNCE LEVEL SHIFT VGATE LOGIC and PULLUP Rs LOGIC and PULLUP Rs SHIFTERSHIFTER CDP1020

Absolute Maximum Ratings Thermal Information Operating Conditions oC to 85oC Thermal Resistance (Typical, Note 1) θJA (oC/W) Maximum Storage Temperature Range (TSTG ). . . . -65oC to 150oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Voltage -10 µA < ILOAD < 10µA All Outputs V OL - - 0.1 V SFTLOCK0, SFTLOCK1 V OH VDD - 0.1 - - V Output High Voltage LEDA0, LEDG0, LEDA1, LEDG1 V OH ILOAD = -16.0mA V LED - 1.0 - - V SFTLOCK0, SFTLOCK1 V OH ILOAD = -0.7mA V DD - 0.3 - - V Output Low Voltage SCK, SDA, ALRT, SFTLOCK0, SFTLOCK1, LEDG0, LEDA0, LEDG1, LEDA1 VOL ILOAD = 1.6mA - - 0.4 V PWREN0, PWREN1 V OL ILOAD = 60µA - - 0.4 V Gate Output High Voltage PWREN0, PWREN1 V GOH ILOAD < 10µAV GATE -0.5V VGATE -0.3V VGATE V Gate Output Current Source PWREN0, PWREN1 I GATE -15 -35 -50 µA Input High Voltage 1394PR0, USBPR0, REMREQ0, SECURE0, 1394PR1, USBPR1, REMREQ1, SECURE1 VIH 0.7•VDD -V DD V SCK, SDA V IH 0.7•VDD -V DD V RESET, CLK V IH 0.7•VDD -V DD V Input Low Voltage 1394PR0, USBPR0, REMREQ0, SECURE0, 1394PR1, USBPR1, REMREQ1, SECURE1, RESET, CLK VIL VSS - 0.2•V DD V SCK, SDA V IL VSS - 0.2•V DD V Input/Output Leakage Current: RESET, CLK, AD0, AD1, SCK, SDA,ALR TI IOL -- ±10 µA Input Pullup Current 1394PR0, USBPR0, REMREQ0, SECURE0, 1394PR1, USBPR1, REMREQ1, SECURE1 IIN 50 200 400 µA Input Hysteresis Voltage SCK, SDA V HYS 0.02 0.10 0.40 V CLK V HYS 0.6 1.0 1.3 V RESET V HYS 0.8 1.1 1.4 V CDP1020

Capacitance C OUT - - 12 pF C IN --8 p F Supply Current (RUN) I DD fCLK = 4.0MHz External - 1.3 5.0 mA PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Voltage -10 µA < ILOAD < 10µA All Outputs V OL - - 0.1 V SFTLOCK0, SFTLOCK1 V OH VDD - 0.1 - - V Output High Voltage LEDA0, LEDG0, LEDA1, LEDG1 V OH ILOAD = -6.0mA V LED - 1.0 - - V SFTLOCK0, SFTLOCK1 V OH ILOAD = -0.4mA V DD - 0.3 - - V Output Low Voltage SCK, SDA, ALRT, SFTLOCK0, SFTLOCK1, LEDG0, LEDA0, LEDG1, LEDA1 VOL ILOAD = 1.6mA - - 0.4 V PWREN0, PWREN1 V OL ILOAD = 50µA - - 0.4 V Gate Output High Voltage PWREN0, PWREN1 V GOH ILOAD < 10µAV GATE -0.5V VGATE -0.3V VGATE V Gate Output Current Source PWREN0, PWREN1 I GATE -10 -20 -30 µA Input High Voltage 1394PR0, USBPR0, REMREQ0, SECURE0, 1394PR1, USBPR1, REMREQ1, SECURE1 VIH 0.7•VDD -V DD V SCK, SDA V IH 0.7•VDD -V DD V RESET, CLK V IH 0.7•VDD -V DD V Input Low Voltage 1394PR0, USBPR0, REMREQ0, SECURE0, 1394PR1, USBPR1, REMREQ1, SECURE1, RESET, CLK VIL VSS - 0.2•V DD V SCK, SDA V IL VSS - 0.2•V DD V Input/Output Leakage Current: RESET, CLK, AD0, AD1, SCK, SDA,ALR TI IOL -- ±10 µA Input Pullup Current 1394PR0, USBPR0, REMREQ0, SECURE0, 1394PR1, USBPR1, REMREQ1, SECURE1 IIN 20 80 160 µA Input Hysteresis Voltage SCK, SDA V HYS 0.05 0.15 0.45 V CLK V HYS 0.4 0.8 1.1 V RESET V HYS 0.3 0.5 0.8 V Capacitance C OUT - - 12 pF C IN --8 p F Supply Current (RUN) I DD - 0.9 4.5 mA PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CDP1020

Hexadecimal numbers are denoted with a “$” symbol preceding the number.
Binary numbers are represented with a “%” symbol proceeding the number, or a “b” following.
Because of the large mix of active-low and active-high signals used in connection with the CDP1020, the terms “asserted” and “de-asserted” will be used exclusively. An active low signal is asserted when it is at a logic 0 and de- asserted when it is at a logic 1 state. Conversely, an active high signal is at a logic 1 state when asserted and at a logic 0 state when de-asserted. The terms reset, clear, and “low” can also mean logic 0; set or “high” can also mean logic 1.
Active low signals are represented with an overline; active high signals have no overline. For example, REMREQ0 is active low, PWREN0 is active high.
There are many pins, signals, registers, and software bits common to both Bay 0 and Bay 1; these names may include the Bay number sufﬁx (0 or 1), an “x” to represent either, or no sufﬁx at all. For example, PWREN, PWREN0, or PWRENx may each be used to describe output pin(s). SCK SDA STOP START START tHD:STA tLOW tHIGH tSU:STO STOP tHD:DAT tSU:DAT tSU:STA tHD:STA

FIGURE 1. CONTROL TIMING

the CDP1020 as shown in Figure 2. regardless of the operating voltage of the IC. to the CDP1020 without the presence of the VDD and VSS supplies. input voltage, thus enabling any of their output circuitry. Schmitt Trigger to improve noise immunity. Interface text for more details. control MOSFETs per Device Bay Speciﬁcation 0.90. (SFR) to be a level or a pulse of a user deﬁned duration. Hardware text for more details. FIGURE 2. PINOUT DIAGRAM FOR THE CDP1020

and is not tied to the VDD rail of the device. external resistor-capacitor circuit, as shown in Figure 3. shouldnot be used with the CDP1020. I2C/SMBus Interface text for more details. DD for a logic high; VSS for a logic low). placed on the same bus (addresses $90, $92, $94, $96). AD1:AD0 input pins, and the “Y” is the R/W (Read/Write) bit. operations will be odd ($91). always be used to set the CDP1020 internal address pointer. are written directly into the register space of the CDP1020. a multiple byte write to the CDP1020. FIGURE 3. RC OSCILLATOR CONFIGURATION

1 Start Condition, generated byI2C /SMB us master (defined

as negative edge on SDA while SCK is high).

2 CDP1020 I

write portion of the transmission.

5 Command byte sent from I

be used to set the internal address pointer of the CDP1020. written into the register specified by the command byte. should continue to transmit data.

7 Stop condition, generated by the

(defined as a positive edge on SDA while SCK is high). during the write portion of the transmission, plus one. FIGURE 5. CDP1020 I2C/SMBUS TRANSMISSION PROTOCOLS

NOTE: The register set in the CDP1020 is implemented in little- endian format, as speciﬁed in Device Bay Speciﬁcation 0.90. As such, the least signiﬁcant byte in any register is in the lowest memory address for that register; likewise the most signiﬁcant byte is in the highest memory address. In the DBCCR, for example, the least signiﬁcant byte (containing the conﬁguration data) is at address $0C. The most signiﬁcant byte (containing all 0’s) is at address $0F . The following subsections describe each of the registers within the CDP1020. Vendor ID Register, $00 Per Device Bay Speciﬁcation 0.90, the ﬁrst register in the CDP1020 register set is the Vendor ID register. The contents of this register identify the manufacturer of the Device Bay Controller. This register is a read-only register that contains $1260, the 16-bit Intersil Corporation PCI SIG identiﬁcation number. This number is contained in the lower two bytes of the register; the upper two bytes are always read as $0000. Revision ID Register, $04 The Revision ID register contains the 8-bit device bay controller manufacturer revision ID. This number is used to identify a particular Device Bay controller from the manufacturer speciﬁed in the Vendor ID register. The Revision ID is a read-only register that contains the 8-bit revision code for the CDP1020. This number is contained in the lower byte of the register; the upper three bytes are always read as $000000. Subsystem Vendor ID Register, $08 The Subsystem Vendor ID Register is used to identify the manufacturer of the device bay system that the CDP1020 is installed in. This register is implemented as a write-once- only register and is designed to be written by the system BIOS immediately after either the power-on-reset, or asserting the RESET pin, which enables a write to this register. Once written, this register becomes read-only and should contain the 16-bit subsystem manufacturer identiﬁcation number. This register and the Subsystem ID register are the only 16-bit registers in the CDP1020. Subsystem ID Register, $0A The Subsystem ID register contains a 16-bit subsystem vendor deﬁned ID number. Typically, this number would deﬁne the device bay system revision or model number. Like the Subsystem Vendor ID, this register is implemented as a write-once-only register and is designed to be written by the system BIOS immediately after either the power-on-reset, or asserting the RESET pin, which enables a write to this register. Once written, this register becomes read-only. This register and the Subsystem Vendor ID register are the only 16-bit registers in the CDP1020. Device Bay Controller Capabilities Register, $0C The Device Bay Controller Capabilities Register (DBCCR) is designed to allow the operating system to easily identify the features of the Device Bay system controlled by the CDP1020. This register contains ﬁve write-once-only bits, deﬁned below. These bits, like those in the Subsystem Vendor ID Register, are designed to be written by the system BIOS immediately after power-on. Once written, they become read-only. The upper 27 bits of the DBCCR are always read as 0 This register is set to $00000002 at reset (two bays, no security locks). BITS 31:5 Reserved for future use. Always read as 0. SECLOCK The SECLOCK bit indicates the presence of an optional physical security lock on at least one of the device bays controlled by the CDP1020. If set, then at least one of the device bays has the physical security lock, the state of which is available in the bay status register BSTRx. If clear, no physical security lock exists in the system. SECLOCK is implemented as a write-once-only bit intended to be written by the BIOS immediately after system power-on. Once written to, this bit becomes read-only. BAYCNT[3:0] The four BAYCNT bits represent the number of bays controlled by the CDP1020 in binary form. These bits, like the SECLOCK bit, are implemented as a write-once-only bits intended to be written by the BIOS immediately after system power-on. Once written to, they become read-only. Since the CDP1020 is a two bay controller, the only valid values that can be written to the BAYCNT[3:0] bits are 0, 1 and 2. If the OS tries to write any other value, the CDP1020 will write a value of 2 (%0010) to this bit field. Bits 31:16 Bits 15:0 $0000 $1260 (Intersil PCI-SIG ID) $00 Bits 31:8 Bits 7:0 $000000 Revision ID $04 Bits 15:0 Subsystem Vendor ID $08 Bits 15:0 Subsystem ID $0A Bits 31:5 Bit 4 Bits 3:0 $00000 SECLOCK BAYCNT[3:0] $0C CDP1020

Bay Control and Enable Register, BCERx The CDP1020 incorporates two separate bay control and enable registers, one for each bay. The organization of these two registers is identical. BCER0 is located at address $10; BCER1 is at $18. Both BCER registers are cleared at reset. BITS 31:8 Reserved. Always read as 0. BIT 7, LOCK_CTL The LOCK_CTL is a read/write bit that controls the software controlled solenoid interlock for each bay. This bit has two distinct modes of operation, depending on the value written into the SOL[3:0] bits in the SFR. If the SOL[3:0] bits in the SFR contain any nonzero value, the LOCK_CTL bit logic is in “pulsed” mode. In pulse mode, the SFTLOCK output will be asserted for a fixed time duration when the LOCK_CTL is changed from a logic 1 to a logic 0. Writinga0t othis bit while it is already 0 has no effect. Writing a 1 to this bit while it is a 0 will set the bit, but will not affect the SFTLOCK output. The duration of the SFTLOCK pulse is controlled by the SPD and SOL[3:0] bits in the SFR. Refer to the Special Function Register text for more details. If the SOL[3:0] bit in the SFR are all 0, the LOCK_CTL circuitry is in “level” mode. In this case, the SFTLOCK output corresponding to the LOCK_CTL bit will simply follow the state of the LOCK_CTL bit. When the LOCK_CTL is set, the SFTLOCK output will be high; likewise, when the LOCK_CTL bit is clear, the SFTLOCK output will be low. Figure 7 shows the relationship between the LOCK_CTL bit and its corresponding SFTLOCK output in both level and pulsed modes. BITS 6:4, BAY_STREQ[2:0] This three bit field represents the state of the bay as requested by the operating system. It does not necessarily represent the actual state of the bay. The states are represented as such: If 000 is written, then no change to the current bay state is requested and the current nonzero value of this ﬁeld is retained. This allows the operating system to modify other bits in this register without affecting the bay state. A bay state change will only occur when these ﬁelds are written if a device is inserted ( 1394PRx & USBPRx = 0). These bits may be read or written at any time by the operating system. These bits are cleared by any hardware transition to the Bay Empty State (i.e., device removal). BIT 3, REMREQ_EN This read/write bit allows the operating system to enable/disable internal CDP1020 interrupts and bay state transitions due to a logic “0” input value of the REMREQx pin. If this bit is clear, the CDP1020 will not notify the OS and will not transition the bay state to Removal Requested when the REMREQx button has been pushed. If this bit is set after the REMREQ_STS bit in the BSTR has been set, an interrupt event will be generated and a bay status change will occur. This bit is cleared by reset. BIT 2, DEVSTSCHG_EN This is a read/write bit that enables/disables internal CDP1020 interrupt events and bay state transitions due to the setting of the DEVSTSCHG bit in the BSTR. If this bit is clear, the CDP1020 will not notify the OS whenever the bay state has changed. The DEVSTSCHG bit in the BSTRx will still reflect a bay state change. The DEVSTSCHG_EN bit also allows the CDP1020 to automatically transition the bay state to Device Inserted when an insertion event is the cause of the DEVSTSCHG. Hardware transitions to the Bay Empty state will always occur on a device removal, regardless of the state of the DEVSTSCHG_EN bit. This bit is cleared by reset. BIT 1, REMEVTWAK_EN This bit enables/disables internal CDP1020 interrupt events due to device removal. This bit gates the device removal event in the DEVSTSCHG logic (see Bay Status Register, below). The intent is to conditionally allow device removal as a wake-up event. If clear, this bit will prevent the DEVSTSCHG flag in the BSTR from being set when a device is removed and the bay is in the Removal Allowed state. A hardware transition to the Bay Empty state will still occur. This bit does not affect any of the interrupt logic if the bay is not in the Removal Allowed state. This bit is cleared by reset. BIT 0, PWR_CTL The PWR_CTL is the enable bit for the V ID power rail. When set, the internal logic of the CDP1020 will output the VGATE voltage level on the PWREN pin associated with this register. (Refer to thePower Enable System text for more details) When clear, the PWREN pin will be pulled down to V SS by a standard N-Channel output driver. This allows the gate voltage of the V ID control MOSFET to be discharged quickly and the device switched off. No external pull down resistor is necessary. This bit is cleared by reset. This bit cannot be set if there is no device in the bay (1394PRx & USBPRx = 1) or if the LOCK_CTL bit is clear. If set and a device is suddenly removed (i.e., without OS permission), the CDP1020 will clear this bit and disable the PWRENx output. Note: A single write to the BCER may set both the LOCK_CTL and PWR_CTL bits at the same time.

000 No change requested

001 Request Bay State = Device Inserted

010 Request Bay State = Device Enabled

011 Request Bay State = Removal Requested

100 Request Bay State = Removal Allowed

101 Reserved

110 Reserved

111 Reserved

Bay Status Register, BSTRx Like the Bay Control and Enable register, there is one Bay Status register associated with each bay controlled by the CDP1020. The addresses for the BSTR registers are $14 (BSTR0) and $20 (BSTR1). Both BSTR registers are cleared at reset. BITS 31:11 Reserved, always read as 0. BITS 10:8, BAY_FF[2:0] This three bit ﬁeld indicates the form factor of the controlled bay: These bits are write-once only bits after a power-on reset and should be written by the system BIOS or the operating system at start-up. Once written, these bits become read- only. Subsequent internal and external resets do not affect the write status of these bits. The value of these bits is indeterminate at power on and are not affected by any type of reset. BIT 7, SL_STS The read only SL_STS indicates the state of the external security lock. This bit simply reﬂects the inverted state of the SECUREx pin. If clear, external security lock is disengaged. If set, the lock is engaged. The state of this bit depends on the external state of the SECUREx pin and the state of the SECLOCK bit in the DBCCR register (see above). If the SECLOCK bit is clear, this bit will always read as a “0”. If SECLOCK is set, the state of this bit will reﬂect the inverted state of the SECUREx pin. BIT 6:4, BAY_ST[2:0] This three bit field represents the actual state of the bay. These bits are read only. The bay state is represented as such: Bay states and how they are controlled is described in the State Machine Logic text. BIT 3, REMREQ_STS This bit indicates that the removal request button for this bay has been pressed (REMREQx pin has been driven low). This bit is referred to as a “sticky status bit”; once set, the you must write a “1” to this bit position to clear it. If the REMREQ_EN bit in the associated control register is set, the CDP1020 will generate a REMREQ interrupt event when this bit is set. AREMREQ interrupt event will cause a hardware transition of the bay state to Removal Allowed and assert the ALR T pin of the CDP1020 to notify the OS of theREMREQx button press. BIT 2, DEVSTSCHG This bit indicates that a hardware event has occurred that has changed the status of the device bay. This could be caused by a device insertion or a device removal. This bit, like the REMREQ_STS bit, is a sticky status bit; once set, the OS must write a “1” to clear it. This bit will be set on all device removals except when the REMEVTWAK_EN bit in the BCER is clear and the bay is in the Removal Allowed state. If the DEVSTSCHG bit is set due to an insertion event and the DEVSTSCHG_EN bit in the BCER is set, the CDP1020 will hardware transition the bay state to Device Inserted and assert the ALR T pin to notify the system of the insertion. This bit is cleared by reset. BIT 1, 1394PRSN_STS This bit reﬂects the inverted state of the1394PRx pin associated with this status register. If the1394PRx pin is high, this bit will read cleared. If the1394PRx pin is low (1394 device inserted) this pin will read high. The setting of this bit can generate a device status change event. This bit is cleared by reset. BIT 0, USBPRSN_STS This bit reﬂects the inverted state of the USBPRx pin associated with this status register. If theUSBPRx pin is high, this bit will read cleared. If theUSBPRx pin is low (USB device inserted) this pin will read high. The setting of this bit can generate a device status change event. This bit is cleared by reset.

000 DB32

001 DB20

010 DB13

000 Bay Empty

001 Device Inserted

010 Device Enabled

011 Removal Requested

100 Device Removal Allowed

Special Function Register, $FC The Special Function Register (SFR) allows control of various features not explicitly deﬁned in the Device Bay Speciﬁcation 0.90. This register contains write-once-only bits, which are designed to be written by the system BIOS immediately after power-on. Once written, they become read-only. The upper 24 bits of the SFR are always read as 0. All bits are cleared on reset. BITS 31:8 Reserved for future use. Always read as 0... BITS 31:8 Reserved for future use. Always read as 0. BITS 7:5, ITO[2:0] Bits 7, 6 and 5 deﬁne the Insertion Time-Out (ITO) bits ﬁeld of the SFR. These bits allow the OS/BIOS to specify the amount of time the CDP1020 will wait, from when it detects the insertion of a device until it notiﬁes the OS. The insertion time-out should be used to allow Device Bay devices time to settle mechanically into the bay before they are enabled. The 3-bit ITO field defines the time-out in 8 discrete increments of 800ms (nominal at 4MHz). The table below shows typical time-out values. Please note that these time-out values do not account for the fact that all presence inputs are debounced for 50ms before any time-out period begins. The time-out defaults to 0 after reset. SOL[3:0] The SOL[3:0] bits, along with the SPD bit, control the conﬁguration and duration of the software lock solenoid drive pulse. Once written to, these bits become read-only. If %0000 is written to the SOL[3:0] bits, the solenoid output is put into “level” mode. In level mode, the SFTLOCK output simply follows the state of the corresponding LOCK_CTL bit (see Figure 8). If a nonzero value is written to the SOL[3:0] bits, then the solenoid control output is put into “pulsed” mode. In this mode, the solenoid output is pulsed anytime the LOCK_CTL bit is written from a 1 to a 0 (refer to Figure 8). The length of the pulse is determined by both the value written into the SOL[3:0] bits and the SPD bit. With the SPD bit clear, the solenoid control circuitry is set to output short pulses. In terms of a prescaler, the solenoid pulse width is the value of the SOL[3:0] x 50ms. With the SPD bit set, the solenoid control is in long pulse mode. Here, the prescaler is set to SOL[3:0] x 800ms. The table below shows solenoid pulse widths for all values of SOL[3:0] and the SPD bit. NOTE: Writing to SOL[3:0] bits will clear all LOCK_CTL bits and SFTLOCK outputs. Because these bits in the SFR are write-once- only, this situation will only occur on the ﬁrst write. Subsequent writes to these bits will not cause the LOCK_CTL bits to clear. SPD The SPD bit controls the length of the solenoid pulse when in pulse mode: long pulses If set, short pulses If clear. If the SOL[3:0] bits are clear, the SPD bit has no effect. Bits 31:8 Bits 7:5 Bits 4:1 Bit 1 $000000 ITO[2:0] SOL[3:0] SPD $FC INSERTION TIME-OUT VALUES (NOMINAL AT 4MHz) ITO[2:0] TIME-OUT VALUE 000 0s 001 0.8s 010 1.6s 011 2.4s 100 3.2s 101 4.0s 110 4.8s 111 5.6s SOLENOID PULSE WIDTHS (NOMINAL AT 4MHz) SOL[3:0] SOLENOID PULSE, SPD = 0 SOLENOID PULSE, SPD = 1

0000 LEVEL LEVEL

0001 50ms 0.8ms 0010 100ms 1.6s 0011 150ms 2.4s 0100 200ms 3.2s 0101 250ms 4.0s 0110 300ms 4.8s 0111 350ms 5.6s 1000 400ms 6.4s 1001 450ms 7.2s 1010 500ms 8.0s 1011 550ms 8.8s 1100 600ms 9.6s 1101 650ms 10.4s 1110 700ms 11.2s 1111 750ms 12.0s CDP1020

reset pin (RESET) and an internal power-on reset function. Both are logically OR’ed together internally. Trigger to improve noise immunity. provision for a power-down reset. internal circuits, but not necessarily in order of occurrence.

BCER0 and BCER1 reset to $00000000
BSTR0 and BSTR1 reset to $00000000
SFR reset to $00000000
All PWREN, SFTLOCK, and LED outputs cleared
DBCCR set to two bays, no security locks - $00000002
All Write-Once permissions reset
AD0 and AD1 inputs sampled for I 2C/SMBus address
Internal address pointer reset to $00 State Machine Logic The CDP1020 contains two functionally identical state machine logic blocks, one for each bay. Each of these blocks is responsible for monitoring external Device Bay events (i.e., device insertion, device removal, remove requests), controlling the locking mechanism and power enable signal for each bay, updating the state of the bay in response to OS commands and external events as shown in Figure 9. There are five separate functional states that each bay of the CDP1020 can be in at any one time. Each of the two bay controllers within the CDP1020 functions completely independently of the other. The following sections detail state machine operation in each of the five states, including state transitions, operating system responsibility, and I/O functions. In the following sections, the bay state controller will be referred to generically; that is as a bay “x” controller. Thus, bay “x” has a control register BCERx, a status register BSTRx, and so on. The state of the device bay controller is changed through either hardware events (device inserted, device removed) and software events (OS writes into CDP1020 registers can change the bay state under certain conditions). Interrupt Events An interrupt event is deﬁned as one of the following:
The insertion of a device into a bay with the corresponding DEVSTSCHG_EN bit set
Removal of a device after the insertion time-out in any state other than Removal Allowed and the DEVSTSCHG_EN bit is set
Removal of a device in the Removal Allowed state with both the REMWAKEVT and DEVSTSCHG_EN ﬂags set
User assertion of the REMREQ input when the associated REMREQ_EN bit is set and a device is present in the bay LOCK_CTL SFTLOCK LEVEL MODE SFTLOCK PULSE MODE SOLENOID

FIGURE 8. LOCK_CTL BIT/SFTLOCK OUTPUT

delay time is set at system power on whenever the CDP1020 is initialized by writing the appropriate value into the ITO[2:0] bit field of the SFR. As shown in the SFR text, the insertion time- out delay can range from 0s to 5.6s in increments of 800ms. The feature that makes the CDP1020 insertion time out function different from a simple insertion delay is that the CDP1020 will begin to ﬂash the bay status LED green immediately after the device has been detected (if the DEVSTSCHG_EN ﬂag for the bay is set). This is important because it gives the user instant feedback that the device has been recognized. It is important to note that even though the bay status LED is flashing, the CDP1020 has not responded to the device insertion. During the insertion time out period, the status bits (1394PRSN_STS and USBPRSN_STS) remain clear and the bay state is NOT transitioned in the Device Inserted state. Thus, if the OS were to read the CDP1020 during the insertion time out period, it would not know that a device was in the bay. Once the insertion time out period is over, the CDP1020 will generate an insertion event (assuming the DEVSTSCHG_EN ﬂag is set) and the state controller will enter the Device Inserted state. It is important to note that while waiting for the insertion time out, the CDP1020 has not fully registered the device in the bay. Thus, if the device were forcibly removed during this time, a removal event would not be generated. The CDP1020 would simply reset the insertion time out counter and stop ﬂashing the bay status LED. Bay Empty A bay empty state is defined exclusively as both the presence inputs for the bay ( 1394PRx andUSBPRx) de-asserted. The state of these pins is controlled by the insertion and removal of devices in the bay. As shown in Figure 9, the insertion of a device (and the assertion of one or both of the presence pins) causes the CDP1020 to recognize that a device is in the bay. If the DEVSTSCHG_EN flag for the bay is set, an insertion interrupt event will be generated and the state machine to transition bay state from Bay Empty (%000) to Device Inserted (%001). Typically the Bay Empty state will be returned to from either the Device Inserted state (before the device has been enabled) or the Device Removal Allowed state (after the OS has powered down the device). However, the Bay Empty state can also be entered from Removal Requested and Device Enabled states if the device was forcibly removed from the system. In all cases, if the CDP1020 detects that both presence pins have been deasserted, the Bay Empty state will be entered and the PWREN output for the V ID MOSFET gate driver will be disabled. The bay empty state is reﬂected by the bay state machine by setting BAY_ST[2:0] ﬁeld (bits 6:4 of the bay status register) to %000. The bay empty state can be entered from any of the other four bay states and is entered exclusively through hardware transitions controlled by the CDP1020; OS writing into the BCER cannot change the bay state to Bay Empty. Entering the Bay Empty state from any state other than Removal Allowed will cause the CDP1020 to generate a removal interrupt event if the DEVSTSCHG_EN bit in the BCER is set. A removal event will be generated if the bay was in the Removal Allowed state and both the REMEVTWAK the DEVSTSCHG_EN bits in the BCER are set. In both cases, the CDP1020 will notify the host system via the ALR T pin. In the Bay Empty state the bay status LED (LEDGx and LEDAx) outputs will be off. Device Inserted State The Device Inserted state, %001, is entered in one of two manners. When a device is inserted, the CDP1020 will transition to the Device Inserted state (after the insertion time out period) if the DEVSTSCHG_EN bit for the bay in question is set. In such a case, the CDP1020 will generate an insertion event, set the DEVSTSCHG bit in the BSTR, flash the bay status LED green and notify the OS through the ALR T pin. Alternately, the OS can transition the CDP1020 to the Device Inserted state by writing a %001 to the BAY_STREQ bit ﬁeld in the BCER. This can only be done from any other bay state as long as a device is inserted in the bay. While in the CDP1020 is in the Device Inserted state the OS will typically engage the software controlled lock for the bay, enable V ID to the bay and enumerate the device on its native communication bus. While in this state, the bay status LED will ﬂash green at 1Hz. Device Enabled In the Device Enabled state, the device inserted into the bay has V ID enabled and is fully functional. This state cannot be entered through hardware action; only the OS writing %010 to the BAY_STREQ bits in the BCER can transition the bay state to Device Enabled. In the Device Enabled state, if the presence pins are de- asserted at any time, the CDP1020 hardware will automatically transition the bay state to Bay Empty, clear the PWR_CTL bit and disable the PWRENx outputs. The PWRENx and PWR_CTL states are not affected by the state transitions to the Device Enabled state. While in this state the bay status LED will be solid green. Device Removal Requested The Device Removal Requested state, like the Device Inserted state, can be entered either through an OS write to the BCERx or through hardware actions. Upon the assertion of the bay REMREQ input, the CDP1020 will set the REMREQ_STS bit in the BSTR if there is a device in the bay (i.e., 1394PRSN_STS or USBPRPRSN_STS = 1). A removal request interrupt event will be generated if the CDP1020

the OS writes a %011 to the BAY_STREQ field in the BCERx. While in this state the bay status LED will flash amber at 1Hz. transition the bay state into Device Removal Allowed. of the state of any of the control or status bits. (LEDGx and LEDAx) outputs will be off. the CDP1020 bay state controllers. TABLE 2. HARDWARE EVENT BAY STATE TRANSITION TABLE Power-On Reset Establish initial state. necessarily cause DEVSTSCHG to be set. mechanism may have been overridden. Completion of normal device removal sequence.

TABLE 3. SOFTWARE ACTION BAY STATE TRANSITION TABLE Removal Requested 011b -> BAY_STREQ Unexpected OS behavior. 100b -> BAY_STREQ Unexpected OS behavior. removal through the UI before the device was enabled. sufficient operational power, etc. Device Enabled Device Inserted 001b -> BAY_STREQ Unexpected OS behavior. Device Enabled Removal Requested 011b -> BAY_STREQ User request device removal through the UI. 100b -> BAY_STREQ Unexpected OS behavior. Removal Requested Device Inserted 001b -> BAY_STREQ Unexpected OS behavior. removal request through the UI. 100b -> BAY_STREQ OS has completed the device removal sequence. Device Inserted 001b -> BAY_STREQ User has requested to “re-use” the device through the UI. Device Enabled 010b -> BAY_STREQ User has requested to “re-use” the device through the UI. enabled on its native bus(es). Removal Requested 011b -> BAY_STREQ Unexpected OS behavior.

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2 COLOR,

FIGURE 18. TYPICAL CDP1020 SYSTEM HARDWARE CONNECTIONS - PiiX4 BASED INTEL ARCHITECTURE PLATFORM (ONLY BAY

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Summary

SMBus/I2C ACPI Dual Device Bay Controller April 1999

Description