CDK3400 CADEKA | Alldatasheet

Document overview

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Technical content

CDK3400/CDK3401 10-bit, 100/150MSPS, Triple Video DACs Rev 1B Data Sheet ©2008 CADEKA Microcircuits LLC www.cadeka.com Ampl ify th e Human Exp eri ence CDK3400/CDK3401 10-bit, 100/150MSPS, Triple Video DACs

features

n 150 megapixels per second n ±0.1% linearity error n Sync and blank controls n 1.0Vpp video into 37.5Ω or 75Ω load n Internal bandgap voltage reference n Double-buffered data for low distortion n TTL-compatible inputs n Low glitch energy n Single +5V power supply

applications

– RGB – YCBCR – Composite, Y, C n Multimedia systems n Image processing n True-color graphics systems (1 billion colors) n Broadcast television equipment n High-Definition Television (HDTV) equipment n Direct digital synthesis General Description CDK3400/3401 products are low-cost triple D/A converters that are tailored to fit graphics and video applications where speed is critical. Two speed grades are available: CDK3400 at 100MSPS and CDK3401 at 150MSPS. TTL-level inputs are converted to analog current outputs that can drive 25-37.5Ω loads corresponding to doubly-terminated 50-75Ω loads. A sync current following SYNC input timing is added to the IO G output. BLANK will override RGB inputs, setting IO G, IOB and IO R currents to zero when BLANK = L. Although appropriate for many applications, the internal 1.235V reference voltage can be overridden by the VREF input. Few external components are required, just the current reference resistor, current output load resistors, and decoupling capacitors. Package is a 48-lead TQFP. Fabrication technology is CMOS. Performance is guaranteed from 0 to 70°C. Block Diagram

Ordering Information

Part Number Package Pb-Free RoHS Compliant Operating Temp Range Packaging Method Package Quantity CDK3400CTQ48 TQFP-48 Yes Yes 0°C to +70°C Tray 250 CDK3400CTQ48Y TQFP-48 Yes Yes 0°C to +70°C Tray 1,250 CDK3401CTQ48 TQFP-48 Yes Yes 0°C to +70°C Tray 250 CDK3401CTQ48Y TQFP-48 Yes Yes 0°C to +70°C Tray 1,250 Moisture sensitivity level for all parts is MSL-3. 10-bit D/A Converter SYNC CLOCK G9-0 COMP +1.235V Ref IOG BLANK 10-bit D/A Converter B9-0 IOB 10-bit D/A Converter R9-0 IOR REF REF SYNC R V

©2008 CADEKA Microcircuits LLC www.cadeka.com 2 Data Sheet CDK3400/CDK3401 10-bit, 100/150MSPS, Triple Video DACs Rev 1B Pin Configuration TQFP-48 BLANK V DD NC RREF VREF COMP IOG IOR VDD VDD IOB GND GND NC NC NC SYNC 11 CLOCK26 B9 23 R038 TQFP CDK3400/3401 Pin Assignments Pin No. Pin Name Description clock and pixel i/o

26 CLK Clock Input

47-37 R9-0 Red Pixel Data Inputs 48, 9–1 G9-0 Green Pixel Data Inputs 23–14 B9-0 Blue Pixel Data Inputs controls

11 SYNC Sync Pulse Input

10 BLANK Blanking Input

33 IOR Red Current Output

32 IOG Green Current Output

29 IOB Blue Current Output

35 VREF Voltage Reference Output/Input

36 RREF Current-Setting Resistor

34 COMP Compensation Capacitor

12, 30, 31 VDD Power Supply 27, 28 GND Ground

©2008 CADEKA Microcircuits LLC www.cadeka.com 3 Data Sheet CDK3400/CDK3401 10-bit, 100/150MSPS, Triple Video DACs Rev 1B Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. Parameter Min Max Unit Power Supply Voltage VDD (Measured to GND) -0.5 7.0 V Inputs Applied Voltage (measured to GND)(2) -0.5 VDD + 0.5 V Forced Current(3,4) -10.0 10.0 mA Outputs Applied Voltage (measured to GND)(2) -0.5 VDD + 0.5 V Forced Current(3,4) -60.0 60.0 mA Short Circuit Duration (single output in HIGH state to GND) Infinite sec Temperature Operating, Ambient -20 110 °C Junction 150 °C Lead Soldering (10 seconds) 300 °C Vapor Phase Soldering (1 minute) 220 °C Storage -65 150 °C notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. Recommended Operating Conditions Symbol Parameter Min Typ Max Unit VDD Power Supply Voltage 4.75 5.0 5.25 V fS Conversion Rate CDK3400 100 MSPS CDK3401 150 MSPS tPWH CLK Pulsewidth, HIGH CDK3400 3.1 ns CDK3401 2.5 ns tPWL CLK Pulsewidth, LOW CDK3400 3.1 ns CDK3401 2.5 ns tW CLK Pulsewidth CDK3400 10 ns CDK3401 6.6 ns tS Input Data Setup Time 1.7 ns th Input Date Hold Time 0 ns VREF Reference Voltage, External 1.0 1.235 1.5 V CC Compensation Capacitor 0.1 µF RL Output Load 37.5 Ω VIH Input Voltage, Logic HIGH 2.0 VDD V VIL Input Voltage, Logic LOW GND 0.8 V TA Ambient Temperature, Still Air 0 70 °C

©2008 CADEKA Microcircuits LLC www.cadeka.com 4 Data Sheet CDK3400/CDK3401 10-bit, 100/150MSPS, Triple Video DACs Rev 1B

Electrical Characteristics

(TA = 25°C, VDD = +5V, VREF = 1.235V, RL = 37.5Ω, RREF = 540Ω; unless otherwise noted) symbol parameter conditions Min typ Max units IDD Power Supply Current(1) VDD = 5.25V, TA = 0°C 125 mA PD Total Power Dissipation(1) VDD = 5.25V, TA = 0°C 655 mW RO Output Resistance 100 kΩ CO Output Capacitance IOUT = 0mA 30 pF IIH Input Current, HIGH VDD = 5.25V, VIN = 2.4V -5 µA IIL Input Current, LOW VDD = 5.25V, VIN = 0.4V 5 µA IREF VREF Input Bias Current 0 ±100 µA VREF Reference Voltage Output 1.235 V VOC Output Compliance Referred to VDD -0.4 0 +1.5 V CDI Digital Input Capacitance 4 10 pF notes: 1. 100% tested at 25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data. Switching Characteristics (TA = 25°C, VDD = +5V, VREF = 1.235V, RL = 37.5Ω, RREF = 590Ω; unless otherwise noted) symbol parameter conditions Min typ Max units tD Clock to Output Delay VDD = 4.75V, TA = 0°C 10 15 ns tSKEW Output Skew 1 2 ns tR Output Risetime 10% to 90% of Full Scale 3 ns tF Output Falltime 90% to 10% of Full Scale 3 ns notes: 1. 100% production tested at +25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data. System Performance Characteristics (TA = 25°C, VDD = +5V, VREF = 1.235V, RL = 37.5Ω, RREF = 590Ω; unless otherwise noted) symbol parameter conditions Min typ Max units INL Integral Linearity Error ±0.1 ±0.25 %/FS DNL Differential Linearity Error ±0.1 ±0.25 %/FS EDM DAC to DAC Matching 3 10 % PSRR Power Supply Rejection Ratio 0.05 %/% notes: 1. 100% production tested at +25°C. 2. Parameter is guaranteed (but not tested) by design and characterization data.

Table 1. Output Voltage vs. Input Code, SYNC and BLANK, VREF = 1.235V, RREF = 590Ω, RL = 37.5Ω Figure 1. CDK3400/3401 Timing Diagram

reflection induced jitter, overshoot, and undershoot. istered on the rising edge of CLK. and BLANK are registered on the rising edge of CLK. Figure 2. Normal Output Levels BLANK gates the D/A inputs and sets the pedestal voltage. inputs and the pedestal are disabled. be used only during the blanking interval. nected between RREF and GND. other 75Ω termination resistor at the far end of the cable. a net resistive load of 37.5Ω. resistor on RREF should be doubled. pulses may be added to the Green D/A output.

©2008 CADEKA Microcircuits LLC www.cadeka.com 7 Data Sheet CDK3400/CDK3401 10-bit, 100/150MSPS, Triple Video DACs Rev 1B Current-Setting Resistor - RREF Full-scale output current of each D/A converter is deter - mined by the value of the resistor connected between RREF and GND. Nominal value of RREF is found from: RREF = 9.1 (VREF/IFS) where IFS is the full-scale (white) output current (in amps) from the D/A converter (without sync). Sync is 0.4 * IFS. D/A full-scale (white) current may also be calculated from: IFS = VFS/RL Where VFS is the white voltage level and R L is the total resistive load (Ω) on each D/A converter. VFS is the blank to full-scale voltage. Voltage Reference All three D/A converters are supplied with a common voltage reference. Internal bandgap voltage reference voltage is +1.235V with a 3kΩ source resistance. An external voltage reference may be connected to the VREF pin, overriding the internal voltage reference. A 0.1µF capacitor must be connected between the COMP pin and VDD to stabilize internal bias circuitry and ensure low-noise operation. Voltage Reference Output/Input - VREF An internal voltage source of +1.235V is output on the VREF pin. An external +1.235V reference may be applied here which overrides the internal reference. Decoupling VREF to GND with a 0.1µF ceramic capacitor is required. Power and Ground Required power is a single +5.0V supply. To minimize power supply induced noise, analog +5V should be connected to VDD pins with 0.1µF and 0.01µF decoupling capacitors placed adjacent to each VDD pin or pin pair. The high slew-rate of digital data makes capacitive cou - pling to the outputs of any D/A converter a potential problem. Since the digital signals contain high-frequency components of the CLK signal, as well as the video out - put signal, the resulting data feedthrough often looks like harmonic distortion or reduced signal-to-noise perfor- mance. All ground pins should be connected to a common solid ground plane for best performance.

For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved. caDeKa Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free) Data Sheet Ampl ify th e Human Exp eri ence CDK3400/CDK3401 10-bit, 100/150MSPS, Triple Video DACs Rev 1B Mechanical Dimensions